This will allow moving mca_check_all_banks to mca_common.c.
Change-Id: I58e100c1447907bab984a2fdff6c6e0181910c23
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This aligns the mca_check_all_banks implementation in the common mca.c
with the one in the common mcax.c file. Do the MCA bank count check
before the !is_warm_reset() check, so that a mismatch also gets printed
on the cold boot path.
Change-Id: Idbd3e9ce9c7483f84f87adab7adac47335cd59aa
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Since those functions are implemented and used only inside the common
MCA(X) code, there's no need to have them in the header file that gets
included in the SoC-specific code.
Change-Id: Ia84e149d67ac7d80de595379c73a6cf08730719d
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
For Cezanne stubs are added for the functions that the SoC-specific code
needs to provide. Since the mca_is_valid_bank stub on Cezanne always
returns false, the checks get skipped for it at the moment. The actual
functionality will be added in a later patch.
Change-Id: Ic31e9b1ca7f8fac0721c95935c79150d7f774aa4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
To factor out the rest of the common MCAX code, mca_bank_name[] may only
be accessed by accessor functions, so implement this for the last place
that still accessed mca_bank_name[] directly.
Change-Id: Ic6548d3ceeb9c00ad344fc0bb3d97893e17a43a9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56294
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Alder Lake SoC has virtual GPIOs for community 1 which was being
programmed by FSP and hence was skipped by coreboot. As part of
moving most of the GPIO programming to coreboot, we're skipping this
programming in FSP now.
TEST=Check register offset to see if programming is correct.
Change-Id: I4d48553d14465df50e5aaaf27ab26c6a1b70d4cf
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55270
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Fast Read Dual Output and Fast Read Dual I/O commands are
practically identical, the only difference being how the read address is
transferred (saving a whooping 2 bytes which is totally irrelevant for
the amounts of data coreboot tends to read). We originally implemented
Fast Read Dual Output since it's the older command and some older
Winbond chips only supported that one... but it seems that some older
Macronix parts for whatever reason chose to only support Fast Read Dual
I/O instead. So in order to make this work for as many parts as
possible, I guess we'll have to implement both. (Also, the Macronix
device ID situation is utter madness with different chips with different
capabilities often having the same ID, so we basically have to make a
best-effort guess to strike a trade-off between fast speeds and best
chance at supporting all chips. If this turns out to be a problem later,
we may have to add Kconfig overrides for this or resort to SFDP parsing,
although that would defeat the whole point of trying to be fast.)
BUG=b:193486682
TEST=Booted CoachZ (with Dual I/O)
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ia1a20581f251615127f132eadea367b7b66c4709
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
We may want to use that flash vendor on future variants.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I2c0fa87fd3f8de8f928e5f41eae2a78204597b5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
To be able to enable & disable PSP_verstage in the saved .config file,
the symbol VBOOT_STARTS_BEFORE_BOOTBLOCK needs to be changed from a
select to a default with a prompt.
BUG=182477057
TEST=Build, get PSP_verstage, disable VBOOT_STARTS_BEFORE_BOOTBLOCK,
verify that VBOOT_STARTS_IN_BOOTBLOCK is set.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Iba735f33f9b079c9868ef2fff099c5298ff72b6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56289
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Initially APL was considered as IFDv2 platform irrespective being
added into ifd_2_platforms[], hence commit hash 621ed4c had migrated
APL into IFDv1 which break its FLMSTR1/FLMSTR2/FLMSTR3 Read/Write
access. This change adds APL into the list of IFDv2 platforms to fix
booting issue on the LeafHill board.
Change-Id: Ied59ddb2fe05b421266a6b119fd6eab17b8beedc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56300
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rick Lee <rick.lee@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This will allow factoring out and moving check_mca() to soc/amd/common.
Change-Id: I92c7657baef17c248a5aef1eda268e9647502837
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56280
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch changes the way how the not implemented MCA bank 3 gets
skipped. For the not implemented bank 3 the name gets set to NULL
resulting in mca_is_valid_bank returning false causing the bank to get
skipped. This is a preparation for commonizing the MCA(X) handing in the
soc/amd sub-tree.
Change-Id: I40d6a6752504d804c45b445fce7e763e80161211
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
In mca_check_all_banks only check valid MCA banks for errors. This
aligns the Picasso code a bit more with the Stoneyridge code base which
will be updated in a follow-up patch. This is a preparation for
commonizing the MCA(X) handing in the soc/amd sub-tree.
Change-Id: I0c7f3066afd220e6b8bf8308a321189d7a2679f6
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56275
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The length of mca_bank_name should match the return value of
mca_get_bank_count which gets the number of MCA banks from an MSR.
TEST=No error message on serial console on amd/mandolin
Change-Id: Ibdad51a7ef27266e110dfbb43188361952618342
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56274
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Also use array indices for the initialization.
TEST=Checked with the public Picasso PPR #55570-B1 Rev 3.16
Change-Id: I10a65210da73e64b67d613609fcc0f9a245a81fb
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56273
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A regular assignment works just as well and also allows type-checking.
It also avoids a common mistake where `sizeof` is applied to a pointer
to obtain the size of the data it points to, without dereferencing it.
Found-by: Coverity CID 1458231
Change-Id: I7ed05322c3c911f3da4145f81e4d9760a275fec2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56265
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ESPI & LPC keywords were added for the zork program, but it was
found that they weren't needed, so they were never used. The previous
patch removes them from sconfig, so now they aren't needed in coreboot.
BUG=None
TEST=Build
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I9ae7817bb63d69ee272103b2d1186f125e188950
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56278
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ESPI & LPC keywords were added for the zork program, but it was
found that they weren't needed, so they were never used.
BUG=None
TEST=Build
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I3a78afc55477d62eac8056e2ca4bcdd3ab12ea47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56197
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to the AMD FCH architects, we should be using the default
value for the NO_HOG bit. This fixes a problem where the SPI DMA no
longer functions after the LPC init runs.
BUG=b:179699789, b:192373221
TEST=Boot guybrush and see SPI DMA working
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If015869657f36d3533f4ab9ebd1f54b0d4eb283a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
There is no technical reason this needs to be done in romstage. Moving
it into ramstage allow us (in future CLs) to use threads to pre-load
the apob from SPI.
BUG=b:179699789
TEST=Boot and Ezkinil and Guybrush and verify APOB update still work
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I960437ff4400645de5a3e7447fcdbc52de85943e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
The %p format specifier already prints out 0x, so remove the 0x from the
string. I also updated the other format specifiers to use the %# syntax
to print out the 0x.
BUG=b:179699789
TEST=see correct format.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5b00d2c06687e549f69486eb5e18f7bed560b2ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56225
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently the MCA support for Cezanne only clears the MCA status
registers. The MCA error handling and BERT table generation will be
added in subsequent patches.
Change-Id: Ib9b5174186c28c8c82f57ffd8936c8dad4e63c5b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add this macro to be able to conveniently access the MC_CTL_MASK
register for each MCA bank. Also drop the unused definitions for
MC1_CTL_MASK and MC4_CTL_MASK.
Change-Id: I23ce1eac2ffce35a2b45387ee86aa77b52da5494
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This MSR isn't an architectural MSR, so it shouldn't be in the common
x86 MSR definition header file. From family 17h on this register has
moved to a different location.
Change-Id: Id11d942876da217034e6f912b1058f00bd15c22c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Since we can use both the old MCA registers and the new MCAX registers
to access the MCA status registers, we can use the common
mca_clear_status function here.
Change-Id: I9ddcc119eca2659361b1496fd7ffe124fb323d26
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
In multiple locations within the coreboot tree all available
IA32_MC_STATUS registers are cleared, so add this to the common code to
avoid duplication of code.
Change-Id: I04af23c16021b0ce90f7105f7a3856bd26ffa736
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56258
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Building nvramcui with i386-elf-gcc (coreboot toolchain
v2021-04-06_7014f8258e) 8.3.0 and Link Time Optimization (LTO) enabled
in libpayload (`CONFIG_LP_LTO=y`) fails with the error below.
LPGCC nvramcui.bin
curses/PDCurses/pdcurses/refresh.c: In function 'wrefresh':
curses/pdcurses-backend/pdcdisp.c:217:4: error: 'bg' may be used uninitialized in this function [-Werror=maybe-uninitialized]
curses/pdcurses-backend/pdcdisp.c:214:18: note: 'bg' was declared here
curses/pdcurses-backend/pdcdisp.c:217:4: error: 'fg' may be used uninitialized in this function [-Werror=maybe-uninitialized]
curses/pdcurses-backend/pdcdisp.c:214:14: note: 'fg' was declared here
lto1: all warnings being treated as errors
lto-wrapper: fatal error: i386-elf-gcc returned 1 exit status
compilation terminated.
/opt/xgcc/lib/gcc/i386-elf/8.3.0/../../../../i386-elf/bin/ld.bfd: error: lto-wrapper failed
collect2: error: ld returned 1 exit status
`pair_content()` returns in case `PAIR_NUMBER(attr)` is invalid, so
guard the usage of `serial_set_color()`.
if (pair < 0 || pair >= COLOR_PAIRS || !fg || !bg)
return ERR;
Note, building with x86_64-linux-gnu-gcc-10 (Debian 10.2.1-6) 10.2.1
20210110 does *not* fail.
Change-Id: Ic63e34f2b5bc9f826db37597bebc6b20542481d7
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch replaces the usage of GPR (General Purpose Registers) like
ECX and EBX for backing up data way and non-eviction mask with SPR
(Special Purpose Registers) EDI and ESI.
Purpose of this change is to ensure the safety while developers might
use ECX often while doing rdmsr/wrmsr rather than making use of EDI.
TEST=Able to boot JSL and TGL platform without any hang using eNEM.
Change-Id: I12e0cb7bb050e4f7b17ecf30108db335d1d82ab7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56161
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This devicetree option is never set and never used. Drop it.
Change-Id: I9cd4733746849728b2b9f85793eace9191a97f49
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
SaGv is only available on ULT/ULX processors, which use PCH-LP. Given
that the Siemens Chili board selects `SOC_INTEL_CANNONLAKE_PCH_H`, it
does not use ULT/ULX processors, and thus does not support SaGv. Drop
the `SaGv` setting from the devicetrees, as it has no effect.
Change-Id: I5be518cce08206ad149efd1665e44a7111b24202
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56205
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Felix Held