Now pci_domain_ops in chip.c can also be marked as static.
Change-Id: I5e481fe311c9db4aacfd94bbf671edf679528946
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Since config_of() calls die() if dev or dev->chip_info are NULL,
config_of_soc() will either return a non-NULL pointer or won't return.
Change-Id: I6de6bb1610e823af215436c94ff1a78ff6b86b78
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Since config.c also gets linked into verstage on PSP and not only into
the stages running on the x86 cores, use all-y instead of adding
config.c to all classes separately.
Change-Id: Icacb13e73e80e6f3d8c2141784702fb895daf7db
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The corresponding MSRs of all AMD family 17h and 19h CPUs/APUs match the
code.
Change-Id: I29cfef5d8920c29e36c55fc46a90eb579a042b64
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The next patch will add a tsc subfolder that might end up containing
code that is guarded with different Kconfig options, so move the guards
into the Makefiles in the subfolders instead of guarding the inclusion
of the Makefiles in the subdirectories with the corresponding Kconfig
option.
Change-Id: Iafc867eb9adcb23e9a4878cc381684db6f9692d5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Remove SOC_INTEL_COMMON_BLOCK_HDA from mainboards Kconfig since it is
selected by their SoC soc/intel/cannonlake.
Change-Id: I9597746a217575b42f6325998b948e16b452231a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48289
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move mainboard/gpio.h to variant/gpio.h and rename its methods to make
clear that these methods are implemented on variant level.
Change-Id: Ib4e7ec948ca4d019ad82ebc5abe39fc408281cf4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48299
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add variant_configure_early_gpios() configuring early GPIOs to make the
difference clear.
Change-Id: I6e7c8c32963c9eeab4399947dac511442987cb45
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48298
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move mainboard/gpio.h to variant/gpio.h and rename its methods to make
clear that these methods are implemented on variant level.
Change-Id: Ibcb6322067285984bad70761fce34cfcb6ed8e0f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48297
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move mainboard/gpio.h to variant/gpio.h and rename its methods to make
clear that these methods are implemented on variant level.
Change-Id: I1ae9b54ed683000f65323b11747ce3280a1c7f2a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48296
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Don't make the default paths to AMD blobs depend on USE_AMD_BLOBS. This
way we get error messages about the missing files when the blobs repos
aren't checked out.
Change-Id: I754fdc5e1414c8a3dc88b364bcfbea9a26b59eb0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Allow to specify which signature is to be checked.
Change-Id: Ica874b1c4283fdb8dbd702c34ccb3315a2cf160d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
DeltaLake Open System Firmware stack (FSP/coreboot/Linuxboot) has
reached EVT exit parity. Update the documentation accordingly.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I7cce855d207a53b1d3cd497b74cdc0b00027a3ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Create the storo variant of the waddledee reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.3.1).
BUG=b:174284884
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_STORO
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I5ad41e0b2bc95b44733a2ad3c543267f3f56f9e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Provide get_mmu_ranges() for ARM64 to let payloads could get
MMU ranges for all used memory regions.
BUG=b:171858277
TEST=Build in x86, arm, arm64.
emerge-zork libpayload depthcharge
emerge-nyan libpayload depthcharge
emerge-asurada libpayload depthcharge
Signed-off-by: Meng-Huan Yu <menghuan@google.com>
Change-Id: I39b24aefc9dbe530169b272e839d0e1e7c697742
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The CPU core clock divisor ID needs to be in the range from 8 to 0x30
including both numbers.
TEST=Compared with Picasso's PPR #55570
Change-Id: Ie5ee342d22294044a68d2f4b2484c50f9e345196
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Without the EC blob being present in the SPI flash, the board won't even
power up.
Change-Id: Ia3c50e86414bbc707bc33e28c636196c1be2f1e6
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This is an adapted copy of mainboard/example/min86 that is currently
only used for Jenkins to test the SoC code in soc/amd/cezanne and isn't
expected to reach boot block at the moment. It will be extended in
future follow-up commits.
Change-Id: I6806955952fbfa3227294cfc44fdf9156140e933
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This is based on the minimal example code in soc/example/min86 and was
adapted to use the AMD non-CAR boot block and the common AMD PCI MMCONF
support.
In its current state this won't even reach the boot block, but will pass
the build bot. The missing parts for that will be added in future
patches. This is an attempt to not go the usual route to create a copy
of a previous SoC generation and the make changes to the code to work
for the new SoC, but to start from a nearly empty directory and then add
the actual code stage by stage and component by component.
Change-Id: I70aeb9ae010e943abfa667a0ea95c6fa9f15b7f5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
DPTF paramerters form thermal team.
Set PL1 Min/Max 15/25W, PL2 Min/Max 40/49W.
BUG=b:174514010
BRANCH=puff
TEST=build image and verified by thermal team.
Change-Id: I9e6c4bae181e87f87f2e92337bb9d989f5b7d955
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
set APU_EDP_BL_DISABLE(GPIO_85) to low to avoid the VARY_BL fast than
APU_DP_BLON.
BUG=b:171954512
BRANCH=zork
TEST=validate the panel sequence with scope.
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ia6d3f4335583bb2d91a6bce96d89cff84247d0ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Create the copano variant of the volteer reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.3.1).
BUG=b:174413884
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_COPANO
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ib06625f492f68a6a6f5c6b382772b68f1eb681ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Use a wrapper code that does nothing on x86_32, but drops to protected
mode to call into FSP when running on x86_64.
Tested on Intel Skylake when running in long mode. Successfully run the
FSP-M which is compiled for x86_32 and then continued booting in
long mode.
Change-Id: I9fb37019fb0d04f74d00733ce2e365f484d97d66
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48202
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds a helper function for long mode to call some code in protected
mode and return back to long mode.
The primary use case is to run binaries that have been compiled for
protected mode, like the FSP or MRC binaries.
Tested on Intel Skylake. The FSP-M runs and returns without error while
coreboot runs in long mode.
Change-Id: I22af2d224b546c0be9e7295330b4b6602df106d6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
According to the spec provided by Bayhub, the 3.3V power rail must be enabled at least 100ms before reset is released.
To ensure this, set the power enable signal in the bootblock GPIO table.
BUG=b:173676531
BRANCH=firmware-volteer-13521.B
TEST=Built and booted into OS, test USB function normally.
Change-Id: I0c536f36c138ace93766f3024f6ec5d47b38269f
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47799
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use a new driver for the SX9324 proximity detector device.
This is first draft settings, will modify it after fine tuning.
BUG=b:172397658
BRANCH=zork
TEST=run "i2cdump -y -f 0 0x28" and checked all registers are expected.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I869d0b6640247099ca489e96ed94e03811a04bf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47867
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Export all registers that driver is looking for. And put in alphabetic order.
The missing registers for kernel v5.4 sx93xx are:
reg_irq_msk
reg_irq_cfg0
reg_irq_cfg2
reg_afe_ph0/1/2/3
BUG=b:172397658
BRANCH=zork
TEST=Build passed
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ic9d7a959b1769b6846bba302e3aeab9a3a1cedac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47866
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Latest HW schematic add LTE_RST pin to control module power sequence.
BUG=b:173490220
BRANCH=zork
TEST=measure the waveform is meet the LTE module spec.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I0f0a35a905d711dd8d17dea2ae82a8dfa1fa05ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Enable Acoustic noise mitigation for drawcia and set slew rate to 1/4
which is calibrated value for the board. Other values like PreWake,
Rampup and RampDown are 0 by default.
BUG=b:162192346
BRANCH=dedede
TEST=Correct value is passed to UPD and Acoustic noise test passes.
Change-Id: Iadcf332d59dac2ba191b82742a18a1ab326940d1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This patch exposes acoustic noise mitigation related UPDs/configuration
to be filled from devicetree.
For each variant, we might have different values for various parameters.
Filling it from devicetree will allow us to fill separate values for
each board/variant.
Note that since JasperLake only has one VR, we're only filling index 0
for slew rate and FastPkgCRampDisable.
BUG=b:162192346
BRANCH=dedede
TEST=code compilation is successful and values from devicetree are
getting reflected in UPDs
Change-Id: Id022f32acc3fd3fe62f78e3053bacdeb33727c02
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Don't use the common block acpi.h when we aren't using the
COMMON_ACPI config. Fixes a dependency build issue in an upcoming
commit.
Change-Id: I3b80f7bbdf81e594fdde5b750c666edd8ca7268d
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
The new CBFS stack will log messages for found files but leaves error
messages up to the caller. This patch adds appropriate generic error
messages to cbfs_lookup(), matching the behavior of the old CBFS stack
for not found files.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I8cf44026accc03c466105d06683027caf1693ff0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The GPIO controller on Picasso has 4 banks of GPIOs with a size of 256
bytes each, so increase the reserved size to match the hardware.
Also replace the base GPIO address with the corresponding define.
Change-Id: I453f1c531d612a0e82ee0d91762fec6cdb2b8556
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Initiate device tree based on latest schematic.
BUG=b:174266035
TEST=Build Test
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia94119cb6d7eff6ea13c7d6a7dfd6ce891f706fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add implementation of EC smihandler
BUG=b:174266035
TEST=Build Test
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I211f5755ff44514ab7ab4083f684ddd88c23fe48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48115
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable building for Chrome OS and add associated ACPI configuration.
BUG=b:174266035
TEST=Build Test
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I5311879a127a2c8da1bbb086449019d932d57b72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Felix Held