All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
northbridge/intel/i855
Mainboards:
mainboard/lanner/em8510
Change-Id: Ic9ba0ba7e2b6e602a5749cc531dd705c49e3f08d
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
cpu/amd/geode_gx2
northbridge/amd/gx2
southbridge/amd/cs5535
Mainboards:
mainboard/amd/rumba
mainboard/lippert/frontrunner
mainboard/wyse/s50
Change-Id: I81c130f53bbfa001edbfdb7a878ef115757f620c
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
If the DRAM does *not* actually overlap the PCI space, the remap code
notices it is the case, but for some reason proceeds with the remapping,
attempting to remap a negatively sized chunk. Bummer.
With a single 1024M (two ranks of 512M) module:
Nothing to remap
Mem remapping enabled
Remapstart 5120(MB)
Remapend 6144(MB)
Top of RAM 1024MB
New top of RAM 2560MB
Wrote remap map a0101
Mem remapping enabled
Remapstart 4096(MB)
Remapend 2560(MB)
New top of memory is at 2560MB
Needless to say, subsequent ram_resource() ruins the memory map for the
OS -- Linux won't boot without a mem= argument and memtest quickly.
TEST=memtest and Linux boot on HP t5550 with 1024M of memory
Change-Id: Ic221723a26c5d1a03bf34c7722b0abe115f456ba
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/22271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This is required for Flashrom to work well.
Change-Id: Id756d86a7f3b34f816ea7a7ed78f159512f550d5
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/22258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Especially on ICH7 failing to do so results in i2c block read being
unusable. On ICH10 this problem doesn't manifest itself that much.
This moves disabling the watchdog reboot to the northbridge code like
i945 (even though it technically is southbridge stuff).
TESTED on Intel DG41WV: hacking on raminit is much nicer since no
need to do a hard power down for +4s are needed to clear the timeouts.
Change-Id: Icfd3789312704f61000a417f23a121d02d2e7fbe
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
gma.c of Nehalem was copied from Sandy/Ivy Bridge, so fix it there too.
Tested on lenovo/x230. Since both the bit that was masked wrongly and the
one that wasn't masked, but sould have been, are 0, the behaviour on
lenovo/x230 doesn't change.
Change-Id: I5f51c4929df83f948fcb7dc06e07ac3cc4ccf4f2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/22596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
These were forgotten when updating the caller and resulted in build
failures for every but the NGI path.
Change-Id: I2490a3b4dca6c248eb37f43aa676ae619afdbfc7
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This is mostly written from scratch and uses common spd ddr2 decode
functions.
This improves the following:
* This fixes incorrect CAS/Freq detection on DDR2;
* Fixes tRFC computation; tRFC == 78 is a valid timing which is
excluded and 0 ends up being used; (TESTED)
* Timings selection does not use loops;
* Removes ddr3 spd decode and is re-added in follow-up patches using
common ddr3 spd functions;
* Raminit would bail out if a dimm was unsupported, now in some cases it
just marks the dimm slot as empty;
* It dramatically reduces stack usage since it does not allocate 4
times 256 bytes to store full SPDs, amongs other unused things that
were stored in sysinfo;
* Reports when no dimms are present;
* Uses i2c block read to read SPD which is about 5 times faster than
bytewise read, with a fallback to smbus mode in case of failure,
which does seem to happen when the system is forcefully powered
off.
Change-Id: I760eeaa3bd4f2bc25a517ddb1b9533c971454071
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This fixes some bitwise logic errors that caused the coarse offset not
to be programmed.
This fixes a regression introduced by 6d7a8c
"nb/intel/x4x/raminit: Rework receive enable calibration"
where the coarse offset doesn't get programmed anymore.
TESTED on Foxconn g41s-k on a DIMM where the final DQS receive enable
delays are close but above and below the edge of a coarse delay setting.
Change-Id: I41869815f782a2ea1178bdea006e3a7587441323
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Corrects MBSC/MBFS programming when initializing DRAM on boards with both
3 and 4 DIMM slots.
Reformats comments to current coreboot standards.
Drops some romcc "optimizations" no longer necessary.
Boot tested on asus/p2b-ls, where it fixes a memory related hang after
SeaBIOS resets the board with nothing to boot from.
Change-Id: Ib8c21489338643e13f69bd58008d14733796d4d0
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/22687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This partially reverts 2510e2aa "northbridge/intel/i3100: Unify UDELAY
selection" which moved all supported boards from UDELAY_TSC to
UDELAY_IO. Since UDELAY_IO is the default this changes nothing.
Change-Id: I42856e5929a7ba047987414a25cd0ae9712434a7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22173
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Simplifies our C interface function gma_gfxinit(), due to the following
changes:
* *libgfxinit* knows about the underlying PCI device now and can
probe MMIO addresses by itself.
* The framebuffer mapping is now completely handled inside the
library where we validate that we neither overflow
- the stolen memory,
- the GTT address space, the GTT itself nor
- the aperture window (i.e. resource2 of the PCI device)
that we use to access the framebuffer.
Other changes:
* Fixes and a quirk for DP training.
* Fix for DP-VGA adapters that report an analog display in EDID.
* Fixes for Skylake support with coreboot.
* DDI Buffer drive-strength configuration for Haswell, Broadwell and
Skylake.
* `gfx_test` can now be run from X windows (with glitches).
* Compatibility with GCC 7 and SPARK GPL 2017.
TEST=Booted lenovo/t420 and verified that everything works as usual.
Change-Id: I001ba973d864811503410579fd7ad55ab8612759
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The current header `i915.h` is too invasive to be used everywhere where
we want to use *libgfxinit*.
Change-Id: Iba57256d536e301e598d98182448d2daa1bf9a89
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Port the ACPI opregion implementation that resides in
drivers/intel/gma to older platforms. It allows to include a vbt.bin and
allows GNU/Linux to load the opregion as ASLB is being set.
Windows' Intel will likely ignore it as it relies on legacy VBIOS
to be loaded at 0xc0000.
Change-Id: Ifc9fc52d84dcbb0da577e61467ece8a48752f44b
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit just moves the vboot sources into
the security directory and fixes kconfig/makefile paths.
Fix vboot2 headers
Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
XMP profiles can have a restriction on max supported DIMMs per channel,
but many configurations work with more DIMMs.
This is relevant on mainboards with 2 DIMM slots per channel (usually 4
in total). Populating both slots with DIMMs that support XMP profiles only
with 1 DIMM per channel turns off said XMP profiles.
TEST=On a system with two DIMM slots per channel populate both slots on
one channel and ensure that DIMMs run with XMP profiles enabled.
Change-Id: I1f22d981afcef0ee73785823b0a943cf3d3564e3
Signed-off-by: Vagiz Trakhanov <rakkin@autistici.org>
Reviewed-on: https://review.coreboot.org/21841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
DRAM Controller is always 00.0. No need to check its PCI ID.
Change-Id: I9c5f3e5658905e464491579f8da01aa6a03bd3b7
Signed-off-by: Vagiz Tarkhanov <rakkin@autistici.org>
Reviewed-on: https://review.coreboot.org/21754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Port the ACPI opregion implementation that resides in
drivers/intel/gma to older platforms.
It allows to include a vbt.bin and allows GNU/Linux to load the
opregion as ASLS is being set.
Windows' Intel will likely ignore it as it relies on legacy VBIOS
to be loaded at 0xc0000.
Tested successfully on DG43GT (x4x) with vbt.bin,
with X200 (gm45) with vendor option rom and
D945GCLF (i945) with fake vbt.
Change-Id: I1896411155592b343e48cbd116e2f70fb0dbfafa
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The scramble seed intended for CH1 were written to the regs of CH0.
Write the scramble seed for CH1 at the correct offset.
TESTED on Lenovo T430, HP 2760P, Asrock B75PRO3-M.
Change-Id: I3778947e96b3298c38e6d5b74988e617e1ffea7b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Iru Cai <mytbk920423@gmail.com>
This code path was only triggered in one corner case: GFX UMA set to
48MiB. It created a hole below UMA to save MTRRs. But, this hole was
never accounted for when calculating cbmem_top(). Instead of trying
to fix it, remove it, it's not worth the trouble.
TEST=Booted lenovo/x200 with all available CMOS gfx_uma_size settings.
Change-Id: I3f4ceec4224d86113be9bfa3ce4759bed584640d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
New AGESA support files will be used for binaryPI
platforms as well. Furthermore, some of those should
move from split nb/ sb/ directories to soc/, so move
support files for the API under drivers/.
Change-Id: I549788091de91f61de8b9adc223d52ffb5732235
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move all boards that have moved away from AGESA_LEGACY_WRAPPER
or BINARYPI_LEGACY_WRAPPER to use POSTCAR_STAGE.
We use POSTCAR_STAGE as a conditional in CAR teardown to tell
our MTRR setup is prepared such that invalidation without
writeback is a valid operation.
Change-Id: I3f4e2170054bdb84c72d2f7c956f8d51a6d7f0ca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This file mostly mimics Porting.h and should be removed.
For now, move it and use it consistently with incorrect form
as #include "cbtypes.h".
Change-Id: Ifaee2694f9f33a4da6e780b03d41bdfab9e2813e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
SPD decoding problems are no longer a good method for detecting if i2c
byte read failed, since the return value of i2c_block_read is checked.
Change-Id: I230aa22964c452cf28a9370c927b82c57e39cc62
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This simplifies computing dram timings a lot.
This removes computation of rank size based on columns, rows,
banks,... and uses the information in SPD byte 31. The result of this
is that dimms with multiple asymmetric ranks are not supported
anymore. These however are very rare and most likely never tested on
this platform.
This also uses i2c block read instead of byte read to speed up the
raminit. The result is less time is being spend reading SPDs.
It still keeps smbus read byte as a backup if i2c block read were to
fail.
Change-Id: I97c93939d11807752797785dd88c70b43a236ee3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
According to clang, main has no prototype for bcom/winnetp680
so add it into corresponding raminit.h
Change-Id: I8a55267901986757a4fa88ee13460ffbed3eeadc
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/21356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
There's no reason to mutate the struct device when determining
the ACPI name for a device. Adjust the function pointer
signature and the respective implementations to use const
struct device.
Change-Id: If5e1f4de36a53646616581b01f47c4e86822c42e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Implement cbmem_top() required for cbmem support in romstage.
Boot tested on asus/p2b-ls. Boards to move to this setup in
followup patches.
Change-Id: I432f145a5343c1bb5f2b0de3b6b88f57124d1bd9
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20977
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
With AMD_INIT_ENV and AMD_INIT_S3LATERESTORE moved
from romstage to ramstage, heapamanager in romstage
is no longer needed.
Change-Id: Iea8ad3ddb245c83dd290436ac9d4ecac9350b88c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
