Instead of positional arguments switch sconfig to use getopt and pass
the arguments as options in the build system. This will make it easier
to add additional options.
Change-Id: I431633781e80362e086c000b7108191b5b01aa9d
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
BUG=chromium:1023662
TEST=buildbot pass
TEST=1. Use python2 script
2. Run `emerge-kevin coreboot` twice, so we get bootblock.bin.1
and bootblock.bin.2
3. Run `xxd` on these two bootblock so we get bootblock.bin.1.hex
and bootblock.bin.2.hex
4. `diff bootblock.bin.1.hex bootblock.bin.2.hex` and record the
difference. (at least, the time info changes)
5. Migrate to python3
6. Similar steps, we get bootblock.bin.py3.hex
7. `diff bootblock.bin.1.hex bootblock.bin.py3.hex`, the difference
is similar. (time info, git hash changes)
Signed-off-by: Yilin Yang <kerker@google.com>
Change-Id: I04253084ec9b65310c52598b629390051cd2172b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45447
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=chromium:1023662
TEST=1. Create a tiny file `in.txt` as input
2. Run `fixed_cksum.py in.txt out.txt 20` with py2 and py3 version,
the output is the same
3. Run `variable_cksum.py in.txt out.txt` with py2 and py3 version,
the output is the same
Signed-off-by: Yilin Yang <kerker@google.com>
Change-Id: I9428269dfb826a3a95fffef9ea3f7c1a7107ef84
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
BUG=chromium:1023662
TEST=1. Use python2 script
2. Run `emerge-asurada coreboot` twice, so we get bootblock.bin.1
and bootblock.bin.2
3. Run `xxd` on these two bootblock so we get bootblock.bin.1.hex
and bootblock.bin.2.hex
4. `diff bootblock.bin.1.hex bootblock.bin.2.hex` and record the
difference. (at least, the time info changes)
5. Migrate to python3
6. Similar steps, we get bootblock.bin.py3.hex
7. `diff bootblock.bin.1.hex bootblock.bin.py3.hex`, the difference
is similar.
Signed-off-by: Yilin Yang <kerker@google.com>
Change-Id: I788e7c9b09257142728a0f76df8c2ccc72bf6b3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
On some systems where the system compiler enables `-Wformat-security
-Werror=format-security` options by default, building libcpp fails
because the code passes a variable directly as a format string.
This change addresses this problem by patching the affected code.
Tested with the default compiler of Nixpkgs unstable, GCC 9.3.0 with the
options described above enabled by default.
Signed-off-by: Masanori Ogino <mogino@acm.org>
Change-Id: Ibf3c9e79ce10cd400c9f7ea40dd6de1ab81b50e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The latest debian image needs the python2 package specified instead of
just 'python'. Also add python3 to the builder as we'll probably be
getting python3 scripts before too long.
Change-Id: Iceea3981b1e219141bf06ad0b559cdbf1c98b360
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Rarely, the driver of one device needs to know about another device
that can be anywhere in the device hierarchy. Current applications
boil down to EEPROMs that store information that is consumed by some
code (e.g. MAC address).
The idea is to give device nodes in the `devicetree.cb` an alias that
can later be used to link it to a device driver's `config` structure.
The driver has to declare a field of type `struct device *`, e.g.
struct some_chip_driver_config {
DEVTREE_CONST struct device *needed_eeprom;
};
In the devicetree, the referenced device gets an alias, e.g.
device i2c 0x50 alias my_eeprom on end
The author of the devicetree is free to choose any alias name that
is unique in the devicetree. Later, when configuring the driver the
alias can be used to link the device with the field of a driver's
config:
chip some/chip/driver
use my_eeprom as needed_eeprom
end
Override devices can add an alias if it does not exist, but cannot
change the alias for a device that already exists.
Alias names are checked for conflicts both in the base tree and in the
override tree.
References are resolved after the tree is parsed so aliases and
references do not need to be in a specific order in the tree.
Change-Id: I058a319f9b968924fbef9485a96c9e3f900a3ee8
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35456
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Bayou and OpenBIOS aren't supported by the coreboot build system
anymore, so remove these mentions.
Change-Id: Ibdf6fdc776068041cb468fdbf5b56b06f85c2d4b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Instead of generating hexdumps, output binary SPD files since we plan to
convert all hex SPD files to binary. Also adjust the file extension
where needed.
Test: compared generated binaries with converted binaries from hex files
Change-Id: Ie99d108ca90758d09dbefad20fe6c9f7fc263ef1
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Passing binary SPD files to apcb_edit can lead to an encoding error,
since the files were read in text mode. To fix this, read SPD files
always in binary mode and only decode them, when `--hex` is set.
Tested by comparing output files from the same SPDs in both, binary and
hex mode.
Change-Id: I6b75a9e1234e71667bdc8cb4eb10daf8c0ac3c17
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Apply the change in CB:44905 to the puff template, moving DPTF policies
from static ASL files into the new SSDT-based DPTF implementation.
BUG=b:158986928
BRANCH=puff
TEST=None
Change-Id: I601fd4c6aeaa3afee0f7fd9d13376f2fffd6d793
Signed-off-by: Sam McNally <sammc@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
While GMP supports fat builds on x86 that adapt to the CPU's
capabilities, by default it builds for the CPU of the builder.
Running that binary on an older CPU then can fail.
Change-Id: Iafdc2eb696189b9e2c5ead316f310d98c949ef74
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45044
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the field for the PSP verstage signature entry. This adds the
public key signing token to the PSP Directory table to verify the signed
PSP verstage binary
BUG=b:166100797
TEST=Build in a file and verify that it's present with the correct ID.
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I7525045d8746b6857979d07b02758ab4d4835026
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Eric Peers <epeers@google.com>
GCC9 introduced a new warning [-Waddress-of-packed-member]. This
is giving the following warning when building amdfwtool: warning: taking
address of packed member of ‘struct _bios_directory_entry’ may result in
an unaligned pointer value. Looking at the definition of the struct, it
looks like this is probably true.
Since the function being called doesn't read from the values, zeroing
them out in the beginning of the function, the code just passes pointers
to the temporary variables without initializing them.
BUG=None
TEST=Build & use AMD firmware table.
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I2f1e0aede8563e39ab0f2ec6daed91d6431eac43
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Eric Peers <epeers@google.com>
BUG=b:153888802
TEST=Able to list correct eSPI frequency as per TGL SPI flash guide
Without this CL :
Found Component Section
FLCOMP 0x093030f6
Dual Output Fast Read Support: not supported
Read ID/Read Status Clock Frequency: 50MHz
Write/Erase Clock Frequency: 50MHz
Fast Read Clock Frequency: 50MHz
Fast Read Support: supported
Read Clock Frequency: 20MHz
With this CL :
Found Component Section
FLCOMP 0x093030f6
Dual Output Fast Read Support: not supported
Read ID/Read Status Clock Frequency: 50MHz
Write/Erase Clock Frequency: 50MHz
Fast Read Clock Frequency: 50MHz
Fast Read Support: supported
Read eSPI/EC Bus Frequency: 60MHz
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I20840e6f931d7c1fabea0b6892e3bd19ead81168
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
BUG=b:153888802
TEST=Able to list correct SPI frequency as per TGL SPI flash guide
Without this CL :
Found Component Section
FLCOMP 0x093030f6
Dual Output Fast Read Support: not supported
Read ID/Read Status Clock Frequency: 33MHz
Write/Erase Clock Frequency: 33MHz
Fast Read Clock Frequency: 33MHz
Fast Read Support: supported
Read Clock Frequency: 20MHz
With this CL :
Found Component Section
FLCOMP 0x093030f6
Dual Output Fast Read Support: not supported
Read ID/Read Status Clock Frequency: 50MHz
Write/Erase Clock Frequency: 50MHz
Fast Read Clock Frequency: 50MHz
Fast Read Support: supported
Read Clock Frequency: 20MHz
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Id0a0a0cbd948ef8334cf522c09e881b464e87f0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44819
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Consider IBEX_PEAK onwards all chipsets are belong to PCH family.
BUG=b:153888802
TEST=Able to print correct PCH revision on Hatch Platform.
> ifdtool -d coreboot.rom
Without this CL :
ICH Revision: 300 series Cannon Point/ 400 series Ice Point
With this CL :
PCH Revision: 300 series Cannon Point/ 400 series Ice Point
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Ifd40dddc9179f347c0ea75149ec08089a829fdb4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Able to uniquely identify the chipset without specifying the platform
specific quirks (adl/cnl/icl/jsl/tgl etc.).
BUG=b:153888802
TEST=Able to dump FD contains correctly without specifying platform
quirks on Hatch Platform.
> ifdtool -d coreboot.rom
Without this CL :
ICH Revision: 100 series Sunrise Point
With this CL :
ICH Revision: 300 series Cannon Point/ 400 series Ice Point
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I83763adb721e069343b19a10e503975ffa6abb24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44815
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Marking dependencies has undergone some change in Chrome OS tree. The
script to cherry-pick the changes to ChromeOS tree prepends "Original-" to
the concerned meta data i.e. Cq-Depend becomes Original-Cq-Depend. This
causes dependencies to not take effect when changes are submitted to the
continuous integration. Do not prepend "Original-" to the dependency
meta data.
BUG=None
TEST=Ensure that the Cq-Depend line is added without any prefix.
Change-Id: I0503234954f872ee56708e19e89cae9d9fa30df7
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add support for 10th-gen/Comet Lake-U based boards:
- add PCI IDs for host bridge, IGD, LPC devices
- add support for dumping GPIOs, PCRs, etc
Tested on an unbranded CML-U board running AMI firmware
Change-Id: I44871917565fc628fd1073a6e5c36b6a3246a61c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Add memory parts needed by zork boards. Attributes are derived from data
sheets.
BUG=b:162939176
TEST=Compared generated SPDs with data sheets and checked in SPDs
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I67f205f9af24bbc5c12656be1f363a15fe975955
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44447
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If a memory part is a x16 part that has two dies and only a single
rank, then the x16 describes the part width (since this solution will
need to be a stacked solution) and as such, we must translate the
DeviceBusWidth to the "die bus width" instead.
Change DeviceBusWidth variable name to PackageBusWidth to be more
descriptive
BUG=b:166645306, b:160157545
TEST=run gen_spd and verify that spds for parts matching description
above changed appropriately.
Change-Id: Ia6f3ca109d344b7a015da28125a94ce10d2bdfb8
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
For boards that have already assigned memory ids, there needs to be a
way to fix parts to a specific id. After assigning all the fixed ids the
tool still attempts to minimize the SPDs entries. Since a fixed ID could
be anywhere, gaps can be created in the list. So an empty SPD entry is
created to fill the gaps in the list until they are used.
BUG=b:162939176
TEST=Generate various outputs
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I1f8ea1ff4f33a97ab28ba94896a1054e89189576
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Now that generic SPD files have the memory type prepended to the
filename, they can be stored in the same location. This CL moves
the generic SPDs to the new location.
Change the ddr4 gen_part_id.go and gen_spd.go tools to use
"ddr4_spd_manifest.generated" instead of "spd_manifest.generated".
Change the lpddr4x gen_part_id.go and gen_spd.go tools to use
"lp4x_spd_manifest.generated" instead of "spd_manifest.generated".
Move TGL DDR4 and LPDDR4x generic SPDs into a common location.
Move JSL DDR4 and LPDDR4x generic SPDs into a common location.
Change the volteer/spd/Makefile.inc to use the new path for the spds.
Change the dedede/spd/Makefile.inc to use the new path for the spds.
BUG=b:165854055
TEST="emerge-volteer coreboot" and verify all variants build correctly.
Change-Id: I83b088cb718d15ffd3012c84a12b5231ae84a3e4
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44648
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Check for duplicate entries in mem parts json file.
BUG=b:162939176
TEST=Verified that tool throws error when there is a duplicate.
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I7c638c7938958727cfc832e7b4556acbc04b0ca4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44478
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move ddr4 and lp4x to spd_tools root folder. The tool now applies to non
intel platforms.
BUG=b:162939176
TEST=Run tool
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I0941ea036d760ee27eb34f259f4506a4b7584bee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44844
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add "MEMORY_TYPE = lp4x" to the generated Makefile.inc to indicate
this is lpddr4x memory and to use the generic SPDs from the lpddr4x
respository of SPDs.
BUG=b:160157545
TEST=run gen_part_id for volteer and verify that it adds the line "MEMORY_TYPE =
lp4x" to the makefile produced.
Change-Id: I416690ae8aff8052474b16ef0d3e940e72e6a2fb
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Serial Presence Detect (SPD) data for memory modules is used by Memory
Reference Code (MRC) for training the memory. This SPD data is
typically obtained from part vendors but has to be massaged to format
it correctly as per JEDEC and MRC expectations. There have been
numerous times in the past where the SPD data used is not always
correct.
In order to reduce the manual effort of creating SPDs and generating
DRAM IDs, this change adds tools for generating SPD files for DDR4
memory used in memory down configurations on Intel Tiger Lake (TGL)
based platforms. These tools generate SPDs following JESD79-4C and
Jedec "4.1.2.L-5 R29 v103" specification.
Two tools are provided:
* gen_spd.go: Generates de-duplicated SPD files using a global memory
part list provided by the mainboard in JSON format. Additionally,
generates a SPD manifest file (in CSV format) with information about
what memory part from the global list uses which of the generated
SPD files.
* gen_part_id.go: Allocates DRAM strap IDs for different DDR4
memory parts used by the board. Takes as input list of memory parts
used by the board (with one memory part on each line) and the SPD
manifest file generated by gen_spd.go. Generates Makefile.inc for
integrating the generated SPD files in the coreboot build.
BUG=b:160157545
Change-Id: I263f936b332520753a6791c8d892fc148cb6f103
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Closing stdout early seems to have a detrimental effect on kconfig on a
system under high load (e.g. when doing lots of builds in parallel).
Change-Id: I6987f1deac596124c7b397bf7bc5a78d691cc538
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
amdfwtool currently assumes that we MUST have an apob_nv area if we
have an aopb. This is not required, so if neither the apob_nv size or
base are specified, just move on.
BUG=b:158363448
TEST=Build an image with no APOB_NV region. Dump regions to show that
it's not there.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ibaeacd3dcdfd73f690df61c2a19d39bbb9dcc838
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44045
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
.xcompile is generated before the submodules handling, but there's no
need for the submodules to be around, so skip here, too.
Change-Id: I60205f65b124a09067de5ae50f066b5cf64733f2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add support for Cannonlake-LP SoCs (Whiskeylake-U,
Coffeelake-U, Cometlake-U) as a separate parsing profile,
copying the existing 'Sunrise' profile and adjusting for differences
in reset mapping and GPIO macro generation
Test: convert inteltool GPIO log dump into coreboot macros for
an out-of-tree CML-U board.
Change-Id: I86296697ee892af7aa0818fb608b6d68fad2f307
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Unlike Linux kernel which has a static shadow region layout, we have
multiple stages in coreboot and thus require a different shadow offset
address. Unfortunately, GCC currently only supports adding a static
shadow offset at compile time using -fasan-shadow-offset flag.
For this reason, we enable GCC to determine asan shadow offset address
at runtime using a callback function named __asan_shadow_offset().
This supersedes the need to specify this address at compile time. GCC
then makes use of this shadow offset to protect stack buffers by
inserting red zones around them.
Some other benefits of having this GCC patch are:
a. We can place the shadow region in a separate linker section with
all its advantages like automatic fit insurance. This ensures if
a platform doesn't have enough memory space to hold shadow region,
the build will fail. (However, if we use a fixed shadow offset on a
platform that actually doesn't have enough memory, it may still
build without any errors.)
b. We don't modify the memory layout compared to the current one, as
we are placing the shadow region at the end of the space already
occupied by the program.
c. We can be much more flexible later if needed (thinking of other
stages like bootblock).
d. Since we are appending the shadow buffer to the region already
occupied, we make efficient use of the limited memory available
which is highly beneficial when using cache as ram.
Further, we have made sure that if you compile you tree with ASan
enabled but missed this patch, it will end up in the following
compilation error:
"invalid --param name 'asan-use-shadow-offset-callback'"
So, you cannot accidentally enable the feature without having your
compiler patched.
Change-Id: I401631938532a406a6d41e77c6c9716b6b2bf48d
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Duncan Laurie