Commit Graph

7588 Commits

Author SHA1 Message Date
Hung-Te Lin 7b654a9702 cbfstool: Fix compile warnings caused by incorrect data types.
The "offset" in cbfs-mkpayload should be printed as type %lu
instead of %d as `gcc` rightfully warns about.

    gcc -g -Wall -D_7ZIP_ST -c -o /srv/filme/src/coreboot/util/cbfstool/cbfs-mkpayload.o cbfs-mkpayload.c
    cbfs-mkpayload.c: In function ‘parse_fv_to_payload’:
    cbfs-mkpayload.c:284:3: warning: format ‘%d’ expects argument of type ‘int’, but argument 3 has type ‘long unsigned int’ [-Wformat]
    cbfs-mkpayload.c:296:3: warning: format ‘%d’ expects argument of type ‘int’, but argument 3 has type ‘long unsigned int’ [-Wformat]

This warning was introduced in the following commit.

    commit 4610247ef1
    Author: Patrick Georgi <patrick@georgi-clan.de>
    Date:   Sat Feb 9 13:26:19 2013 +0100

        cbfstool: Handle alignment in UEFI payloads

        Reviewed-on: http://review.coreboot.org/2334

Change-Id: I50c26a314723d45fcc6ff9ae2f08266cb7969a12
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2440
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2013-02-18 12:28:43 +01:00
Paul Menzel 475d42a16c cbfstool: Add `-Werror` to make all warnings into errors
Ensure that no changes with warnings are committed. Although using
`-Werror` is debatable [1][2].

[1] http://blog.flameeyes.eu/2009/02/future-proof-your-code-dont-use-werror
[2] http://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html

Change-Id: I402f2d82dd4087d8a575b0a85305a02ef04bb537
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2441
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-02-18 12:10:44 +01:00
Zheng Bao ca6e1f6c04 AMD S3: Program the flash in a bigger data packet
According to spi.c in src/southbridge/amd/agesa/hudson
readwrite = (bytesin + readoffby1) << 4 | bytesout;
We can see that Hudson limits the SPI programming data
packet size as 15.

We used to write data to SPI in dword mode. It didn't
take full advantage of the data packet size. We need to
leverage that to speed up programming time.

Change-Id: I615e3c8e754e58702247bc26cfffbedaf5827ea8
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/2306
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-02-18 09:00:24 +01:00
Zheng Bao 178df1121d AMD S3: Fix typo vol*a*tile in southbridge Kconfig
Change non-volitile to non-volatile.

Change-Id: Idfc7db3b3dcf078f0f3134fc62679bed439a4fd2
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/2437
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-02-18 08:59:47 +01:00
Martin Roth 92f03c0a06 AMD Family12h: Fix warnings
Add needed prototypes to .h files.
Remove unused variables and fix types in printk statements.
Add #IFNDEFs around #DEFINEs to keep them from being defined twice.
Fix a whole bunch of casts.
Fix undefined pre-increment behaviour in a couple of macros.  These now
  match the macros in the F14 tree.
Change a value of 0xFF that was getting truncated when being assigned
  to a 4-bit bitfield to a value of 0x0f.

This was tested with the torpedo build.
This fixes roughly 132 of the 561 warnings in the coreboot build
  so I'm not going to list them all.
  Here is a sample of the warnings fixed:

In file included from src/cpu/amd/agesa/family12/model_12_init.c:35:0:
src/include/cpu/amd/amdfam12.h:52:5: warning: redundant redeclaration of 'get_initial_apicid' [-Wredundant-decls]
In file included from src/cpu/amd/agesa/family12/model_12_init.c:34:0:
src/include/cpu/amd/multicore.h:48:5: note: previous declaration of 'get_initial_apicid' was here

src/northbridge/amd/agesa/family12/northbridge.c:50:10: warning: no previous prototype for 'get_node_pci' [-Wmissing-prototypes]
src/northbridge/amd/agesa/family12/northbridge.c: In function 'get_hw_mem_hole_info':
src/northbridge/amd/agesa/family12/northbridge.c:302:13: warning: unused variable 'i' [-Wunused-variable]
src/northbridge/amd/agesa/family12/northbridge.c: In function 'domain_set_resources':
src/northbridge/amd/agesa/family12/northbridge.c:587:5: warning: format '%lx' expects argument of type 'long unsigned int', but argument 3 has type 'device_t' [-Wformat]
src/northbridge/amd/agesa/family12/northbridge.c:587:5: warning: format '%lx' expects argument of type 'long unsigned int', but argument 3 has type 'device_t' [-Wformat]
src/northbridge/amd/agesa/family12/northbridge.c:716:1: warning: format '%x' expects argument of type 'unsigned int', but argument 3 has type 'long unsigned int' [-Wformat]

In file included from src/mainboard/amd/torpedo/agesawrapper.h:31:0,
                 from src/northbridge/amd/agesa/family12/northbridge.c:38:
src/vendorcode/amd/agesa/f12/AGESA.h:1282:0: warning: "TOP_MEM" redefined [enabled by default]
In file included from src/northbridge/amd/agesa/family12/northbridge.c:34:0:
src/include/cpu/amd/mtrr.h:31:0: note: this is the location of the previous definition
In file included from src/mainboard/amd/torpedo/agesawrapper.h:31:0,
                 from src/northbridge/amd/agesa/family12/northbridge.c:38:
src/vendorcode/amd/agesa/f12/AGESA.h:1283:0: warning: "TOP_MEM2" redefined [enabled by default]

src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetNumberOfComplexes':
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:99:19: warning: operation on 'ComplexList' may be undefined [-Wsequence-point]
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetLengthOfPcieEnginesList':
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:126:20: warning: operation on 'PciePortList' may be undefined [-Wsequence-point]
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetLengthOfDdiEnginesList':
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:153:19: warning: operation on 'DdiLinkList' may be undefined [-Wsequence-point]
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetComplexDescriptorOfSocket':
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:225:17: warning: operation on 'ComplexList' may be undefined [-Wsequence-point]

src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePhyServices.c:246:1: warning: no previous prototype for 'PcieFmForceDccRecalibrationCallback' [-Wmissing-prototypes]

In file included from src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexConfig.c:58:0:
src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/LlanoComplexData.h:120:5: warning: large integer implicitly truncated to unsigned type [-Woverflow]

And fixed a boatload of these types of warning:
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c: In function 'HeapGetBaseAddress':
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:687:17: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:694:19: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:701:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:702:23: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:705:23: warning: assignment makes integer from pointer without a cast [enabled by default]
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:709:21: warning: assignment makes integer from pointer without a cast [enabled by default]

Change-Id: I97fa0b8edb453eb582e4402c66482ae9f0a8f764
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2348
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-18 05:01:53 +01:00
Zheng Bao 96508a7949 AMD S3: Include the s3_resume.h only when S3 is enabled.
Change-Id: I9a6c4f61e5dda6665f92c8526bb26a458ee2b739
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/2384
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-02-18 01:08:44 +01:00
Ronald G. Minnich 7b6945405a libpayload: only compile drivers/serial.c on machines that use it.
Create a new serial console variable, X86_SERIAL_CONSOLE
which is only enabled when SERIAL_CONSOLE and ARCH_X86 are defined.

Builds for x86 and ARM.

Change-Id: I607253c418de015975a839e3c33577842885ec0c
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2412
Tested-by: build bot (Jenkins)
Reviewed-by: Gabe Black <gabeblack@chromium.org>
2013-02-16 04:48:51 +01:00
David Hendricks 802921562f exynos5250: clean out some stale IRAM-related config variables
This cleans out some obsolete Kconfig variables pertaining to IRAM
usage.

Change-Id: Ie53f5f7204eadc3a3dddc739d2b4b6237242b198
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2417
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-02-16 00:43:13 +01:00
David Hendricks 882fdcf227 armv7/exynos5250: fix usage of _stack and _estack
This patch fixes up the usage of stack pointer and regions.
The current approach only works by coincidence, so this fixes a few
things at once to get it into a working state and allow us to use
checkstack() again:

- Add a STACK_SIZE Kconfig variable. Earlier on it was evaluated to 0.

- Assign _stack and _estack using CPU-specific Kconfig variables since
  it may reside elsewhere in memory (not necessarily DRAM).

- Make the existing IRAM stack variables more useful in this context.

Change-Id: I4ca5b5680c9ea7e26b1b2b6b3890e028188b51c2
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2416
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-02-16 00:39:01 +01:00
Stefan Reinauer 1cf46a7bbf ARMv7: Drop u-boot type remains
Just a mechanical cleanup.

Change-Id: I0815625e629ab0b7ae6c948144085f1bd8cabfb5
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2408
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-02-15 19:05:39 +01:00
Stefan Reinauer 37955a21d1 Exynos5250: Drop unused file ehci-s5p.h
Change-Id: I39014377af718766ef86c149e2d2da3d97eaa728
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2407
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-15 19:03:43 +01:00
Christian Gmeiner b97ee89684 OT200: add CMOS support
nvramtool works as expected.

root@CHGM-DEV-OT200:~# /home/vis/nvramtool -a
baud_rate = 19200
debug_level = Emergency

Change-Id: Ia25dc5b4f0ed3a2dd7cc67b7d3174db3a6eff70e
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/2382
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2013-02-15 09:04:30 +01:00
Ronald G. Minnich 8deb5c6e0f libpayload: Use the same type for 32 bit data in readl as in uint32_t.
The compiler gets mad when the types are equivalent size but not necessarily
interchangeable because of strict aliasing checks. Since uint32_t is likely to
be used when trying to read 32 bit data, it makes sense for them to be the
compatible.

Signed-off-by: Gabe Black <gabeblack@google.com>

Change-Id: If73d794866055dc026fc06d6268e692adac0f835
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2411
Tested-by: build bot (Jenkins)
Reviewed-by: Gabe Black <gabeblack@chromium.org>
2013-02-15 06:52:01 +01:00
Ronald G. Minnich 1a29c1e766 libpayload: fix compiler flags
lpgcc was unconditionally setting -m32.

Most of the flags it sets in the common case are right, however: no need
to duplicate them everywhere, and we only want to change the common ones
in one place, so it would be a shame to duplicate _CFLAGS all over the place.

So add another variable, _ARCHEXTRA, which can be used to add
special flags to _CFLAGS. We onlu use it at present for the x86; this may
change.

This allows us to get through compiling on arm and x86.

Change-Id: I12f1620982c4ee10f76b3953e4225f13db31531e
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2399
Tested-by: build bot (Jenkins)
Reviewed-by: Gabe Black <gabeblack@chromium.org>
2013-02-15 06:51:52 +01:00
Ronald G. Minnich 2cc105c741 libpayload: get time to compile cross-arch
Get rid of the nest of includes, and make separate sections
for each architecture. Also gets rid of the "there's X86 and there's
everything else" structure of this file.

Change-Id: I4232f50f048fa05e911e5de3aa9ec1530931b461
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2397
Tested-by: build bot (Jenkins)
Reviewed-by: Gabe Black <gabeblack@chromium.org>
2013-02-15 06:51:38 +01:00
Ronald G. Minnich c1ee8641cb libpayload: make functions static that are unused outside memory.c
The default_ functions in memory.c are only used to initialize a weak
variable.  They should not be used outside memory.c. Make them
invisible.

Remove the declaration from libpayload.h. For real this time.

Change-Id: Id54c1fd172c78748f01a958ce4065dd0eb53bbc3
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2394
Tested-by: build bot (Jenkins)
Reviewed-by: Gabe Black <gabeblack@chromium.org>
2013-02-15 06:51:17 +01:00
Ronald G. Minnich f2e10cb544 libpayload: Use an appropriate range of memory when looking for cb tables.
These live at the bottom of memory on x86, but that's IO mapped on the exynos.
The particular range used will likely need to be configurable, but this will
make it work in one more case than it used to.

Change-Id: I4d4963b9732cf538d00f8effb4398f30cbbde6aa
Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2410
Tested-by: build bot (Jenkins)
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-15 03:19:06 +01:00
Stefan Reinauer ba1008e33f Exynos: Drop dead code in cpu.h
Change-Id: Ibb5fa27a0d45ddd8f57e8e8c28961d204e2ef1e3
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2409
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-15 02:44:00 +01:00
Stefan Reinauer 8bc58da8ac ARMv7: straighten out reset code
We don't need three different implementations.

Change-Id: Ie7b5fa90794676ea38838454a33e8e9188428eb7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2406
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-15 02:43:09 +01:00
Stefan Reinauer 5dbf689b62 Exynos5: Drop S5P directory and merge files
s5p-common mostly contained duplicate files, drop the whole directory
and merge the few pieces that we are using into exynos5-common.

Change-Id: I5f18e8a6d2379d719ab6bbbf817fe15bda70d17f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2405
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-15 02:11:34 +01:00
Stefan Reinauer 7512e4593e ARMv7: Drop sr32, and wait_on_value
They're unused. Also drop some unused defines in system.h

Change-Id: Ia5afc3a676a4a94787041430f05d08f333033c73
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2404
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
2013-02-15 01:40:34 +01:00
Stefan Reinauer 0663dfd3d5 ARMv7: Fix include file names in memset & memcpy
We don't have asm/

Change-Id: I7f80f47e9d7f457b7a5a64603c59b14d3b536a8c
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2403
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-15 01:37:03 +01:00
Stefan Reinauer 8a4ce28fc4 ARMv7: Drop more unused files
Change-Id: I0dd83f96d2a9598e9677d1b0b114229de6724287
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2401
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-15 01:15:07 +01:00
Ronald G. Minnich 2149ad3c9c libpayload: add a ldscript for arm
I think this needs to be its own ldscript. I'm pretty sure this one
is going to need some work however. Is libpayload PIC? That would be
best if so.

Change-Id: I44578d70dfa72de527af8901a86583c2a60130ec
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2398
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
2013-02-15 01:13:11 +01:00
Stefan Reinauer 5ae44ded5c Drop include/arch-generic/div64.h
It's unused.

Change-Id: Id67ca754ff7ad148ff1ecd4f1e5c986a4e7585a8
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2400
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-15 01:11:07 +01:00
Stefan Reinauer 8e7b3c458c Exynos: Drop unused include files
Change-Id: Ib533938446a289167725f5beda77c2ee5236e8a5
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2395
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
2013-02-15 00:13:19 +01:00
Stefan Reinauer a957b7ad21 ARMv7: drop multiboot support
Multiboot is an x86 only thing. Drop support on ARM.

Change-Id: I13fafa464a794206d5450b4a1f23a187967a8338
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2392
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14 23:55:34 +01:00
Stefan Reinauer 0928eb3429 Exynos: Drop duplicate copy of watchdog.h
Change-Id: I4c9bfa9eb7708420dc42c16bc152d761d2bdfee3
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2391
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14 23:54:33 +01:00
Stefan Reinauer fc4823d245 ARMv7: Drop SKIP_LOWLEVEL_INIT
It's not used.

Change-Id: I713d60209815f0aad93f5d4d3afef9f825db427e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2393
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
2013-02-14 23:48:01 +01:00
Stefan Reinauer f151a81f8b Exynos5250: Drop SHA implementation
We don't need SHA in coreboot.

Change-Id: I1985d5e2c74fac39ff9dcdba4c23bb34fa857ec7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2390
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
2013-02-14 23:15:21 +01:00
Ronald G. Minnich c2e8cf5675 libpayload; put the ldscript into an arch-dependent directory path
Since it's utterly architecture-dependent, put it in arch/x86.
Avoid the temptation to make yet another directory with just one
file in it. Fix the makefile to pick up the proper arch-dependent script.

Change-Id: I21ea02551a97bdcbc38419714f3b38cf8335c178
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2389
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-14 21:32:02 +01:00
Paul Menzel 7df4ec0303 Chromebooks: mainboard.c: Do not spell Chromebook in CamelCase
»Chromebook« is the official spelling [1]. So correct that with
the following command.

    $ git grep -l ChromeBook | xargs sed -i s,ChromeBook,Chromebook,

The incorrect spelling was only used for the chip name.

[1] http://www.google.com/intl/en/chrome/devices/hp-pavilion-chromebook.html#hp-pav

Change-Id: I9c19f399a3e3d36bd644ec375822daa384a14961
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2370
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-14 19:25:54 +01:00
Paul Menzel 835df770e3 Google Butterfly: thermal.h: Align macro content
Change-Id: I3729f9bf66fcd72fa8870bb56a9c253a7368c774
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2371
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-14 19:24:46 +01:00
Stefan Reinauer 0aa37c488b sconfig: rename lapic_cluster -> cpu_cluster
The name lapic_cluster is a bit misleading, since the construct is not local
APIC specific by concept. As implementations and hardware change, be more
generic about our naming. This will allow us to support non-x86 systems without
adding new keywords.

Change-Id: Icd7f5fcf6f54d242eabb5e14ee151eec8d6cceb1
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2377
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14 07:07:20 +01:00
David Hendricks 398e84c71a armv7: don't write a forward entry in coreboot tables
We don't seem to need it, and it currently confuses the payload.

(credit to Gabe Black for this, I'm just uploading it)

Change-Id: I4e3a60eceb9b24e3bc8e50db431c1a731d1cdbae
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/2385
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14 07:05:04 +01:00
David Hendricks a86e4ba8bd snow: Set up MMU after DRAM is working
This was omitted earlier while we were debugging DRAM code (0a5bc7f).
It was likely broken due to inconsistent units earlier on. Now that
things are cleaned up and working, let's add it back in.

Change-Id: I2f356355c98b2896e2371fa63b9c9f20ae76d634
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2379
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14 07:03:55 +01:00
David Hendricks 2d0b55bd6b snow: remove superfluous printk's from romstage main
These were left over from earlier debugging and are no longer
needed. They don't indicate any status or useful info (other
than which line of code has been executed). Error messages are
available in case something needs attention.

Change-Id: Ie09fac29c42908cb8924169e56d8927fb76f02da
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2386
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14 07:02:54 +01:00
Stefan Reinauer 4aff4458f5 sconfig: rename pci_domain -> domain
The name pci_domain was a bit misleading, since the construct is only
PCI specific in a particular (northbridge/cpu) implementation, but not
by concept. As implementations and hardware change, be more generic
about our naming. This will allow us to support non-PCI systems without
adding new keywords.

Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2376
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14 02:00:10 +01:00
David Hendricks dc8259ce1d armv7/exynos: remove some stale files leftover from initial import
This removes some files leftover from the initial port. Some are
leftover from U-Boot and some were leftover from the skeleton code
derived from x86.

There's a bit more that we'll get in another sweep.

Change-Id: I325793ecb902b3b9430dcf531714ce025d201de6
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2380
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-13 21:23:34 +01:00
David Hendricks b25208fc8b armv7: use start and size parameters in mmu_setup()
mmu_setup() was originally written in U-Boot to utilize board-specific
global data. Since we're trying to avoid that, we added start and size
parameters so that board-specific info can be passed in via mainboard
code. Let's start using it that way.

Change-Id: I7d7de0e42bd918c9f9f0c177acaf56c110bf8353
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2378
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-02-13 03:04:57 +01:00
Paul Menzel 1b6fecd64d armv7: stages.c: Fix grammar: s,The is to,This is to,
The comment introduced in

    commit 50c0a50ac6
    Author: David Hendricks <dhendrix@chromium.org>
    Date:   Thu Jan 31 17:05:50 2013 -0800

        armv7: unify stage hand-off routines

        Reviewed-on: http://review.coreboot.org/2254

contained a typo, which is corrected now.

Change-Id: I87f7cfa82fcd12b6961d3329e634b4c201cc047e
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2372
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-12 17:38:09 +01:00
Paul Menzel fd72d5a838 Google Butterfly: acpi/thermal.asl: Fix typo »The*re* is no …«
The commit introducing support for the Google Butterfly Chromebook

    commit d7bd4eb003
    Author: Stefan Reinauer <reinauer@chromium.org>
    Date:   Mon Feb 11 11:11:36 2013 -0800

        Add support for "Butterfly" Chromebook

        Reviewed-on: http://review.coreboot.org/2359

contains the typo, which is corrected now.

Change-Id: I932f4cd248cac71c3ede39a7da97162e791827cb
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2373
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Peter Stuge <peter@stuge.se>
2013-02-12 16:40:51 +01:00
Paul Menzel 1236b84234 Google Butterfly: gpio.h: Correct whitespace errors
Correct some whitespace inconsistencies introduced in the
following commit.

    commit d7bd4eb003
    Author: Stefan Reinauer <reinauer@chromium.org>
    Date:   Mon Feb 11 11:11:36 2013 -0800

        Add support for "Butterfly" Chromebook

        Reviewed-on: http://review.coreboot.org/2359

Change-Id: Ifeda7eb29ddf855cdfea41ddbd685441ede55756
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2374
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-12 15:27:58 +01:00
Paul Menzel d60bb4927a Google Parrot/Butterfly: fadt.c: Align macros correctly
The commits adding support for the Google Parrot Chromebook

    commit a7198b34cc
    Author: Stefan Reinauer <reinauer@chromium.org>
    Date:   Tue Dec 11 16:00:47 2012 -0800

        Add support for Google Parrot Chromebook

        Reviewed-on: http://review.coreboot.org/2026

and the Google Butterfly Chromebook

    commit d7bd4eb003
    Author: Stefan Reinauer <reinauer@chromium.org>
    Date:   Mon Feb 11 11:11:36 2013 -0800

        Add support for "Butterfly" Chromebook

        Reviewed-on: http://review.coreboot.org/2359

had macros in `fadt.c` which were not aligned correctly and did
not adhere to the coding style which uses just one space after
`#define`. Fix this and use tabs instead of spaces everywhere.

Change-Id: I1422c57a3bdc2faa29d2a6e2064e4d3aeed0f1cb
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2375
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-12 15:19:04 +01:00
Hung-Te Lin d01d0368f4 libpayload: New CBFS to support multiple firmware media sources.
Upgrade CBFS in libpayload to use new media-based implementation from coreboot
( http://review.coreboot.org/#/c/2182/ ).

Old CBFS functions (cbfs_find, cbfs_find_file, get_cbfs_header) are still
supported, although the recommended way is to use new CBFS API.

To migrate your existing x86 payload source:
	- Change cbfs_find to cbfs_get_file
	- Change cbfs_find_file to cbfs_get_file_content
	- Prefix every CBFS call with a CBFS_DEFAULT_MEDIA argument.

Ex, char *jpeg_data = cbfs_find_file("splash.jpg", CBFS_TYPE_BOOTSPLASH);
 => char *jpeg_data = cbfs_get_file_content(
		CBFS_DEFAULT_MEDIA, "splash.jpg", CBFS_TYPE_BOOTSPLASH);

The legacy setup_cbfs_from_{ram,flash} is also supported, although the better
equivalent is to make a new media instance:
	struct cbfs_media ram_media;
	init_cbfs_ram_media(&ram_media, start, size);
	char *data = cbfs_get_file_content(&ram_media, "myfile", my_type);

Verified by being successfully linked with filo.

Change-Id: If797bc7e3ba975d7e3be905c59424f7a93b8ce11
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2191
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-12 11:34:20 +01:00
Patrick Georgi 02ae0bf8fe build system: Don't run the full build system on "make clean"
When running "make clean" the build system used to parse the entire
build system. Besides costing time, it prevents cleaning the tree
if a blobs-board is selected but blobs are not enabled.

Instead, clean always removes all of $(obj) and .xcompile, while
distclean additionally removes .config and the like.

Besides cleaning up more completely (eg. dependency files), a side
effect is that this also removes $(obj)/util, if it exists
(default location for build tools).

Change-Id: Ief6362460d4eb7edcb4b0a47ec76cb9a61bf3b86
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2338
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-12 08:18:43 +01:00
David Hendricks 9a00016238 fix an error message in checkstack()
The order of some printk arguments were reversed.

Change-Id: I5e8f70b79050b92ebe8cfa5aae94b6cd1a5fd547
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2364
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-12 05:05:39 +01:00
David Hendricks ca3198f5d6 armv7: jump to ELF image using stage_exit()
This is just to get us to the payload.

TODO: Do we want to implement any of the stuff from the x86 version,
such as copying coreboot to a new location?

Change-Id: Ia0544f111d7a1189ebd92d0ba3e11448eabd6252
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2363
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-02-12 03:57:36 +01:00
Hung-Te Lin 7635a60ca8 armv7: Add emulation/qemu-armv7 board.
To simplify testing ARM implementation, we need a QEMU configuration for
ARM. The qemu-armv7 provides serial output, CBFS simulation, and full
boot path (bootblock, romstage, ramstage) to verify the boot loader
functionality.

To run with QEMU:
 export QEMU_AUDIO_DRV=none
 qemu-system-arm -M vexpress-a9 -m 1024M -nographic -kernel build/coreboot.rom

Verified to boot until ramstage loaded successfully by QEMU v1.0.50.

Change-Id: I1f23ffaf408199811a0756236821c7e0f2a85004
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2354
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-12 03:02:45 +01:00
Patrick Georgi bc64cae995 spi-generic.h: Adapt include guard
Rename _SPI_H_ to _SPI_GENERIC_H_ to match recent file rename.

Change-Id: I8b75e2e0a515fb540587630163ad289d0a6a0b22
Reported-by: Peter Stuge <peter@stuge.se>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2360
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2013-02-11 22:34:17 +01:00