Commit Graph

35200 Commits

Author SHA1 Message Date
Matt DeVillier c08d4c5c55 soc/amd/stoneyridge: Correct ACPI CPU string prefix
Commit 9550e97 [acpi: correct the processor devices scope] changed
the default CPU scope from _PR to _SB, but the default prefix in
Stoneyridge's Kconfig was missed, leading to ACPI errors for
'AE_NOT_FOUND for object \_PR.P00n.' Fix the default prefix and
eliminate the errors reported in dmesg.

Test: boot Linux w/5.3 kernel on google/liara, check for errors

Change-Id: I5611b6836062a0a9f90036d7fe40cd98bd730af3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-24 11:50:00 +00:00
Kyösti Mälkki c3c55210ee ACPI: Replace smm_setup_structures()
Except for whitespace and varying casts the codes were
the same when implemented.

Platforms that did not implement this are tagged with
ACPI_NO_SMI_GNVS.

Change-Id: I31ec85ebce03d0d472403806969f863e4ca03b6b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-24 11:49:15 +00:00
Kyösti Mälkki 5daa1d3898 ACPI: Replace uses of CBMEM_ID_ACPI_GNVS
These are the simple cbmem_find() cases. Also drop the redundant
error messages.

Change-Id: I78e5445eb09c322ff94fe4f65345eb2997bd10ef
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-06-24 11:48:38 +00:00
Kyösti Mälkki e37459ed64 ACPI: Add framework for GNVS initialisation
Provide common initialisation point for setting up
GNVS structure before first SMI is triggered.

Change-Id: Iccad533c3824d70f6cbae52cc8dd79f142ece944
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42423
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-24 11:46:26 +00:00
Zhuohao Lee cf06124cc6 volteer: Create delbin variant
Create the delbin variant of the volteer reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.1.1).

BUG=b:158797761
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_DELBIN

Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Change-Id: Icf5fc6b9cc6a7c47e52103b2d396bcddb26adf50
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-24 05:07:34 +00:00
Zhuohao Lee 36aaddf7d7 util/mainboard/google/volteer: Add dptf.asl to the template
The dptf.asl is needed when creating a new volteer variant, otherwise,
it will make the variant build failed. The error could be found from
this link: https://review.coreboot.org/c/coreboot/+/42709

BUG=b:158797761
TEST=Generate the Delbin correctly

Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Change-Id: Ib4059df9e08d6a1dba88f0299bb39c8c6ae406ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-06-24 05:07:27 +00:00
Felix Held 9e92c1d787 mb/amd/mandolin: resize EC FMAP section to match EC firmware size
The EC firmware is 128k including its header, so there's no need to
reserve another 4k for the header.

TEST=Mandolin still boots.

Change-Id: Id3a7a087bf37461ca8ad3da9a809f13d7f0d570c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42705
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-24 01:18:56 +00:00
Paul Fagerburg 8af1bcd38f hatch: Create wyvern variant
Create the wyvern variant of the puff reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.1.1).

BUG=b:158269582
BRANCH=None
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_WYVERN

Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: Id7a090058d2926707495387f7e90b3b8ed83dac7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42551
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-23 23:23:30 +00:00
Edward O'Callaghan 394b5fabf4 hatch: Create faffy variant
Create the faffy variant of the puff reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.1.1).

V.2: Manually modified to keep Kconfig sorted.

BUG=b:157448038
BRANCH=None
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_FAFFY

Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Change-Id: I5f14c2d6144ce3c2e48488ca81f31b3c04dc5fb9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42717
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-23 22:46:14 +00:00
Martin Roth cfc170b213 src/*: Update makefiles to exclude x86 code from psp-verstage
The assumption up to this point was that if the system had an x86
processor, verstage would be running on the x86 processor.  With running
verstage on the PSP, that assumption no longer holds true, so exclude
pieces of code that cause problems for verstage on the PSP.

This change will add these files to verstage only if the verstage
architecture is X86 - either 32 or 64 bit.

BUG=b:158124527
TEST=Build and boot on Trembyle

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I797b67394825172bd44ad1ee693a0c509289486b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42062
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-23 21:28:40 +00:00
Felix Held f3343f2560 mb/amd/mandolin/acpi: drop gpe.asl
Change-Id: I366108334006c81a4d5fb193f583a1e83f7c1456
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-23 18:39:35 +00:00
Furquan Shaikh baf1364f79 mb/google/zork: Add support for fingerprint device
This change adds support for fingerprint device in overridetree for
the following variants:
1. berknip
2. morphius
3. trembyle

Generates the following node in SSDT1:
    Scope (\_SB.FUR1)
    {
        Device (CRFP)
        {
            Name (_HID, "PRP0001")  // _HID: Hardware ID
            Name (_UID, Zero)  // _UID: Unique ID
            Name (_DDN, "Fingerprint Reader")  // _DDN: DOS Device Name
            Method (_STA, 0, NotSerialized)  // _STA: Status
            {
                Return (0x0F)
            }

            Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
            {
                UartSerialBusV2 (0x002DC6C0, DataBitsEight, StopBitsOne,
                    0x00, LittleEndian, ParityTypeNone, FlowControlNone,
                    0x0040, 0x0040, "\\_SB.FUR1",
                    0x00, ResourceConsumer, , Exclusive,
                    )
                GpioInt (Level, ActiveLow, ExclusiveAndWake, PullDefault, 0x0000,
                    "\\_SB.GPIO", 0x00, ResourceConsumer, ,
                    )
                    {   // Pin list
                        0x0006
                    }
            })
            Name (_S0W, 0x04)  // _S0W: S0 Device Wake State
            Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake
            {
                0x0A,
                0x03
            })
            Name (_DSD, Package (0x02)  // _DSD: Device-Specific Data
            {
                ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
                Package (0x01)
                {
                    Package (0x02)
                    {
                        "compatible",
                        "google,cros-ec-uart"
                    }
                }
            })
        }
    }

BUG=b:147853944

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I7ccb3633332ce3e388293872af7b22f1867c8465
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-23 17:42:35 +00:00
Edward O'Callaghan 5d33d03d3f util/mb/google/tmpl/puff: Fix overridetree.cb to swap USB ports
Switch USB2 port1 and port3 due to circuit change from rev0.

BUG=b:154071868,b:154585046,b:156429564
BRANCH=none
TEST=none

Change-Id: I5b9a20bd657ed587ec891e52f66629d554df6166
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-06-23 01:15:14 +00:00
Edward O'Callaghan b6737fc54a util/mb/google/tmpl/puff: Import overridetree.cb copy
BUG=b:154071868
BRANCH=none
TEST=none

Change-Id: I40faa5f80e78cd73ba5ef977574f7f662c0ab8a1
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-06-23 01:13:12 +00:00
Zhuohao Lee 7587526583 palkia: separate the gpio pins control for the second touch
There are two touch screen controllers on the Palkia device.
One is on the lid; another is on the base. To support
the different control path (for example: turning off the base's
touch event when we don't want to use it however still keeping
the lid's touch event), we use the different gpio pins to control
the second touch. As a result, we need to modify the devicetree
to adopt this change. With this change, we can control the
primary and secondary touch screen controller respectively.

BUG=b:149714955
TEST=lid/base touch screen works correctly

Change-Id: I1f896e334e51c78300af724cbef8d57641ae5612
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-23 00:54:09 +00:00
Edward O'Callaghan 4229dfc215 util/mb/google/tmpl/puff: Generate correct gpio muxing
BUG=b:154071868
BRANCH=none
TEST=none

Change-Id: Iae4fe48b6a3df730b2334cb1f32b35addc90bec0
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-06-23 00:06:56 +00:00
Edward O'Callaghan 6ceca5d064 util/mb/google/tmpl/puff: Fix include paths for gen board
BUG=b:154071868
BRANCH=none
TEST=none

Change-Id: Ifa5cd021ae37d61ddb9eb9bf6a970a931058e33c
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-06-23 00:06:43 +00:00
Edward O'Callaghan e54487f207 mb/google/hatch: Make puff and variants share common mainboard.c
Here we consolidate some of the mainboard.c duplication between
Puff and it's variants.

Customizations can be done later via introducing a devicetree
parameterisation.

BUG=b:154071868
BRANCH=none
TEST=none

Change-Id: I75c2de7ae8efd544d800bc77e34e667c3afa4b01
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42672
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-23 00:06:28 +00:00
Marshall Dawson 6e5e24e2b3 cbmem: Remove IDs for TSEG and BERT
Remove the changes added in
  commit 80df052d3 "cbmem: Add IDs for TSEG and BERT table data"

No platform uses either ID.  TSEG in cbmem is incompatible with stage
cache.  BERT reserved data in cbmem is unusable in Linux.

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I5501424bfeb38d5ff5432678df9e08b4c16258f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42532
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22 22:57:13 +00:00
Marshall Dawson 03743b7fa3 soc/amd/picasso: Set BERT_SIZE to 0 when no table generated
BUG=b:136987699
TEST=Verify no region reserved when CONFIG_ACPI_BERT=n

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I95d511e454e7f2998e46e14112eea5e8b09d59b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-22 22:56:59 +00:00
Marshall Dawson d91d2df2cc soc/amd/picasso: Convert BERT reserved region from cbmem
Picasso's BERT region should not have been moved to cbmem in commit
  901cb9c "soc/amd/picasso: Move BERT region to cbmem".  This
causes an error of "APEI: Can not request [] for APEI BERT registers.

FSP has been modified to set aside a requested region size for BERT,
simiar to TSEG.  Remove the cbmem reservation and locate the region
by searching for the HOB.

BUG=b:136987699
TEST=Check that BERT is allocated

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I20e99390141986913dd45c2074aa184e992c8ebb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42530
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22 22:56:34 +00:00
Elyes HAOUAS a138366f3a src/mainboard: Remove unused include 'sandybridge.h'
Change-Id: I9356a56c34d1c6746cf8acfe931386ffed58ba74
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-22 16:30:48 +00:00
Felix Held 96a7a835bf mb/amd/mandolin/hda_verb: use AZALIA_RESET and AZALIA_PIN_CFG macros
TEST=Doesn't change the resulting binary for BUILD_TIMELESS=1.

Change-Id: I9fccc53c3d56116027e28a9eec6ec27202017a79
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-22 16:24:27 +00:00
Angel Pons 013711b533 sb/intel/i82801ix/fadt.c: Use acpi.h definitions
Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.

Change-Id: I284eec23a8804f7bb18d2ef493c1200c197c109e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-22 14:49:49 +00:00
Angel Pons aaa8ab7ac3 sb/intel/i82801{ix,jx}/hdaudio.c: Use `Azalia` in printk
For some reason, one printk statement begins with `HD Audio` instead of
the more common `Azalia`. Change the different prefix for consistency.

Change-Id: Ia79e340f331b9186cc09b04f925ff9d94204955e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-06-22 14:49:24 +00:00
Angel Pons 98a8b441e5 sb/intel/i82801{gx,ix,jx}/hdaudio.c: Drop unused typedef
Tested with BUILD_TIMELESS=1, Roda RK9 does not change.

Change-Id: I9967d625a8e6d2e1063b9b38965d81a466738964
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-22 14:49:09 +00:00
Angel Pons 7a2864b421 sb/intel/i82801jx/hdaudio.c: Align with i82801ix
The code is pretty much the same, only differing in a comment and a
printk statement.

Change-Id: Ic404ef466636fc05c2baa70aad8a39bb1b458d42
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-22 14:48:57 +00:00
Angel Pons c9d6333ab6 sb/intel/i82801ix/hdaudio.c: Clean up cosmetics
Reflow some comments and add spaces around an operator.

Tested with BUILD_TIMELESS=1, Roda RK9 does not change.

Change-Id: I655d74ecbefa664d79b1af805f92cbcf877a43ac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-22 14:48:20 +00:00
Angel Pons 3bff419824 sb/intel/i82801ix/early_init.c: Reorder functions
Both i82801gx and i82801jx start with the LPC setup function. For some
reason this isn't reproducible, but it should not effect functionality.

Change-Id: I9d26a151757d60e56ed70181ff7aef48e229d322
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-22 14:47:54 +00:00
Angel Pons 9f75f68978 sb/intel/i82801ix: Rename i82801ix_lpc_decode()
For consistency with other Intel southbridges, we rename this function
to `i82801ix_lpc_setup`.

Tested with BUILD_TIMELESS=1, Roda RK9 does not change.

Change-Id: Id8b3bcc9174277e085868866a1b5d90b5c51201a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-22 14:47:37 +00:00
Angel Pons 9b43b89296 sb/intel/i82801{ix,jx}: Correct include guards
These southbridges are not i82801gx.

Tested with BUILD_TIMELESS=1, Roda RK9 does not change.

Change-Id: I6b4c7bc11bcb668adb0aae463defea982cf9059c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-06-22 14:47:12 +00:00
Marshall Dawson 90cd4aaccb vc/amd/fsp/picasso: Sync UPD and GUID files
Update to the latest auto-generated UPD files.  Add the GUID for the
BERT HOB now being reported.

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ia01f626bc85696483173b567bb4f06d308832a91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42529
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22 13:37:03 +00:00
David Wu 3f7a52f00e mb/google/volteer/variants/terrador: Enable Cmd Mirror
Enable CmdMirror for Terrador to achieve optimum routing from SoC to
DRAMs

BUG=b:156435028
BRANCH=none
TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I0db9fff0dddf35c99a6cb2a90d40886ed8e18686
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-22 12:28:34 +00:00
David Wu 63ce260a3e soc/intel/tigerlake: Add CmdMirror option in chip.h
Provide CmdMirror option in chip.h so that it can control CmdMirror FSP
UPD via dev tree.

BUG=b:156435028
BRANCH=none
TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Idae9fa439f077f8f3fb16fe74c2f263c008cd5f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42276
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22 12:28:23 +00:00
Paul Menzel feecdc2c0b mb/emulation/qemu-i440fx,q35: Fix comment style
The comment fits in 96 characters, so do it, also getting rid of the
unwanted multi-line comment style.

Add a dot/period to the end of the sentence.

Change-Id: I7b5c7ea5da00d649aa06361e0e0cf2431874a6ec
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-22 12:28:03 +00:00
Jonathan Zhang 38c9b8045e soc/intel/xeon_sp/cpx: rename xeon_sp_get_cpu_count()
Rename function from xeon_sp_get_cpu_count()
to xeon_sp_get_socket_count().

This function returns CPU socket count, by getting it from the field
named as numCpus in FSP HOB.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: Ic96bdf4ab042ac15d43f9b636185627c63fbf8a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42439
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22 12:27:43 +00:00
Daniel Gröber 5569ee9d13 spi/winbond: Simplify status reg union types
Having speparate types for the status register with three and four block
protection bits respectively doesn't really make sense, it's the same
size either way just a different representation, so one union type will
do.

This allows us to de-duplicate the status register read in
winbond_get_write_protection as well as removing another layer of union
in 'struct status_regs'.

Change-Id: Ie99b98fb6762c8d84d685b110cfc2fd5458b702e
Signed-off-by: Daniel Gröber <dxld@darkboxed.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42111
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22 12:27:24 +00:00
Daniel Gröber a890138968 lockdown: Add hint for how to check for lockdown support in boot log
Change-Id: Iaceb2e82f900e52efcce702486e18d0483665640
Signed-off-by: Daniel Gröber <dxld@darkboxed.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41749
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22 12:27:18 +00:00
Daniel Gröber 16dbbeb895 lockdown: Add Kconfigs for SPI media protection mode
SPI_WRITE_PROTECTION_REBOOT seems to be a Winbond thing, other vendors
such as Macronix only support permanent protection but conditional on
the WP# pin state.

Change-Id: Iba7c1229c82c86e1303d74c7bc8f89662b5bb58c
Signed-off-by: Daniel Gröber <dxld@darkboxed.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41747
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22 12:27:08 +00:00
Nick Vaccaro 231020132c mb/google/volteer/variants/volteer: clean up gpio.c
Remove an unneccessary comment and group the variant_early_gpio_table
together based on GPIO group.

Changed static variable name gpio_table to override_gpio_table to be
more descriptive.

BUG=none
TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot
volteer to kernel.

Change-Id: Iabe810df1e5a3df35e3543ab81b9fdb6f76c223a
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42577
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22 12:25:11 +00:00
Nick Vaccaro f3d399eb8b mb/google/volteer: move volteer devices to overridetree.cb
Move the following volteer-specific devices from baseboard's
devicetree.cb into volteer's overridetree.cb file:
 - Goodix Touchscreen
 - ELAN Touchscreen
 - ELAN Touchpad
 - SAR0 Proximity Sensor

Adjust the other variant's overridetree.cb files to correspond to
the changes made to the baseboard's devicetree.cb in this change.

BUG=b:159241303, b:154646959
TEST='emerge-volteer coreboot chromeos-bootimage', flash and boot
volteer to kernel and verify that the trackpad works.

Change-Id: I30f8266ec87a7cde293c84d3e687d133207b8d59
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-22 12:25:04 +00:00
Nick Vaccaro 2cc060061e mb/google/volteer: update fw_config definition
Update fw_config definition in devicetree.cb to match current
definition for volteer.

BUG=b:159157584
TEST=none

Change-Id: I761893818231880d86fd13cfa61319157d06a7d5
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42331
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22 12:24:51 +00:00
Yu-Ping Wu 59495543db libpayload: gdb: Condition video console init on LP_VIDEO_CONSOLE
With the stub video_console_init() removed from depthcharge in
CL:2241493, depthcharge will fail to compile:

 payloads/libpayload/gdb/stub.c:76: undefined reference to
 `video_console_init'

Since video_console_init() is meant to be implemented in
libpayload, libpayload should be consistent with itself by not calling
this function when it's not implemented (i.e., when !LP_VIDEO_CONSOLE).

Therefore, initialize video console only if LP_VIDEO_CONSOLE is set.

BRANCH=none
BUG=none
TEST=USE="menu_ui" emerge-gale depthcharge

Change-Id: Ic45f9073330258cb77301003484ec525b2404180
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42505
Reviewed-by: Joel Kitching <kitching@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22 12:24:42 +00:00
John Zhao 2c807ff6fe mb/google/volteer: Disable D3Cold for TCSS along with pass through mode
The pass through mode (SW CM) RTD3 is not supported until QS platform.
D3Cold is needed to be disabled along with upstream TBT firmware
signed_TGL_HR_4C_A0_rev6_pre4_SW_CM_PM_support_ENG_VER_perst_check_fix.
This temporary patch will need to be reverted once PM RTD3 support is
validated on QS platform.

BUG=b:159050315
TEST=Verfiy PM S0ix along with upstream TBT firmware.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I98ed991e4185abf1f3168e33b099e0e97c9075f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42504
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Divya Sasidharan <divya.s.sasidharan@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22 12:24:20 +00:00
Tim Wawrzynczak 2dcca0f924 mb/google/volteer: Override power limits with SKU-specific limits
Using guidance from Intel, a new set of power limits (PL1, PL2 & PL4)
are available for TGL-U. They are dependent upon the SKU of the CPU
that the mainboard is running on. Volteer is updated here to use these
new limits.

To accomplish this, the SoC chip config's power_limits_config member
was expanded to an array, which can be indexed by POWER_LIMITS_*_CORE
macros. Just before power limits are applied, the correct set of them
is chosen from the array based on System Agent PCI ID. Therefore, a
TGL board should have two sets of power limits available in the
devicetree.

BUG=b:152639350
TEST=On a Volteer SKU4 (4-core), verified the following console output:
CPU PL1 = 15 Watts
CPU PL2 = 60 Watts
CPU PL4 = 105 Watts

Change-Id: I18a66fc3aacbb3ab594b2e3d6e2a4ad84c10d8f0
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-06-22 12:24:11 +00:00
Raul E Rangel a31a769760 amd/picasso/acpi: Add power resources for I2C and UART
This allows the kernel to runtime suspend these devices and properly
shut them down.  If a tty is not used, the kernel will disable the
device.

I omitted UART0 because the PSP will not power the controller before
accessing it. This causes PSP boot failures. See b/158772504. We also
can't enable UART0 D3 until we stop using the mmio kernel command line
`console=uart,mmio32,0xfedc9000`. The kernel will suspend the UART
controller before it notices that the mmio address matches ttyS0. This
causes the kernel to fail writing to the UART. So we need to move over
to `console=ttyS0`.

BUG=b:153001807, b:157617092, b:157858890, b:158772504
TEST=Boot trembyle and see I2C devices entering and exiting D3.
* See the UART devices entering D3
* Made sure the i2c peripherals were still functional.
* Ran suspend stress test for 40+ iterations.

[    0.349094]     power-0362 __acpi_power_on       : Power resource [FUR1] turned on
[    0.350627]     power-0362 __acpi_power_on       : Power resource [FUR2] turned on
[    0.352094]     power-0362 __acpi_power_on       : Power resource [FUR3] turned on
[    0.353626]     power-0362 __acpi_power_on       : Power resource [I2C2] turned on
[    0.376980]     power-0362 __acpi_power_on       : Power resource [PRIC] turned on
[    0.399997]     power-0362 __acpi_power_on       : Power resource [PRIC] turned on
[    0.401953]     power-0362 __acpi_power_on       : Power resource [I2C3] turned on
[    0.403460]     power-0362 __acpi_power_on       : Power resource [I2C4] turned on
[    0.483646]     power-0418 __acpi_power_off      : Power resource [I2C4] turned off
[    1.028404]     power-0418 __acpi_power_off      : Power resource [I2C3] turned off
[    1.448426]     power-0418 __acpi_power_off      : Power resource [I2C2] turned off
[    5.308094]     power-0418 __acpi_power_off      : Power resource [FUR1] turned off
[    5.340833]     power-0418 __acpi_power_off      : Power resource [FUR2] turned off
[    5.382041]     power-0418 __acpi_power_off      : Power resource [FUR3] turned off
[    5.423861]     power-0362 __acpi_power_on       : Power resource [I2C3] turned on
[    6.698225]     power-0362 __acpi_power_on       : Power resource [I2C2] turned on
[    6.856573]     power-0418 __acpi_power_off      : Power resource [I2C3] turned off
[    8.246970]     power-0418 __acpi_power_off      : Power resource [I2C2] turned off

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I04c4a729d4cb9772ab78586fdbb695b450cc1600
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-22 12:23:07 +00:00
Jonathan Zhang a3db721633 mb/ocp/deltalake: add RW_MRC_CACHE flash region
Add RW_MRC_CACHE flash region to hold MRC cache data.

With memory training skipped for subsequent reboots, the boot
time is reduced by 8 minutes on OCP Delta Lake server, when
FSP verbose logging is turned on.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I27ed00100e1ea9e29b0e71ea5a8397cd550e193a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42025
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22 12:21:35 +00:00
Jonathan Zhang 826523b679 mb/ocp/deltalake: Add OCP Delta Lake mainboard
OCP Delta Lake server is a one socket server platform powered by
Intel Cooper Lake Scalable Processor.

The Delta Lake server is a blade of OCP Yosemite V3 multi-host
sled.

TESTED=Successfully booted on both YV3 config A Delta Lake server
and config C Delta Lake server. The coreboot payload is Linux kernel
plus u-root as initramfs. Below are the logs of ssh'ing into a
config C deltalake server:
jonzhang@devvm2573:~$ ssh yv3-cth
root@ip's password:
Last login: Mon Apr 20 21:56:51 2020 from
[root@dhcp-100-96-192-156 ~]# lscpu
Architecture:          x86_64
CPU op-mode(s):        32-bit, 64-bit
Byte Order:            Little Endian
CPU(s):                52
On-line CPU(s) list:   0-51
...
[root@dhcp-100-96-192-156 ~]# cbmem
34 entries total:

   0:1st timestamp                                     28,621,996
  40:device configuration                              178,835,602 (150,213,605)
...
Total Time: 135,276,123,874,479,544
[root@dhcp-100-96-192-156 ~]# cat /proc/cmdline
root=UUID=f0fc52f2-e8b8-40f8-ac42-84c9f838394c ro crashkernel=auto selinux=0 console=ttyS1,57600n1 LANG=en_US.UTF-8 earlyprintk=serial,ttyS0,57600 earlyprintk=uart8250,io,0x2f8,57600n1 console=ttyS0,57600n1 loglevel=7 systemd.log_level=debug

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: I0a5234d483e4ddea1cd37643b41f6aba65729c8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-22 12:21:18 +00:00
Jonathan Zhang 08ef4f10c7 soc/intel/xeon_sp/cpx: consider stack personality
Each IIO stack has a personality. Only when personality of a stack is
TYPE_UBOX_IIO, the stack has PCIe devices.

For example, for CPX-SP, the stack 3 has personality of TYPE_UBOX, it
does not have PCIe devices.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: I2f6bfdac4d1110dd95f1b3a72e2e51f70c79212b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42333
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22 12:21:04 +00:00
Jonathan Zhang 7ba0e99127 soc/intel/xeon_sp/cpx: update ACPI xSDT
Add uncore devices, interrupt definition, gnvs to xSDT tables.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: I2fa9c26abc6aef2d255535c2abf8b6b67d26359f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40927
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22 12:20:51 +00:00