Commit Graph

35200 Commits

Author SHA1 Message Date
David Wu 7c040adc8c mb/google/volteer/var/voxel: Update gpio settings and overridetree.cb
Based on schematic and gpio table of voxel, generate gpio settings
and overridetree.cb for voxel.

BUG=b:157879197,b:155062762
TEST=FW_NAME=voxel emerge-volteer coreboot chromeos-bootimage
Verify that the image-voxel.bin is generated successfully.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I49c1923e63d87f11de362fd893905ac2f1137bba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-07-06 06:15:27 +00:00
Julius Werner 63358eaff6 libpayload: cbgfx: Fix add_fractions() overflow reduction
log2(1) is 0 and log2(0) is -1. If we have the int64_t 0xffffffff then
log2(0xffffffff >> 31) = log2(0x1) = 0, so the current reduction code
would not shift. That's a bad idea, though, since 0xffffffff when
interpreted as an int32_t would become a negative number.

We need to always shift one more than the current code does to get a
safe reduction. This also means we can get rid of another compare/branch
since -1 is the smallest result log2() can return, so the shift can no
longer go negative now.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ib1eb6364c35c26924804261c02171139cdbd1034
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Joel Kitching <kitching@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-07-06 06:14:57 +00:00
Chris Wang a94136f082 mb/google/zork: Apply cereme telemetry settings for dalboz
Currently, the telemetry settings are not for the pollock platform
and might causethe power and performance issue. so applied the Pollock
reference board settings to Dalboz to improve the performance,
and the values need to be updated after the SDLE test finished.

BUG=b:157961590,b:152922299
TEST=Build.

Change-Id: I0da5b81afaa5814c13ec0257dc0eb3471be94c29
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2228257
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42998
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06 06:14:31 +00:00
Chris Wang 1e3e528d23 mb/google/zork: Apply USB2 default phy tune parameter for Zork family
Apply the default USB2 phy tuning parameter for Zork family

BUG=b:155132211
TEST=Build, verified the default value been applied on trembyle
and the USB2 device works well.

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I1f00b04173796d70147e232bafa405487b0761e1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2260216
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42997
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06 06:14:17 +00:00
Chris Wang 04dfc26f94 mb/google/zork: Add USB2 phy tuning parameter for SI tuning
Add the USB2 phy tuning parameter to adjust the USB 2.0 PHY driving strength.

BUG=b:156315391
TEST=Build, verified the tuning value been applied on Trembyle.

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I3d31792d26729e0acb044282c5300886663dde51
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2208524
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Tested-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-06 06:14:07 +00:00
Caveh Jalali 6e62223f01 mb/google/volteer: Add support for passive USB-C daughterboard
The USB-C SBU and HSL orientation configuration depends on the USB
daughterboard used on the system. This patch adds an additional
configuration for supporting passive USB daughterboards using "probe"
directives to select the appropriate configuration at runtime.

BUG=b:158673460
TEST=verified active USB DBs enumerate at USB3 speeds in linux

Signed-off-by: Caveh Jalali <caveh@chromium.org>
Change-Id: Ia4bd97de8f974531f97469a5e47ecf4d948beca9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-06 06:12:14 +00:00
Karthikeyan Ramasubramanian 11715d8dc6 mb/google/dedede: Create Boten Legacy variant
Upcoming builds of boten will use 16 MiB SPI ROM. So create a legacy
Boten variant to support the builds that use 32 MiB SPI ROM.

BUG=None
TEST=Build the boten and boten_legacy variant.

Cq-Depend: TBD
Change-Id: Idf7732768aa7fbf2281a4cbf47b7b5b4f8ef51da
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-07-06 06:11:45 +00:00
Karthikeyan Ramasubramanian dab20f887e mb/google/dedede: Create Drawcia Legacy variant
Upcoming builds of drawcia will use 16 MiB SPI ROM. So create a legacy
Drawcia variant to support the builds that use 32 MiB SPI ROM.

BUG=None
TEST=Build the drawcia and drawcia_legacy variant.

Cq-Depend: TBD
Change-Id: Ifb5a4778abe38a396e35963a3270b0d3cc9809e0
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-07-06 06:11:37 +00:00
Kyösti Mälkki 8d119fcfba soc/amd/common: Fix missing gpio_banks.h include
Change-Id: I2c92280f3bbd80bd7a0d3abfb2fddcef997e144e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-06 06:09:28 +00:00
Raul E Rangel 30d7b54742 soc/amd/picasso/memlayout: Verify bootblock is 16-bit aligned
The bootblock must be 16-bit aligned for it to boot.

BUG=b:159081993
TEST=Made sure trembyle still compiles.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I29c244a3f08df46c5992fe81683b9c0d740ff248
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-06 06:08:55 +00:00
Maulik V Vaghela e927d9b3ad soc/intel/jasperlake: set SerialIoUartDebugMode to skip Uart Init
Since coreboot is initializing uart for debug logs, fsp should not reinitialize it.
Thus we need to set FSP UPD to skip Uart init in FSP and use settings done by coreboot

BUG=None
BRANCH=None
TEST=FSP is able to push debug logs on UART with this setting

Cq-Depend: TBD
Change-Id: I0fda2ace3b1f63159e9809d6a3044a3bad452f07
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2020-07-06 06:08:24 +00:00
Ronak Kanabar a8b80942a0 vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2194
The FSP-M/S headers added are generated as per FSP v2194.

BUG=b:159193895
BRANCH=None
TEST=Build and boot JSLRVP

Cq-Depend: TBD
Change-Id: I0cd84fdb0089bf8ea3f4440e89fdee7f11119751
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42471
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06 06:08:03 +00:00
Marshall Dawson 4d38c7546c soc/amd/picasso: Use PSP Sx command only for S3
Skip sending MboxBiosCmdSxInfo for sleep states other than S3.  The
PSP only acts on S3 and ignores all others.  As a result, the command
register is not cleared upon return and coreboot reports a timeout.

BUG=b:153622879
TEST=Use halt from command line, verify command skipped.

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ic47b8507e29e4c53898e88fb46e532b71df87d07
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-06 03:32:54 +00:00
Paul Menzel 6663ad99cf arch/x86: Support x86_64 exceptions
*   Doesn't affect existing x86_32 code.

Tested on qemu using division by zero.
Tested on Lenovo T410 with additional x86_64 patches.

Change-Id: Idd12c90a95cc2989eb9b2a718740a84222193f48
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-05 19:56:09 +00:00
Furquan Shaikh d9c6862809 mb/google/zork: Drop check for ENV_RAMSTAGE in mainboard_ec_init
This change drops the check for ENV_RAMSTAGE in mainboard_ec_init()
since it is included only in ramstage. Also, the content of
ramstage_ec_init() is moved into mainboard_ec_init().

Change-Id: I282fb07a80f4de6064a544f6dd58e8f973a597b9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43118
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05 18:35:00 +00:00
Furquan Shaikh 484f107ac4 mb/google/zork: Drop mainboard_ec_init() from romstage
mainboard_ec_init() does nothing in any stage other than ramstage. So,
this change drops the call to mainboard_ec_init() from
romstage.c. Additionally, it also drops ec.c from romstage and
verstage.

Change-Id: Iae0be4d678b0780cf532000a6c0fff1bce333c0e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43117
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05 18:34:51 +00:00
Furquan Shaikh fa78dd16bf mb/google/zork: Drop unused function variant_romstage_entry()
This change drops the function `variant_romstage_entry()` which is
unused on zork.

Change-Id: I140ab3e837971c4c7dbef5d27616043b5fc6c2c9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43116
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05 18:34:31 +00:00
Furquan Shaikh 8b6b07b942 ec/google/chromeec: Drop codec.asl
This change drops codec.asl file from Chrome EC since it is now
unused.

Change-Id: I6c2f3e53b14aaf76b9c6d038a732e79a4d7bb2f1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43043
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05 18:34:23 +00:00
Furquan Shaikh e284bff9cf mb/google/zork: Use SSDT generator for Chrome EC audio codec device
This change drops the inclusion of codec.asl in DSDT for `GOOG0013`
device and instead uses the newly added Chrome EC audio codec driver
for filling in the device node in SSDT.

TEST=Verified that following node gets generated:
Scope (\_SB.PCI0.LPCB.EC0.CREC)
{
	Device (ECA0)
	{
		Name (_HID, "GOOG0013")  // _HID: Hardware ID
		Name (_UID, One)  // _UID: Unique ID
		Name (_DDN, "Cros EC audio codec")  // _DDN: DOS Device Name
		Method (_STA, 0, NotSerialized)  // _STA: Status
		{
			Return (0x0F)
		}
	}
}

Change-Id: I3e626ce01a3735ac2c966c0e95310be4c828b241
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43042
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05 18:34:12 +00:00
Furquan Shaikh 31b816b42f ec/google/chromeec: Add driver for audio codec device
This change adds driver for audio codec device (HID `GOOG0013`) living
behind Chrome EC. This driver generates the required ACPI node for the
codec device. In a later change, GOOG0013 device will be dropped
the .asl file.

Change-Id: Ib2759eac60265ef81df70af1d4f1f72bd9d987e8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43041
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05 18:34:02 +00:00
Furquan Shaikh dfd7e9d560 ec/google/chromeec: Move if EC_GOOGLE_CHROMEEC to i2c_tunnel/Kconfig
This change moves `if EC_GOOGLE_CHROMEEC` from chromeec/Kconfig to
chromeec/i2c_tunnel/Kconfig. This is done to make it clear that the
Kconfig file in i2c_tunnel is sourced unconditionally, but the configs
in i2c_tunnel/Kconfig are conditionally defined based on the
evaluation of if condition.

This change addressed the feedback received on
https://review.coreboot.org/c/coreboot/+/40515/11/src/ec/google/chromeec/Kconfig#200.

Change-Id: I66cd91d6b1813ff6d0fb7be719e2da65ac6ac23b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43040
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05 18:33:53 +00:00
Furquan Shaikh ee68b88bab mb/google/kahlee: Drop macro H1_PCH_INT
This change drops H1_PCH_INT macro for GPIO_9 since it is the same
across all variants. Also, the name differed from the schematics
version `H1_PCH_INT_ODL` creating confusion.

Change-Id: I7b038426a984d8abc460a0da3ee1dc5559d7ad5f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-07-05 18:33:47 +00:00
Angel Pons aff9f54e6b arch/x86/Makefile.inc: Drop unused reset.c rule
No x86 mainboard has a reset.c file.

Change-Id: I167629c7addf485944926d57cf0228606c0f32e5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42582
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05 17:04:18 +00:00
Angel Pons 06a70e0a7c mb/supermicro/x9scl: Select IPMI_KCS
Needed for `chip drivers/ipmi` in the devicetree.

Change-Id: Ice70aab7cedaeb91a33dd90d763c5a487f190b8f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41687
Reviewed-by: Michael Niewöhner
Reviewed-by: Jonathan Kollasch <jakllsch@kollasch.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05 11:32:34 +00:00
Kyösti Mälkki 9cc6493e8f drivers/pc80/tpm: Remove support code if TPM is disabled
Change-Id: I7015d4bf6f536c5cea8e1174db81f09f756ae0e5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Michael Niewöhner
2020-07-05 11:32:17 +00:00
Kyösti Mälkki 1be23b0733 mb/lenovo/x230s: Add MAINBOARD_HAS_LPC_TPM
With devicetree listing drivers/pc80/tpm, it is compulsory
to have the corresponding driver included in the build.
Followup work will drop the associated weak function
declaration that util/sconfig currently generates.

Change-Id: Ife8deb2c973ab7c7b820244b6f72efd3b56570ae
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43047
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05 11:31:09 +00:00
Kyösti Mälkki f91cd6970e mb/google/poppy-nocturne: Add SX9310 driver unconditionally
Change-Id: I11b02cc5f8b59559443329fe0c49a6fb82b7862a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41726
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05 11:29:21 +00:00
Patrick Rudolph 56fdafbaff drivers/pc80/tpm/tis: Add x86_64 support
Fix integer with different size to pointer conversion on x86_64.

Change-Id: Ic06a32d549b694310f4c724246f28fed15acf83f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42983
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05 08:52:56 +00:00
Patrick Rudolph 34a5a9b3e6 include/cpu/x86/lapic: Add support for x86_64
Fix integer with different size to pointer conversion.

Change-Id: I9c13892b2d79be12cc6bf7bc0a5e3a39b64032a1
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42984
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05 08:52:33 +00:00
Tim Wawrzynczak e414ce4532 drivers/intel/pmc_mux: Rename con driver to conn
For historical reasons, Windows has issues with certain names being
used for files and directories, 'con' or 'CON' being one of
them. Therefore, rename the pmc_mux/con driver to pmc_mux/conn in
order to work around this issue.

TEST=built volteer (only user of this driver as of now)

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ia78dc4efe647c96a7169a3b95fc3b8944d052c83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-07-04 21:59:00 +00:00
Patrick Georgi 54be395a9b smbios: TYPE_NONE and TYPE_OTHER are already taken
Change-Id: Ic66f7c919a71cb53773d5056e5f756cd6faf4909
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43135
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04 20:39:10 +00:00
Sindhoor Tilak e5f25cee1c post_code: reorganize order of postcode defines
Currently, the certain postcode values aren't in increasing
order of values.

The change, just reorganzies the defines in increasing order
of the values

Signed-off-by: Sindhoor Tilak <sindhoor@sin9yt.net>
Change-Id: Id5f0ddc4593f689829ab9a7fdeebd5f66939bf79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-07-04 11:36:04 +00:00
Johnny Lin ad0ccb336d drivers/ocp/dmi: Add OCP_DMI driver for populating SMBIOS from IPMI FRU data
It implements the SMBIOS IPMI FRU mapping table defined in
https://www.opencompute.org/documents/facebook-xeon-motherboard-v31
22.3 SMBIOS FRU mapping table.
Mainboard needs to configure the correct values for FRU_DEVICE_ID and BMC_KCS_BASE.

For type 11 string 1 to 6 are common and implemented in this driver, the
rest are project dependent and can be added in the mainboard code.

Tested on OCP Tioga Pass.

Change-Id: I08c958dfad83216cd12545760a19d205efc2515b
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40308
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04 11:31:16 +00:00
Jonathan Zhang 29f61a2110 soc/intel/xeon_sp/cpx: update HOB display code
Fix a typo to use CONFIG_DISPLAY_HOBS instead of CONFIG_DISPLAY_HOB.

Build hob display into romstage, in addition to ramstage.

Memory map HOB data is a big structure. Update the soc_display_memmap_hob()
to assist trouble shooting of FSP interface.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Iece745fe21d11b4a470ba8318201bb6e68c5da26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42841
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04 11:25:50 +00:00
Johnny Lin 37f38505f2 mb/ocp/deltalake: Add VPD flash regions and select VPD and VPD_SMBIOS_VERSION
Tested on OCP Delta Lake.

Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: I1e6e2bd25cbe3b0c0547dda9e457c4d55df28388
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42428
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04 11:24:05 +00:00
Johnny Lin 5e8709f89e mb/ocp/deltalake: Update SMBIOS type 2 Location In Chassis from BMC
There are 4 slots in YV3, Location In Chassis should be 1~4.

Tested=on OCP Delta Lake, dmidecode -t 2 verified the string is correct.

Change-Id: I3b65ecc6f6421d85d1cb890c522be4787362a01b
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-07-04 11:23:56 +00:00
BryantOu 4a8e58fd93 arch/x86/smbios: Add SMBIOS type8 data
Refer to section 7.9 Port Connector Information of DSP0134_3.3.0
to add type 8 data, the table of data should be ported according
to platform design and MB silkscreen.

Change-Id: I81e25d27c9c6717750edf1d547e5f4cfb8f1da14
Signed-off-by: BryantOu <Bryant.Ou.Q@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-04 11:21:18 +00:00
Johnny Lin b8899ef7e7 lib/coreboot_table: Add Intel FSP version to coreboot table
Add a new LB_TAG_PLATFORM_BLOB_VERSION for FSP version, it would
add Intel FSP version to coreboot table LB_TAG_PLATFORM_BLOB_VERSION
when PLATFORM_USES_FSP2_0 is selected.

Tested=On OCP Delta Lake, with an updated LinuxBoot payload cbmem utility
can see "LB_TAG_PLATFORM_BLOB_VERSION": "2.1-0.0.1.120"

Change-Id: I92a13ca91b9f66a7517cfd6784f3f692ff34e765
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-07-04 11:20:08 +00:00
Kyösti Mälkki 542cffacbb drivers/pc80/tpm: Remove LPC_TPM
Replace uses with MAINBOARD_HAS_LPC_TPM, if drivers/pc80/tpm
is present in devicetree.cb it is necessary to always include
the driver in the build.

Change-Id: I9ab921ab70f7b527a52fbf5f775aa063d9a706ce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
2020-07-04 11:17:44 +00:00
Jonathan Zhang 34cfeee406 doc/mb/ocp: Add documentation for Delta Lake
Add OCP platform Delta Lake documentation.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I9216c80023db071591c8d3add7c0f041e9e6b97e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-04 11:16:44 +00:00
Christian Walter 02b3937083 MAINTAINERS: Add Maintainers for Prodrive Hermes Mainboard
Change-Id: Ifaed81016be9cd2845b3a2c55ee1a5ac4d317081
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-04 11:16:19 +00:00
Johnny Lin 407b35aa9f mb/ocp/deltalake: Populate SMBIOS data and set the read PPIN to BMC
1. Populate SMBIOS data from OCP_DMI driver read from FRU and PPIN MSR
   for OEM string 1 to 6, add string 8 for PCIE configuration.
2. Set the read PPIN MSR to BMC.

Tested on OCP Delta Lake.

Change-Id: I9127cf5da1c56d8012694d070615aec24cc22fdf
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41279
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04 11:15:23 +00:00
Johnny Lin 54a7f41de1 soc/intel/xeon_sp: Add read CPU PPIN MSR function
These changes are in accordance with the documentation:
[*] page 208-209
    Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual,
    Volume 4: Model-Specific Registers. May 2019.
    Order Number: 335592-070US

Tested on OCP Tioga Pass and Delta Lake.

Change-Id: I8c2eac055a065c06859a3cb7b48ed59f15ae2fc4
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42901
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04 11:15:11 +00:00
Johnny Lin 99198b2f76 drivers/ipmi: Add IPMI KCS support in romstage
It's necessary to run IPMI commands in romstage for writing error SEL
such as memory initialization error SEL, and also for other usages
such as starting FRB2 timer, OEM commands, etc.

Add CONFIG_BMC_KCS_BASE for BMC KCS port address that can be used
across romstage and ramstage.

Change-Id: Ie3198965670454b123e570f9056673fdf515f52b
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40234
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04 11:14:44 +00:00
Subrata Banik f861f99967 soc/intel/tigerlake: Remove unused EHL DID from TGL SoC
TEST=Able to build and boot TGLRVP.

Change-Id: I7be3cb0bd63778e34c810d69e68b584691225f7a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-04 09:52:10 +00:00
Jamie Ryu eb1f5bc079 mb/google/volteer: Enable CSE Lite SKU for ES2 platforms
BUG=b:158140797
TEST=build and boot volteer with CSE Lite SKU
Cq-Depend: chrome-internal:3100721

Change-Id: I4f939883617a1271b30c76d41e61113bbdd6ab5b
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42070
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03 23:56:55 +00:00
Jamie Ryu 02a1b338f8 soc/intel/tigerlake: Disable hybrid storage mode in CSE Lite RO boot
A UPD HybridStorageMode allows a platform to dynamically configure the
PCIe strap configuration required if an Optane device is connected.
The strap configuration is done by HECI commands between FSP and CSE to
override the default PCIe strap value, and the updated strap value is
stored in SPI RW data to be used on the next boot.

CSE Lite supports the strap override when running on CSE RW partition,
while CSE RO partition does not support it because CSE RO is not allowed
to access SPI RW data. The strap override failure on CSE RO causes FSP
not initializing PCH Clkreq and PCIe port mapping and this results NVMe
and Optane initialization failure.

By disabling HybridStorageMode in case of CSE RO boot, NVMe detection is
done by the default PCIe configuration and Optane is detected as a
single NVMe storage device on CSE RO boot in recovery mode. Both NVMe
and Optane devices detection as well as OS installation to these storage
devices are verified on CSE RO boot in recovery mode.

BUG=b:158643194
TEST=boot and verified with tglrvp and volteer in recovery mode
Cq-Depend: chrome-internal:3100721

Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: I5397cfc007069debe3701bf1e38e81bd17a29f0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42282
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03 23:56:34 +00:00
Patrick Georgi 401671c7ab Update vboot submodule to upstream master
Updating from commit id c531000f:
2020-05-18 20:55:55 +0000 - (vboot: Add recovery reason code for CSE Lite SKU errors)

to commit id 68de90c7:
2020-07-02 11:31:05 +0000 - (Allow building for non-CrOS environments)

This brings in 59 new commits.

Change-Id: I7f3c30511ff4acc60e3581bdab89d685dc7beaa5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43008
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03 21:03:19 +00:00
Aaron Durbin 76fcf82901 mb/google/zork: adjust eSPI virtual irq settings
The eSPI polarity macros were reversed. Those are fixed so adjust
the corresponding values related to the correct expectations of
the IRQ path: eSPI virtual wire IRQs are active level high. The EC
sends active level high virtual wire IRQs. The default interrupt
encodings in ACPI for P2/S devices are active edge high. Therefore,
there is no need to override anything.

BUG=b:157984427

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ia28d82cd9e432df98839f68bac4eae4447455e53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-03 15:36:30 +00:00
Aaron Durbin d3758540a9 soc/amd/common: fix eSPI virtual wire polarity encoding
eSPI interrupts are active level high. The eSPI polarity register
in the chipset inverts incoming signals if the corresonding bit
is 0 in the register. Therefore, all active high (edge or level)
virtual wire interrupts need to ensure they are not inverted.

And really the sender of the interrupts should be conforming to the
the eSPI spec. As such inverting any signals should not be necessary,
but this register in the chipset allows for fixing up those misbehaviors.

BUG=b:157984427

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I7346bb0484506d96d7ab2e6d046ffa0571683a48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-03 15:35:44 +00:00