Conditionally add a debug spinloop to enable easy connection of JTAG
debuggers.
TEST=Build and run on Galileo Gen2 with a JTAG debugger.
Change-Id: I7a21f9e6bfb10912d06ce48447c61202553630d0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15127
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This reverts commit 5ede3d8cce.
No longer needed due to FSP being updated, with the 139_40 release,
to accept StackBase field
BUG=chrome-os-partner:52784
BRANCH=none
TEST=built and booted with FSP 139_40
Change-Id: Ic832d8dc4ca87631f5fef80d4d41558d9a72630a
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/15068
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
FSP 2.0 spec has updated the signatures for the FSPM and FSPS blobs
with the 139_40 release. In order to successfully pass through
memory/silicon init the header files must be updated to the latest
versions
BUG=chrome-os-partner:52784
BRANCH=none
TEST=built and booted
Change-Id: Ib60d0d9afa4ee29dff26177826ba59db81b630e8
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/15066
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Scan the boot block when building it with C_ENVIRONMENT_BOOTBLOCK
selected.
TEST=Build and run with Galileo Gen2
Change-Id: I922f761c31e95efde0975d8572c47084b91b2879
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15130
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Add car_stage_entry as an optional routine in the checklist.
TEST=Build and run on Galileo Gen2
Change-Id: I52f6aefc2566beac01373dbebf3a43d35032a0df
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15129
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Support ROM_SIZE greater than 16 MiB. Work around SMBIOS rom size
limitation of 16 MiB by specifying 16 MiB as the ROM size.
TEST=Build and run on neoncity
Change-Id: I3f464599cd8a1b6482db8b9deab03126c8b92128
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15108
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
EMMC TX DATA Control needs to be programmed to 0x1A1A to make amenia
system can run stable on EMMC with HS400 mode.
Change-Id: I42c23ff7e6956e75de5e1b1339a570b35d999301
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Tested-by: Petrov, Andrey <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15092
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Support the common Intel LPSS I2C driver for the 6 I2C bus controllers
that are present on the Skylake-LP PCH with a 120 mHz clock. The
required lpss_i2c_base_address() method is implemented separately for
verstage/romstage and ramstage environments.
This provides methods to convert to and from "struct device" and the
I2C controller bus number for that device. These are used to provide
support for the "I2C Bus Operations" that are present in the coreboot
devicetree.
To support the I2C controller before ramstage an early init function
is provided to do minimal initializaiton of the PCI device and assign
a temporary base address for use before memory. The final base
address is assigned during device enumeration and used during ramstage.
Because it is usually not necessary to enable I2C controllers before
ramstage a config register for the devicetree is provided to perform
early initialization of this controller. In addition the bus speed
can be set in the devicetree and that speed will be applied when the
device is initialized. If not provided the default speed is set to
I2C_SPEED_FAST.
This was tested with the google/chell mainboard by reading and writing
from the trackpad and codec devices during both verstage and ramstage.
Change-Id: Ia0270adfaf2843a3be4e00c732c85401a3401ef5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15105
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Allow reg_script to be used during the bootblock.
TEST=Build and run on Galileo Gen2
Change-Id: I55fe0be3f50116927b801ce67a3f23bb1931f6e7
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15131
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Don't write reserved bits in the Quark platform. Follow the previous
boot behavior and just enable SSE.
TEST=Build and run on Galileo Gen2
Change-Id: Ib3143eff02b2610b595bd666c10d70e43103ccda
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15128
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add asmlinkage to bootblock_main_with_timestamp so that it may be called
directly from the assembly code.
TEST=Build for Amenia and Galileo Gen2
Change-Id: Iefb8e5c1ddce2ec495b9272966b595d5adcebc1c
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15125
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move the existing I2C voltage configuration variable into a new
structure that is equivalent, similar to how USB ports are configured.
This is to make room for additional I2C configuration options like
bus speed and whether to enable the bus in early boot which are coming
in a subsequent commit.
The affected mainboards are updated in this commit so it will build.
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Id2dea3df93e49000d60ddc66eb35d06cca6dd47e
Reviewed-on: https://review.coreboot.org/15104
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add the voltage tolerance GPIO attribute for configuring I2C/I2S buses
that are at 1.8V. This is currently done by passing in a value to FSP
but it is needed earlier than FSP if the I2C bus is used in verstage.
This does not remove the need for the FSP input parameter, that is
still required so FSP doesn't disable what has been set in coreboot.
The mainboards that are affected are updated in this commit.
This was tested by exercising I2C transactions to the 1.8V codec while
in verstage on the google/chell mainboard.
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I93d22c2e3bc0617c87f03c37a8746e22a112cc9c
Reviewed-on: https://review.coreboot.org/15103
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Add a function similar to broadwell to set the PRR for a region of
flash and protect it from writes. This is used to secure the MRC
cache region if the SPI is write protected.
BUG=chrome-os-partner:54003
BRANCH=glados
TEST=boot on chell, verify PRR register is set and that the
MRC cache region cannot be written if the SPI is write protected.
Change-Id: I925ec9ce186f7adac327bca9c96255325b7f54ec
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Id: abb6f645f5ceef3f52bb7afd2632212ea916ff8d
Original-Change-Id: I2f90556a217b35b7c93645e41a1fcfe8070c53da
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/349274
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-on: https://review.coreboot.org/15102
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add a generic LPSS I2C driver for Intel SOCs that use the Synopsys
DesignWare I2C block and have a similar configuration of that block.
This driver is ported from the Chromium depthcharge project where it
was ported from U-Boot originally, though it looks very different now.
From depthcharge it has been modified to fit into the coreboot I2C
driver model with platform_i2c_transfer() and use coreboot semantics
throughout including the stopwatch API for timeouts.
In order for this shared driver to work the SOC must:
1) Define CONFIG_SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ to set the clock
speed that the I2C controller core is running at.
2) Define the lpss_i2c_base_address() function to return the base
address for the specified bus. This could be either done by looking
up the PCI device or a static table if the controllers are not PCI
devices and just have a static base address.
The driver is usable in verstage/romstage/ramstage, though it does
require early initialization of the controller to set a temporary base
address if it is used outside of ramstage.
This has been tested on Broadwell and Skylake SOCs in both pre-RAM and
ramstage environments by reading and writing both single bytes across
multiple segments as well as large blocks of data at once and with
different configured bus speeds.
While it does need specific configuration for each SOC this driver
should be able to work on all Intel SOCs currently in src/soc/intel.
Change-Id: Ibe492e53c45edb1d1745ec75e1ff66004081717e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15101
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In order to support doing bus operations on an I2C device that is
described in the devicetree there needs to be some linkage of the
device and the existing opaque I2C controller bus number.
This is provided in a similar fashion to the existing SMBUS operations
but modified to fit within the existing I2C infrastructure.
Variants of the existing I2C helper functions are provided that will
obtain the bus number that corresponds to this device by looking for
the SOC-provided I2C bus operation structure to provide a function
that will make that translation.
For example an SOC using a PCI I2C controller at 0:15.0 could use:
soc/intel/.../i2c.c:
static int i2c_dev_to_bus(struct device *dev)
{
if (dev->path.pci.devfn == PCI_DEVFN(0x15, 0))
return 0;
return -1;
}
static struct i2c_bus_operation i2c_bus_ops = {
.dev_to_bus = &i2c_dev_to_bus
}
static struct device_operations i2c_dev_ops = {
.ops_i2c_bus = &i2c_bus_ops
...
}
With an I2C device on that bus at address 0x1a described in the tree:
devicetree.cb:
device pci 15.0 on # I2C0
chip drivers/i2c/sample
device i2c 1a.0 on end
end
end
That driver can then do I2C transactions with the device object
without needing to know that the SOC-specific bus number that this
I2C device lives on is "0".
For example it could read a version value from register address 0
with a byte transaction:
drivers/i2c/sample/sample.c:
static void i2c_sample_enable(struct device *dev)
{
uint8_t ver;
if (!i2c_dev_readb(dev, 0x00, &ver))
printk(BIOS_INFO, "I2C %s version 0x02x\n", dev_path(dev), ver);
}
Change-Id: I6c41c8e0d10caabe01cc41da96382074de40e91e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15100
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Pass the serial port address to FSP using a UPD value in the MemoryInit
API.
TEST=Build and run on Galileo Gen2
Change-Id: I86449d80310b7b34ac503ebd2671a4052b080730
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15079
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This patch enable and configure the clocks and IOMUX for i2s audio path,
and the i2s0 clock is from CPLL.
Please refer to TRM V0.3 Part 1 Chapter 3 CRU, P126/P128/P144/P154/P155
for the i2s clock div and gate setting.
BRANCH=none
BUG=chrome-os-partner:52172
TEST=boot kevin rev1, press ctrl+u and hear the beep voice.
Change-Id: Id00baac965c8b9213270ba5516e1ca684e4304a6
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 9c58fa7
Original-Change-Id: I130a874a0400712317e5e7a8b3b10a6f04586f68
Original-Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/347526
Original-Commit-Ready: Wonjoon Lee <woojoo.lee@samsung.com>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15034
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
This configures and enables SPI interface #5 used for EC
communications on Gru/Kevin.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=with the appropriate depthcharge change it is possible to trigger
booting Chrome OS from the SD card by pressing '^U' on Gru
keyboard at the right time.
Change-Id: I5304bf47e030c0b9b7794752f30ffdca6c03a4f4
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: b5cc177
Original-Change-Id: I99883daa60562ccddfaeb858c1957d497f05a501
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/346632
Reviewed-on: https://review.coreboot.org/15032
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Set board GPIOs as required and add their description into the
appropriate section of the coreboot table, to make them available to
depthcharge.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=with the rest of the patches applied it is possible to use
keyboard on Gru, which indicates that the EC interrupt GPIO is
properly configured. The rest of the pins will be verified later.
Change-Id: I5818bfe855f4e7faa2114484a9b7b44c7d469727
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: e02a05f
Original-Change-Id: I82be76bbd3211179e696526a34cc842cb1987e69
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/346631
Reviewed-on: https://review.coreboot.org/15031
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
I'm not even sure how this slipped through... looks like it had never
been there in the first place. Anyway, on ARM exceptions should always
be reinitialized in all stages to make sure the handlers are still
around (especially in an OVERLAP_VERSTAGE_ROMSTAGE board like this one).
Change-Id: Ic74ea1448d63b363f2ed59d9e2529971b3d32d9a
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15099
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This defines mux settings for the GPIO bank responsible for SPI
interface #5.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=with the rest of the patches applied it is possible to
communicate with the EC on gru: pressing Ctrl-U during boot
allows to start Chrome OS from the SD card.
Change-Id: Ibc2293b5662892f7b275434f9a672ef68edf4f9e
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 4f92452
Original-Change-Id: Idf55c069b05492f8cdc204a8c273e39a19a3aef3
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/346630
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-on: https://review.coreboot.org/15030
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
The same GPIOs are used on both platforms, definitions are added an a
new .h to make it easier to re-use them across the code.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=panel backlight still enabled on Gru as before. The rest of the
GPIOs are used in the upcoming patches.
Change-Id: If06f4b33720ab4bf098d23fb91322bba23fe6e90
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: c587880
Original-Change-Id: I1a6c5b5beb82ffcc5fea397e8e9ec2f183f4a7e0
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/346219
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-on: https://review.coreboot.org/15029
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
The current implementation from Vladimir simply dumps 1 MB of memory
contents starting at the base address of the second PCI device (which
most likely is the VGA controller on Intel systems). This locks up a
number of different systems, e.g. my Ibex Peak-based T410s.
This patch documents the issue and stops dumping the graphics registers
for the -a/--all parameter.
Change-Id: I581bdc63db60afaf4792bc11fbeed73aab57f63a
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/14627
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Previous FSP implementations in coreboot have included FspUpdVpd.h
directly, along with with efi headers. Instead of taking that
approach in FSP 2.0, we provide a semantic patch that, with minimal
modifications, makes FspUpdVpd.h easier to include in coreboot, and
eliminates reliance on external headers and definitions.
Change-Id: I0c2a6f7baf6fb50ae22b64e08e653cfe1aefdaf9
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/13331
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enable virtual dev switch config.
BUG=None
TEST= On Dev FW screen, press SPACE key to boot to normal mode
Change-Id: I0fba36ed85025e4d17da106978dcc88497afee09
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/15080
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Including the SeaBIOS bootorder file seems to be a fairly common desire,
so let's make it easy.
Change-Id: Ib0874dee46215287b09c0b52648072ef3ff06ec5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15076
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* Add ADI vendor
Copy Intel Mohon Peak mainboard to ADI vendor. No functional changes,
only string and ifdef names changed.
Change-Id: I25a6d0ec549c79a8ff149d39f72648f625dc36fe
Signed-off-by: Chris Ching <chingcodes@google.com>
Reviewed-on: https://review.coreboot.org/14778
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
thermal.h still has references to X230 in include guard since it
seems to have been copied from that port. Code formatting changes
in romstage.c.
Change-Id: Id8bd931bed127036e8bb4ab604d9d6145f767e56
signed-off-by: Jan Tatje <jan@jnt.io>
Reviewed-on: https://review.coreboot.org/15071
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Adds a label for each tool included in the cbfstool package
in order to build them more easily through Make.
Change-Id: Id1e5164240cd12d22cba18d7cc4571fbadad38af
Signed-off-by: Antonello Dettori <dettori.an@gmail.com>
Reviewed-on: https://review.coreboot.org/15075
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since the sd card cmd, data, cd lines are configured
as native mode, allow the native controller to control
the termination.
Configure SDCARD_CLK_FB which is used for calibrating the
timing of the actual clock buffer.
BUG==chrome-os-partner:53747
TEST=verify sd card detection
Change-Id: I56611826afb4fb32fefa7f1e4ba19ca4f30ba578
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/348377
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15096
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
This creates a config for the x60 audio based
on values taken from vendor bios.
The pin config is stored in (for linux 4.5 at least):
/sys/class/sound/card0/hw*/init_pin_configs
In the left column there is the pin number.
In the right column there is the default configuration of that pin.
(This has to be done while running the proprietary bios)
More information on the sound card can be found in:
/proc/asound/card0/codec#*
This also hold the information of /sys/class/sound/
What is improved:
- internal microphone is chosen by default
- when jack is inserted it is chosen instead of internal speaker
Before this had to be done manually in alsa or pulseaudio.
TEST= check if internal microphone is used by default in
pavucontrol if you are using pulseaudio.
Plug in a jack with headphones and check if there
is sound output through these and not the build-in
speaker.
Change-Id: Id3b700fd84905a72cc1f69e7d8bfa6145f231756
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/15063
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
- Put each piece of data from the printall target on its own line.
- Add a blank line between each section.
Change-Id: I50068690ab6795b7ef211865f3798c87debf2a07
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15077
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This patch adds asl code to include support for Google ChromeEC.
We need this to show the battery icon and notifications like charger
connect/disconnect etc.
BUG = 53096
TEST = Plug/Unplug AC Adapter multiple times and make sure the battery
connected is charging properly.
Change-Id: Id908f145789402573ea54fc4f15cf7a0e651ebf4
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/14987
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This patch adds asl code to include support for Google ChromeEC.
We need this to show the battery icon and notifications like charger
connect/disconnect etc.
BUG = 53096
TEST = Plug/Unplug AC Adapter multiple times and make sure the battery
connected is charging properly.
Change-Id: I06f48eda894418514c8ed0136500fff0efd12a35
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15069
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Update the DDR config and DRAM driver to allow running at up to
928MHz. Kevin config/clock rate are not being changed, but Gru now
runs at 928 MHz.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=booted Kevin and Gru to Linux prompt. Ran stressapptest for 10 min on Gru,
Change-Id: I66c1a171d5c7d05b2878c7bc5eaa0d436c7a1be2
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 8baf0d82816a7ea1c4428e15caeefa2795d001f9
Original-Change-Id: I5e1d6d1025f10203da8f11afc3bbdf95f133c586
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/343984
Original-Reviewed-by: Stephen Barber <smbarber@chromium.org>
Reviewed-on: https://review.coreboot.org/15027
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Correct the spelling of *firmware* in a comment.
Change-Id: I44bcd95f754ff839d582dc2150e1883a6315da9e
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/15078
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Just the memory size, there is no strap to identify PCB revision.
Change-Id: I65b2f5b0ac6930bead60ea0a551f13a6bcab24c7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14997
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
fsp_notify(END_OF_FIRMWARE) should be sent to FSP to enable putting CSE
in low power state
Change-Id: I76b8e85ccf077032616ba8e4a333d9264dc65ed2
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/15054
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Because the resource for the ACPI BAR is fixed, pci_dev_set_resources
does not store it to the device. This means we need to do part of the
dance to get the ACPI IO region to work after coreboot.
Of course, this BAR can be destroyed later by the OS probing it, but
at least we try to get it working out of coreboot.
Change-Id: Ibff18d30936f94d4f149a89313254531365f43e6
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/15048
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Previously, 0x0 was the value being used for an unpopulated dimm
on spd[62], however some DDR2 dimms have 0x0 as a valid value.
Now use 0xff which is an unused value even on DDR2/DDR3.
Change-Id: I55a91a6c3fe3733a7bb2abc45ca352c955c07c99
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/15058
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
The way dispatcher table is set up prevents linker from
optimizing unused code away, we currently have raminit in ramstage.
Optimize this manually by configuring AGESA_ENTRY booleans for
romstage and ramstage separately. This will remove references in
FuncParamsInfo and DispatchTable -arrays.
All boards now include multi-core dispatcher, it has minimal footprint:
AGESA_ENTRY_LATE_RUN_AP_TASK
ACPI S3 support depends on HAVE_ACPI_RESUME being enabled:
AGESA_ENTRY_INIT_RESUME
AGESA_ENTRY_INIT_LATE_RESTORE
AGESA_ENTRY_INIT_S3SAVE
Disabled for all boards as it was not used:
AGESA_ENTRY_INIT_GENERAL_SERVICES
Change-Id: I7ec36a5819a8e526cbeb87b04dce4227a1689285
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14417
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Lee Leahy