Commit Graph

47069 Commits

Author SHA1 Message Date
Arthur Heymans 879c0d7edf Makefile.inc: Add fmap_config.h as a dependency to cbfs-struct generation
There is no easy way to add dependencies to cbfs-structs objects and
fmap_config.h is a generated file. Follow-up commits depend on it being
available so add it in the cbfs-struct makefile function.

Change-Id: I7067ff144d38c1ff058825819419b2a2e7801e17
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-20 10:08:33 +00:00
Angel Pons 05e846dda2 mb/bap/ode_e20XX: Drop `_PRS` from static devices
The `_PRS` ACPI object is not needed for static (non-configurable)
devices. For devices where `_CRS` always provides the same set of
resource settings, drop the `_PRS` object. Note that every dropped
`_PRS` object only provides one set of resource settings, which is
identical to the resource settings provided by the `_CRS` object.

Also, drop `IGNORE_IASL_MISSING_DEPENDENCY` as it's no longer needed.

Change-Id: If56267e8a68897236d5ff73322317cbef7ab2243
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-20 10:06:02 +00:00
Angel Pons c925609c1e mb/ibase/mb899: Drop `_PRS` and `_DIS` from static devices
The `_PRS` ACPI object is not needed for static (non-configurable)
devices. For devices where `_CRS` always provides the same set of
resource settings, drop the `_PRS` object. Note that every dropped
`_PRS` object only provides one set of resource settings, which is
identical to the resource settings provided by the `_CRS` object.
The no-op `_DIS` methods can also be removed for the same reason.

Also, drop `IGNORE_IASL_MISSING_DEPENDENCY` as it's no longer needed.

Change-Id: I7e702e9318fbf68dbd883a145111e6beb6815b8b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-20 10:05:43 +00:00
Angel Pons 6decc1dce4 mb/protectli/vault_bsw: Drop `_PRS` from static devices
The `_PRS` ACPI object is not needed for static (non-configurable)
devices. For devices where `_CRS` always provides the same set of
resource settings, drop the `_PRS` object. Note that every dropped
`_PRS` object only provides one set of resource settings, which is
identical to the resource settings provided by the `_CRS` object.

Also, drop `IGNORE_IASL_MISSING_DEPENDENCY` as it's no longer needed.

Change-Id: Ic37608ac9622b37cae6d81045740a033e9aa9d4f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-20 10:05:19 +00:00
Angel Pons a1f68319c5 ChromeEC boards: Drop `IGNORE_IASL_MISSING_DEPENDENCY`
This should no longer be needed because the ASL has been fixed.

Change-Id: I4d1500217bef54fa3d2be397e5e2a155da3f965d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-20 10:04:58 +00:00
Angel Pons fbf58d9f89 ec/google/chromeec: Drop `_PRS` from static devices
The `_PRS` ACPI object is not needed for static (non-configurable)
devices. For devices where `_CRS` always provides the same set of
resource settings, drop the `_PRS` object. Note that every dropped
`_PRS` object only provides one set of resource settings, which is
identical to the resource settings provided by the `_CRS` object.

Change-Id: Ief40e790fdee336fd6c786e18cd01c41fa658c2c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-04-20 10:03:35 +00:00
Angel Pons 5412b41ce6 superio/smsc/mec1308: Drop `_PRS` from static devices
The `_PRS` ACPI object is not needed for static (non-configurable)
devices. For devices where `_CRS` always provides the same set of
resource settings, drop the `_PRS` object. Note that every dropped
`_PRS` object only provides one set of resource settings, which is
identical to the resource settings provided by the `_CRS` object.

In addition, drop `IGNORE_IASL_MISSING_DEPENDENCY` from the two
mainboards using the MEC1308 code, `samsung/{lumpy, stumpy}`.

Change-Id: I5d5cdc28c2cfaa5dfcffd656060b931208977386
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-20 10:02:17 +00:00
Angel Pons 865dd085f6 superio/smsc/sch5545: Drop `_PRS` from static devices
The `_PRS` ACPI object is not needed for static (non-configurable)
devices. For devices where `_CRS` always provides the same set of
resource settings, drop the `_PRS` object. Note that every dropped
`_PRS` object only provides one set of resource settings, which is
identical to the resource settings provided by the `_CRS` object.

In addition, drop `IGNORE_IASL_MISSING_DEPENDENCY` from the only
mainboard using the SCH5545 code, `dell/snb_ivb_workstations`.

Change-Id: Ic462bd3dfa287744d4f733561de81c09c1c397e6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-20 10:01:56 +00:00
Angel Pons cf19f70a2d mb/kontron/986lcd-m: Drop `_PRS` and `_DIS` from static devices
The `_PRS` ACPI object is not needed for static (non-configurable)
devices. For devices where `_CRS` always provides the same set of
resource settings, drop the `_PRS` object. Note that every dropped
`_PRS` object only provides one set of resource settings, which is
identical to the resource settings provided by the `_CRS` object.
The no-op `_DIS` methods can also be removed for the same reason.

Also, drop `IGNORE_IASL_MISSING_DEPENDENCY` as it's no longer needed.

Change-Id: I71275f2581b999d606f36773578b36dbdccf6452
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-04-20 10:01:21 +00:00
Varshit B Pandya 282b3b6873 drivers/intel/dptf: Add support for PROP method
Add PROP method under \_SB.DPTF.TPWR scope which will return static
worst case rest of platform power in miliWatts.

This value is static, which has to configured from devicetree of
overridetree for each platform

BUG=b:205928013
TEST=Build, boot brya0 and dump SSDT to check PROP method

Scope (\_SB)
{
    Device (DPTF)
    {
        Device (TPWR)
        {
            Method (PROP, 0, Serialized)
            {
                Return (XXXX)
            }
        }
    }
}

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I1415d2a9eb55cfadc3a7b41b53ecbec657002759
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-20 09:58:58 +00:00
Julius Werner 5784ab34d4 docs/coding_style: Clarify use of GCC extensions
This patch adds a section to the coding style that explicitly clarifies
the use of GCC extensions in coreboot (which has been long-standing
practice anyway), and expressly allows their use.

See the mailing list discussion for more details:
https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/3C2QWAZ5RJ6ME5KXMEOGB5GW62UTXCLS/

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I0d0eb90d6729fefeb131cdd573ad51f1884afe11
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2022-04-20 09:41:18 +00:00
Wonkyu Kim 9cb5dcb40c soc/intel: clean up dmi driver code
1. Remove dmi.h as it's migrated as gpmr.header
2. Remove unused gpmr definitions
3. For old platforms, define DMI defintions in c code
   for less code changes.

TEST=Build
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ib340ff1ab7fd88b1e7b3860ffec055a75e562de7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-20 09:39:27 +00:00
Subrata Banik 211be9c031 soc/intel/cmn/{block, pch}: Migrate GPMR driver
This patch migrates GPMR driver over DMI to accommodate future SOCs
with different interface (other than PCR/DMI).

TEST=Able to build and boot google/redrix.

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I00ac667e8d3f2ccefd8d51a8150a989fc8e5c7e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-20 09:38:46 +00:00
Tim Wawrzynczak d85e5eb287 mb/google/brya/var/redrix: Add alias back to RP6 WWAN device
This alias name is required for the mainboard.c code to generate the
appropriate power-off seqeuence for use during orderly S5 shutdown
from the OS. It had been accidentally removed, but is required, so
this patch adds it.

BUG=b:227788351
TEST=compile

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I8936a01bd3a6b908033a8c58bd4e84b30d199e98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-20 09:38:20 +00:00
Usha P 63eec22a62 mb/intel/adlrvp_n: Disable SATA controller
Disable SATA config from devicetree for ADL-N RVP, since we are not
planning to use it in chrome config.

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: Ic9dce3a0b06e1a0d0d9fa495aa406eb12557d842
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-04-20 09:38:03 +00:00
Arthur Heymans 0f89a11313 nb/intel/snb: Reduce scope of functions
Change-Id: Idefbe15c5f7c7169d9b60079b90cd02affb261ca
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-20 09:37:34 +00:00
Wisley Chen 35a124ec77 mb/google/brya/var/anahera{4es}: Enable power saving for Smart Card
Configure the power saving pin for Smart Card.

BUG=b:229356121
TEST=emerge-brya coreboot chromeos-bootimage

Change-Id: Ia17970f717c6ba806d9603031c486bad86e42b37
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-20 09:37:15 +00:00
Kenneth Chan d80d88c0fe mb/google/guybrush/var/dewatt: Override SPI fast speed
After assessing the signal integrity, 100 MHz SPI fast speed can be
enabled for SPI ROM.

BUG=b:213403891
TEST=Build and boot to OS in Dewatt board version 2.

Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: I7301d873e36bec4ee46c9d18293f924500ea9aba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63685
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-20 09:37:01 +00:00
Eric Lai 3067701108 lib: Check for non-existent DIMMs in check_if_dimm_changed
Treat dimm addr_map 0 non-existent. addr_map default is 0, we don't set
it if Hw is not present. Also change the test case default to avoid 0.
SODIMM SMbus address 0x50 to 0x53 is commonly used.

BUG=b:213964936
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
The MRC training does not be performed again after rebooting.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I2ada0109eb0805174cb85d4ce373e2a3ab7dbcac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-20 06:57:21 +00:00
Karthikeyan Ramasubramanian d083317fae drivers/usb/pci_xhci: Add Sabrina xhci pci device id
BUG=None
TEST=Build and boot to OS in Skyrim. Ensure that the XHCI controllers
are enumerated successfully and ACPI device objects are added in SSDT.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I7ad4555212ed38ea0f9029275345e4945855a8c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-19 15:58:40 +00:00
Sridhar Siricilla 2c4b426557 mb/google/brya: Disable PCH USB2 phy power gating for felwinter
The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for felwinter board. Please refer Intel doc#723158 for
more information.

BUG=b:221461379, b:226020977
TEST=Verify the build for felwinter board

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I25033ea218fa3154eb99af6be43c4198f4db3bcb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-19 13:09:44 +00:00
Raihow Shi 5215f2ffcb mb/google/brask/variants/moli: update type-c setting in overridetree
Add conn1 for pch_espi and add type-c port2 for pmc_mux.

BUG=b:220814038
TEST=emerge-brask coreboot.

Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Idfd7b761496a110f34838abb0fd408b37d390ba2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-19 13:08:53 +00:00
Raihow Shi 40c47b24a4 mb/google/brask/variants/moli: add delay time to rtd3-cold
This CL adds the delay time 50 ms and 20 ms into the RTD3 sequence,
the reason is that the rise and fall times of each signal
may differ by board, and so those board-specific delays
must be taken into account when power sequencing.

We checked power on sequence requires enable pin prior to reset pin,
so added delay to meet the sequence.
Based on BH799BB_Preliminary_DS_R079_20201124.pdf in chapter 7.2.

BUG=b:228907551
TEST=emerge-brask coreboot.

Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Idecb1c89655c9b8b720c3c65efc77e06e6a8b300
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-19 13:08:32 +00:00
Raihow Shi b83dd7ea63 mb/google/brask/variants/moli: remove i2c1 in overridetree
Remove i2c1 because brask devicetree is already has it.

BUG=b:220814038
TEST=emerge-brask coreboot.

Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Ic782e1c6434ac57bdf65b3d9f4219bdf32d25b9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-19 13:08:16 +00:00
Ian Feng c6d6c88fcf mb/google/skyrim: Configure Pen Detect device
Enable pen garage. Pen detect is active low.

BUG=b:229168203
TEST:Build and boot to OS in skyrim. Evtest work as expected
Input driver version is 1.0.1
Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100
Input device name: "PRP0001:00"
    Supported events:
  Event type 0 (EV_SYN)
  Event type 5 (EV_SW)
    Event code 15 (SW_PEN_INSERTED) state 1
Properties:
Testing ... (interrupt to exit)
Event: time 1649922170.578779, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0
Event: time 1649922170.578779, -------------- SYN_REPORT ------------
Event: time 1649922172.070740, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I3bb07af6aebdc355a73148d8be79b1014147f61d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-04-19 13:07:50 +00:00
Ian Feng e204690227 mb/google/skyrim: Add Goodix touchscreen
Add Goodix touchscreen according to the Programming Guide Rev.0.7

BUG=b:228907558
TEST=local build and tested with Goodix touch screen

Change-Id: I35dd3ca76e9e0f17508bef46c90b53b4be5d0033
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63573
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-19 13:07:28 +00:00
Dtrain Hsu f17f6d9334 mb/google/brask: fix boot beep
Fix the issue that can't hear the boot beep at dev screen. GPP_B14 is
used for PWM_PP3300_BUZZER and it should set to GPO. Modify GPP_B14 from
PAD_CFG_NF_LOCK to PAD_CFG_GPO_LOCK.

BUG=b:229345416
BRANCH=firmware-brya-14505.B
TEST=emerge-brask coreboot and verify if the buzzer beeps.

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I601735ab20974cd992ca5dd6dbaca1517a395aa2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63645
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-19 13:06:14 +00:00
Raihow Shi 4b642fd512 mb/google/brask/variants/moli: Pick VBT based on FW_CONFIG
Pick specific VBTs for HDMI, DP, and ABSENT according to FW_CONFIG.

BUG=b:220241277
TEST=emerge-brask coreboot.

Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Icc8fbef1467605505459fce264697f670591c81e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63604
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-19 13:05:50 +00:00
Wisley Chen d9314c7efe mb/google/brya/var/anahera{4es}: select DRIVERS_GENESYSLOGIC_GL9750
select DRIVERS_GENESYSLOGIC_GL9750 to disable ASPM L0s.

BUG=b:229213455
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: Ie89fa6c66974284063cd25ae8097db94a93326ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-19 13:05:24 +00:00
Arthur Heymans 1842aa2746 Kconfig: Make HAVE_EM100_SUPPORT invisible
This is a property of a platform and should not be exposed to the
user.

Change-Id: I34f9097d40b2bf732cecf30bf13ba5a413dd53a5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-19 13:04:25 +00:00
Arthur Heymans 67f29e818f cpu/x86/Kconfig*: Guard with ARCH_X86
None of these options make sense on different ARCH.

Change-Id: Ie90ad24ff9013e38c42f10285cc3b546a3cc0571
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63673
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-19 13:03:16 +00:00
Selma Bensaid 4bc425c521 payloads/depthcharge: enable LP_CHROMEOS in depthcharge
Fix standslone build failure after depthcharge patch
https://crrev.com/c/3461454 merge.

BUG=chrome-os-partner:226438207
TEST=Compiled brya and redrix in standalone mode.

Signed-off-by: Selma Bensaid <selma.bensaid@intel.com>
Change-Id: Ib2bb2ce42a314e05ef22ea7b8abc067d6361d511
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2022-04-19 13:03:00 +00:00
Bora Guvendik 40e461a00c soc/intel/alderlake: Enable Pre Reset CPU Telemetry
Insert CSE timestamps to coreboot timestamp table.

BUG=b:182575295
TEST=Boot to OS on Brya Redrix board.

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ifbea7155a294e0039a5bd1d16588775e90a29ae3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-19 13:02:33 +00:00
Eric Lai 51e00e60e0 mb/google/nissa: Add gpio lock pins
Followed the Brya series to lock the gpio pins in baseboard. Variant
should honor locked gpios from baseboard, but not the last. Variant can
add more gpios to lock if needed.

BUG=b:216671701
TEST='emerge-nissa coreboot chromeos-bootimage', flash and verify that
nivviks boots successfully to kernel.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ib34ca287596a6958407a944d0caf53f4bcc60d9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-19 13:02:13 +00:00
Raihow Shi 4d4a24529a mb/google/brya: Add Kconfig for TPM I2C bus
Add TPM I2C for crota to avoid TPM I2C fail.

BUG=b:229200525
TEST=emerge-brask coreboot.

Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I8054e623fb0c3c549c3373982ce9d4fbd57e0fd7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-19 13:01:57 +00:00
Terry Chen 212f86bc9b mb/google/brya/var/crota: Kconfig: Select TPM I2C bus driver
Add TPM I2C for crota to avoid TPM I2C fail.

BUG=b:226315394
TEST=USE="project_crota emerge-brya coreboot" and verify it builds
without error.

Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I7eb3ce6c2faf857c8f5d789af395e315caea4102
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-19 13:01:41 +00:00
Jakub Czapiga 9ebc6c1e26 tests: Split Makefile to allow for making host-side test tools
This patch is based on similar changes [1] done in Depthcharge projects,
which aimed to provide unified way to build host-side programs for
testing internal code. New test tools might benefit from it by having
same base code as unit-tests.

[1] https://crrev.com/c/3412108

TEST=make unit-tests
TEST=COV=1 make unit-tests coverage-report

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Iac4517ab6146fa3f2d2b7a20df54601ab2d04c3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-04-19 13:00:56 +00:00
Jakub Czapiga c91b55a201 tests: update CMocka to stable-1.1
CMocka stable-1.1 has some convenience bugfixes like vprint buffer
increase or leftover values log fix (funtion names display correctly
now.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I20ebd15324a21c17cccd2976ae9c3f86b040426d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-04-19 13:00:36 +00:00
Chris.Wang 38f7ba3db4 mb/google/guybrush/var/dewatt: Update APU STT setting
update STT setting for dewatt.

BUG=b:228040295
BRANCH=guybrush
TEST=build, verify the parameter has been applied to
     the system by checking the AGT tool.

Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Id319d42747dd0d5f6a9ca727635d85e6b9bd65af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-19 12:15:04 +00:00
Subrata Banik d643165c64 soc/intel/cmn/fast_spi: Add API to set SPI controller VCL
This patch creates a helper function to set SPI controller VCL bit as
recommended by Intel Flash Security Specification.

BUG=b:211954778
TEST=Able to build google/brya and verified that SPI flash controller
MMIO register 0xC4 bit 30 is set.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie9a12db1bab81779fd8e7db90221d08da3c65011
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-04-19 05:46:38 +00:00
Subrata Banik d5e7c63a85 soc/intel/cmn/fast_spi: Add API to clear outstanding SPI status
This patch creates a helper function to clear HSFSTS_CTL (offset 0x04)
register Bits 0 to 4.

As per Intel PCH BIOS spec section 3.6 Flash Security Recommendation,
it's important to clear all SPI outstanding status before setting SPI
lock bits.

BUG=b:211954778
TEST=Able to build google/brya with this patch and clear SPI controller
HSFSTS_CTL register Bits 0 to 4.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I62adba0d0cef1d4c53b24800f90b4fe76a9d78b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-04-19 05:46:11 +00:00
Subrata Banik a26bb7878b soc/intel/cmn/fast_spi: Add API to check if SPI Cycle In Progress
This patch creates a helper function to check if any SPI transaction
is pending.

As per Intel PCH BIOS spec section 3.6 Flash Security Recommendation,
it's important to ensure there is no pending SPI transaction before
setting SPI lock bits.

BUG=b:211954778
TEST=Able to build google/brya with this patch and no error msg seen
due to `SPI transaction is pending`.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibd3f67ae60bfcb3610cd0950b057da97ff74b5b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-04-19 05:45:43 +00:00
Subrata Banik 6b888adcff soc/intel/cmn/lpc: Fix typo from FAST_SPIBAR to LPC
BUG=b:211954778
TEST=None

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib8cc4b8d13b61e3935f2050d25ce0278162c91c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-19 05:45:07 +00:00
Subrata Banik e0b7423d67 soc/intel/cmn/fast_spi: Use tab instead space
This patch converts whitespace into tabs to maintain the uniformity
across the fast_spi_def.h file.

BUG=b:211954778
TEST=Able to build google/brya.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I56bcd263c6a5c0036e459926a25538e3448fbce6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-04-19 05:44:58 +00:00
Rob Barnes 0e4ca759f4 mb/google/guybrush: Remove EC_ENABLE_LID_SWITCH
Remove EC_ENABLE_LID_SWITCH since this causes a duplicate SW_LID
entries. The other SW_LID entry is generated by MKBP.

BUG=b:228907256
BRANCH=guybrush
TEST=Lid open close triggers events on Nipperkin

Change-Id: I5c1cf7aeac8405bce7bfc77110eceaf3e5383fe7
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-04-18 23:03:59 +00:00
Kevin Chiu 4d4c0a5f27 mb/google/guybrush/var/nipperkin: turn off WLAN ASPM L1ss
BUG=b:227296841
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage
     pass PLT criteria: S0 > 600ms, s0i3 > 14 days

Change-Id: I9c61e1d0f3db8b9885040255d6de266616768b68
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-04-18 23:03:44 +00:00
Damien Zammit e0ff2735f3 mb/hp/z220_series: Add Z220 CMT Workstation variant
This is based on previous work done by a good friend of mine.

The notable differences between this board and the SFF variant is that:
 - CMT has 4 more PCI/PCIe ports than SFF.
 - CMT has 2 more SATA ports than SFF.

TESTED on Z220 CMT Workstation (boots to payload)

Change-Id: I2b298921e6f509440ec7b049e086c0878f708bd3
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-18 01:01:02 +00:00
Felix Singer 598ff42f12 mb/lenovo/t440p/Kconfig: Reorder selects alphabetically
Built lenovo/t440p with BUILD_TIMELESS=1 and coreboot.rom remains the
same.

Change-Id: I7bac7ad5236346a3c2a8928ecdfadde6564ff232
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-16 17:58:13 +00:00
Felix Singer d22fc77704 mb/lenovo/t440p/dsdt.asl: Remove redundant comment
Change-Id: Ie772701192a3589b51642df446f0b2527fb7d630
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-04-16 17:58:05 +00:00
Tim Van Patten e229c6005f mb/google/guybrush: Set BT USB to use GPIO for status
Set the BT USB device to use GPIO for the power status. This causes an
ACPI `_STA()` function to be generated that returns the power status of
the BT USB device, rather than always returning `0x1`. This `_STA()`
function can be used during boot to skip enabling the device (and
performing the associated sleep) if the device is already powered on.

BRANCH=None
BUG=b:225022810
TEST=Dump SSDT table for guybrush

Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: I72f6b28671efddfbef53f328d904a05f73f39efa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-14 22:31:11 +00:00