Commit Graph

25288 Commits

Author SHA1 Message Date
Rizwan Qureshi c1072f2fc7 cbfstool: Update FIT entries in the second bootblock
Once a second bootblock has been added using topswap (-j)
option, Update the entries in second FIT using -j option with
update-fit command.

Additionally add a -q option which allows to insert the address of
a FMAP region (which should hold a microcode) as the first entry in
the second FIT.

BUG=None
BRANCH=None
TEST= Create ROM images with -j options and update FIT using -q option.
example:
./build/util/cbfstool/cbfstool coreboot.tmp create \
	-M build/fmap.fmap -r COREBOOT,FW_MAIN_A,FW_MAIN_B,RW_LEGACY
build/util/cbfstool/cbfstool coreboot.tmp add \
	-f build/cbfs/fallback/bootblock.bin -n bootblock -t \
	bootblock -b -49152 -j 0x10000
build/util/cbfstool/cbfstool coreboot.tmp add-master-header -j 0x10000
build/util/cbfstool/cbfstool coreboot.tmp add -f build/cpu_microcode_blob.bin \
	-n cpu_microcode_blob.bin -t microcode -r COREBOOT -a 16
build/util/cbfstool/cbfstool coreboot.tmp. update-fit \
	-n cpu_microcode_blob.bin -x 4 -j 0x10000 -q FW_MAIN_A

Also try the failure scenarion by providing invalid topswap size.

Change-Id: I9a417031c279038903cdf1761a791f2da0fe8644
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/26836
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-26 05:59:52 +00:00
Rizwan Qureshi 1dc188fad0 cbfstool: add an option for creating a topswap bootblock
Add an option '-j' which takes the size of topswap boundary.
This option serves both as a bool and a size for creating
a second bootblock to be used with topswap feature in Intel CPUs.
'-j' is also used in conjunction with add-master-header to
update the location of cbfs master header in the second bootblock.

BUG=None
BRANHC=None
TEST=add bootblock entry to the image with -j option specifying different
topswap sizes and also use the -j option for add-master-header.

Change-Id: I3e455dc8b7f54e55f2229491695cf4218d9cfef8
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/22537
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-26 05:51:33 +00:00
Simon Glass 4f16049f17 mb/google/kahlee/variants/grunt: Select low-power mode for BayHub720
Put the PCIe clock pins in power-saving mode for the BayHub eMMC bridge to
save power. This requires use of an additional register (Misc control
register 2) and another bit in the existing 'protect' register. The naming
of bit 0 of that register is incorrect, based on the latest datasheet
(14 June 2018) so fix that too.

BUG=b:73726008
BRANCH=none
TEST=boot without this patch:
iotools mem_read32 0xfed80e00
0x0046ffff

With this patch:
$ iotools mem_read32 0xfed80e00
0x00463fff

Also see that the PCIe clock stops when eMMC is idle and can be started by
starting disk activity.

Change-Id: I5ad1467b2e2e151215d2dfd2ce48cd4a451fe480
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/26515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-25 20:50:14 +00:00
Furquan Shaikh 57ccb9c5e8 util/abuild: Enable abuild to compile a single variant
There are many boards in coreboot which support multiple
variants. When abuild is used to compile a single target, it builds
all its variants. If a target has 5 variants, then abuild takes nearly
10x the time to compile all variants of the target. This change adds
an option -b/--board-variant to enable abuild to compile only a single
variant of the target.

TEST=Verified:
1. abuild builds all variants of the target if -b option is not
provided.
2. abuild builds a single variant if -b option is provided.
3. abuild prints appropriate error message if invalid variant name is
provided.

Change-Id: I3781568c6409c5ec2610a8386a21d86037428e7f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27215
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-25 17:41:26 +00:00
Furquan Shaikh 0be087deee mb/google/octopus: Use the newly added override devicetree feature
Now that sconfig is able to support variant-specific override trees,
this change updates octopus boards to use this feature. Following
devices are moved from baseboard devicetree to variant specific
devicetree:
1. Touchscreen
2. Trackpad
3. Digitizer
4. Audio codec

BUG=b:80081934
TEST=Verified that the right devices show up in static.c for each
variant.

Change-Id: I8df0cdf4dbcd7613aa4ef4042c272eca2915da9e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27219
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-25 17:41:00 +00:00
Furquan Shaikh 50ddc0bb28 util/sconfig: Get rid of ops from struct device
"ops" field was used in device structure only to add
default_dev_ops_root for root device. It was always set to NULL for
all other devices. This change gets rid of ops field from struct
device and instead hardcodes default_dev_ops_root in pass1 for root
device.

BUG=b:80081934
TEST=Verified that static.c generated with and without this change is
exactly the same.

Change-Id: I0848788610c2ed27274daf4920de3068a9784d4c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27209
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-25 17:40:46 +00:00
Furquan Shaikh 27efc501d1 util/sconfig: Add support for overriding base tree properties/node
This change adds support to allow variants to override the devices and
properties in base device tree by providing an override device
tree. It works as follows:
1. Both base and override device trees are parsed from provided input
files.
2. Walk through the trees in lockstep fashion using depth-first
traversal checking if a node in override tree has a matching node in
base tree.
 - If matching node is found, then update the properties of base node
 using the override node. Continue walking the children of the nodes.
 - If matching node is not found, then copy the entire override
 subtree of the node under the current base parent. In addition to
 that, chip instance pointers of the nodes in override tree need to be
 updated if they were pointing to the override parents chip instance.

Since chip always expects a device to be present, it leads to a
side-effect that overriding chip registers requires that a device is
always provided for the chip in the override tree as well.

BUG=b:80081934

Change-Id: I6604e4f8abe3fc48240e942fea32da96031e1e46
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27206
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-25 17:40:36 +00:00
Furquan Shaikh f241998352 Kconfig: Add new config for OVERRIDE_DEVICETREE
This change adds a new config option OVERRIDE_DEVICETREE that allows
variants to provide an override devicetree file to override the
registers and/or add new devices on top of the ones provided by
baseboard devicetree using CONFIG_DEVICETREE.

BUG=b:80081934

Change-Id: Ica046b7e0d70d0f1e8d94da714d1e62032277916
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-25 17:40:28 +00:00
Crystal Lin 3ff98ca858 mb/google/poppy/variants/nami: Prevent leakage with touchscreen on Pantheon
We found GPP_C3 keeps high when system in S0ix mode. It caused 1.8V
leakage. To fix this problem, add GPP_C3 into config for Pantheon
Synaptics touchscreen.

BUG=b:78436458
BRANCH=None
TEST=Let DUT in S0ix mode and check GPP_C3 is normal.

Change-Id: Idb2dab93178af1dae54265e49522b473b69a35af
Signed-off-by: Crystal Lin <crystal_lin@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27177
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-25 16:36:14 +00:00
Furquan Shaikh 39ac797eda util/sconfig: Enable parsing of override device tree
This change allows sconfig utility to accept an extra optional
parameter to specify override device tree that can be used to override
the properties or add new devices in addition to that provided by base
device tree. This is helpful for variants that share most of the
devicetree but have to override certain registers or add some devices
which might not be applicable to base devicetree.

In order to support the override devicetree, following changes are
made in this CL:
1. override_root_dev and override_root_bus are provided.
2. main() function is updated to accept an optional argument.
3. If override device file is provided, then parse_devicetree is
called for override_devtree as well.

This change in itself does not provide the override feature. It is
only a small step towards the final goal. The override devicetree
parsed by sconfig is currently unused.

BUG=b:80081934

Change-Id: I477e038c8922ae1a9ed5d8bf22a5f927a19a69c7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-25 08:55:39 +00:00
Sumeet Pawnikar f0c50b0e4b mb/google/octopus/variants/baseboard: Update DPTF parameters
This patch updates DPTF parameters for Octopus baseboard.

BUG=b:79779737
BRANCH=None
TEST=Build coreboot for Octopus board.

Change-Id: I1456b7b9ee9e02491c66b0709c710e1a7ec08cc5
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/27027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-25 08:53:38 +00:00
Arthur Heymans 510758826d nb/lenovo/t400: Enable libgfxinit
Change-Id: I243c22c83a5575c2e1500cc869c41691c4fba415
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-06-25 08:22:01 +00:00
Shelley Chen e1d5facea2 mb/google/nami: Enable xDCI
This change enables xDCI controller on nami.

BUG=b:110443736
BRANCH=None
TEST=None

Change-Id: Ieb63e0d65ac1a142c151a3f93afe306b80a5d99a
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/27181
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-25 08:21:12 +00:00
Naresh G Solanki fb7eaa5beb util/lint/checkpatch_json: Fix checkpatch output keyword match string
From checkpatch output, look for keywords starting with 'ERROR:' &
'WARNING:' .

Also check for keywork ': FILE:'  instead of the same without the
colon (:).


BUG=None
BRANCH=None
TEST=Check if patch https://review.coreboot.org/#/c/coreboot/+/22537/21
is processed & json output is generated properly.

Change-Id: Ib690ab34a1ffabc4f83642634fd34beea16a64dc
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/27170
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-25 08:19:37 +00:00
Nicola Corna 04d2601426 sb/intel/common/firmware: Enable me_cleaner for Nehalem
Recent patches in coreboot have fixed the freeze issues related to the
use of me_cleaner on Nehalem.

However, at least on the Lenovo X201, with me_cleaner some PCIe devices
(like the SATA and USB controllers) disappear. In particular, setting
the AltMeDisable bit ("-S" or "-s" flag) makes them disappear
completely, while unsetting it makes them disappear only during cold
boots.

This kind of behaviour was already observed by Youness Alaoui on the
Purism Librem laptops ([1]), and it seems related to some required
board-specific PCIe configuration in the ME's MFS partition.

For this reason, on the Lenovo X201, "-w EFFS" has been added to the
me_cleaner arguments, which whitelists the MFS-equivalent partition for
ME generation 2. This fixes all the issues, and the PCIe devices work as
expected.

[1] https://puri.sm/posts/deep-dive-into-intel-me-disablement/

Change-Id: Ie77a80d2cb4945cf1c984bdb0fb1cc2f18e82ebc
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/27178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-25 08:19:16 +00:00
Sathyanarayana Nujella 59790dded6 intel/skylake: nhlt: Add capture config for echo ref stream for Max98373 Codec
During Speaker playback, quad Channel I/V feedback data is
captured from SSP0 Rx. Out of these 4-channels, Stereo V-Sense data
needs to be given as echo ref stream.
So, adding stereo capture config to max98373_capture_formats.

BUG=b:110074225
TEST='Audio playback and Capture Stereo echo ref data'

Change-Id: I6fe619ece94d5011caffe37ef10b48f956938db9
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/27182
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-25 08:17:03 +00:00
Furquan Shaikh 1bf411c743 drivers/i2c/alps: Get rid of i2c/alps driver
i2c/alps driver implementation is an exact copy of the i2c/hid driver
with only the addition of ALPS0001_HID. This can be supported by the
i2c/hid driver using the hid field in devicetree which is what glkrvp
mainboard does. So, this change removes the i2c/alps driver which is
anyways unused.

Change-Id: I60761c384f3d800532b2b346272da7be28b77acd
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-24 06:49:08 +00:00
Furquan Shaikh a7e925027f drivers/i2c/sx9310: Check for config not being NULL before using it
This change fixes the issue reported by Coverity CID 1393576 to ensure
that config is checked for NULL before it is actually used.

Change-Id: I5f0cd2bf2437fc640f4cf8d8203a971daf1f8d17
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Enrico Granata <egranata@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-24 06:49:00 +00:00
Angel Pons 65ddbb720b mb/asus/p8h61-m_pro: Add new mainboard
Tested with GRUB 2.02 as a payload, booting Arch Linux as
well as Debian. This code is based on the output of autoport
as well as other mainboards supported in coreboot already.

Working:
 - Serial port I/O
 - S3 suspend/resume. Untested with SeaBIOS since it failed
   to resume on a similar board. It is likely to be due to
   low memory corruption, but I have not worked on it.
 - USB ports and headers
 - USB3 ports attached to the ASM1042 controller. SeaBIOS can
   boot from them, and it is likely GRUB can detect devices on
   those ports as well. The chip has a small SPI flash nearby,
   which seems to hold an Option ROM.
 - Gigabit Ethernet
 - Integrated graphics (libgfxinit)
 - VGA BIOS for integrated graphics init
 - PCIe x16 graphics
 - PCIe x1
 - SATA controller
 - Hardware Monitor
 - Fan Control (fancontrol on linux works well)
 - Native raminit
 - flashrom, using the internal programmer. Tested with coreboot,
   as well as with the vendor firmware.
 - NVRAM settings. Only debug_level has been tested.

Untested:
 - DVI port. It can detect a "fake" display, that is, an
   EEPROM connected to the DVI port. Thus, gma-mainboard.ads
   has been setup accordingly.
 - PS/2 port.
 - Audio: Only rear output (green) has been tested.
 - EHCI debug.
 - Parallel port header.
 - Non-Linux OSes
 - ACPI thermal zone and fan control (probably not working)

Not working:
 - Booting from devices attached to the ASM1061 controller.
   Devices on ports work fine once Linux has loaded.
 - Any SATA devices with Tianocore (payload issue)

Change-Id: I7e89ebe43a2e1ff0308f4876e98bbf2f5a0d85f2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/26419
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-23 22:26:22 +00:00
Elyes HAOUAS fe2510764d nb/intel/i945: Remove dead code
Regarding "Intel 945G/945GZ/945GC/945P/945PL Express Chipset Family",
Document Number: 307502-005, page 91, if Channel B is empty,
all of the C1DRBs are programmed with the same value as C0DRB3.
Mobile 945 express chipset datasheet doesn't mention this specific case.

Change-Id: Ic26103aac7f920e5696b445e125d33405df4f43b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27204
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-23 22:25:51 +00:00
Caveh Jalali 1d23eb6d37 mb/google/poppy/variants/atlas: Add two new Samsung memory options
- add K4E6E304EC-EGCF and K4EBE304EC-EGCF to memory strapping table

BUG=b:110498646
BRANCH=none
TEST=none

Change-Id: Iddacdf1e1d0e2bae0c6168c86e54f5f602cd9d19
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/27184
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-23 05:15:30 +00:00
Caveh Jalali b61c219a38 mb/google/poppy/variants/atlas: add GPIO for bluetooth enable
This configures a GPIO pin for enabling/disabling bluetooth on the
next version of the atlas board.  The default is for bluetooth to be
enabled at this point.

BUG=b:110614620,b:110613353
BRANCH=none
TEST=none

Change-Id: I4ba940e89b1dc03548b7ab44b8f84dc9a3097acb
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/27185
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-23 05:15:21 +00:00
Subrata Banik 918ff858cf soc/intel/cannonlake: Disable UART_DEBUG by default
This patch ensures serial debug is not enabled by default on Cannonlake
platform.

Change-Id: Id925c8c73971a027e45ea3c61e878f134bc9feff
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/27205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-23 04:38:52 +00:00
John Su 50a7fca1d7 mb/google/poppy/variants/nami: Fix non-working thermal sensor QT2 PSV
Modify DPTF TRT parameters to solve thermal sensor QT2 PSV problem.

BUG=b:109941652
TEST=The thermal team verify OK

Change-Id: Id9d39d8282712a0341fea10f74c0e40bb1ac9d7c
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-22 16:51:49 +00:00
Furquan Shaikh d9bbbe3ca4 mb/google/octopus: Update GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
Move GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC under each variant config and
select it for bip and fleex only.

Functional change in this CL is that EC SW sync will be enabled for
phaser.

BUG=b:110523400

Change-Id: If6f37c6b2ee71130b9ed5b10ce92fb23fa1c39fc
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-22 16:24:54 +00:00
T Michael Turney ace395b96a sdm845: increase SRAM for bootblock
Bootblock has grown beyond 32K, grow to 40K

Change-Id: Iedc52151e223ebf4ff5b35a419b5378a6f1c661b
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/26760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-06-22 13:11:39 +00:00
T Michael Turney be073dacb0 libpayload: cheza - fix config for chromium chroot build
Add CONFIG_LP_CHROMEOS to configuration file

Change-Id: I528dee96cf5052b99b8f7573010d98fd80680688
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/26711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-22 13:11:06 +00:00
Matt DeVillier 1f6e3294f8 drivers/fsp1_1: fix VBT Loading by using GMA common function
Commit 77034fa [intel/common: compress VBT] compressed vbt.bin in
CBFS, but only changed the loader in soc/intel/common, forgetting
the separate one used by FSP 1.1.

As the soc/intel/common loader has now been rolled into the one in
drivers/intel/gma, replace the VBT loader used by FSP 1.1 with the GMA one.
Also, remove 2 now-unused header files.

Test: build/boot google/chell, observe display initialized prior
to OS load, no FSP warning in cbmem console due to invalid VBT signature.

Change-Id: Iba882ee4d9e83dcd88bdf7dd2f5591f66005a3fe
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-22 09:28:44 +00:00
Enrico Granata 95278a59bd mb/google/poppy/variants/nocturne: Hook up the SX9310 proximity sensor.
Change-Id: I7358ee34df873098a86d692cc8a909b0ec5023a8
Signed-off-by: Enrico Granata <egranata@chromium.org>
Reviewed-on: https://review.coreboot.org/27172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-22 09:21:19 +00:00
Enrico Granata 76a1f49f74 drivers/i2c: Add a driver for Semtech SX9310
This adds a new driver for the SX9310 proximity detector device.

The purpose of this is to enable the device's calibration information
to be stored in firmware, and then transferred over to the kernel
via ACPI.

This device has more than 10 individual configuration parameters,
so they would not fit in the generic driver's properties table.

Change-Id: Id8c434eec9fe2da731e142442503a12e88db2236
Signed-off-by: Enrico Granata <egranata@chromium.org>
Reviewed-on: https://review.coreboot.org/27173
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-22 09:21:02 +00:00
Arthur Heymans 9700e91b10 cbfstool/fit.c: Fix for older CPUs without total_size in mcu_header
Some older CPUs have a fixed size of 2048 bytes for microcode total size.

Change-Id: Ia50c087af41b0df14b607ce3c3b4eabc602e8738
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27090
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-22 09:20:22 +00:00
Subrata Banik d5018a8f78 soc/intel/cannonlake: Remove DMA support for PTT
Alternative buffer communication support for PTT is no longer
needed for CNL onwards and coreboot does not need to reserve additional
4KiB memory for PTT support.

Change-Id: I11993cef77fd5e879eedabc1ed344f91f8257c90
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/27176
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-22 01:58:33 +00:00
Subrata Banik f699c14c03 soc/intel/common/block/cpu: Add option to skip coreboot AP init
SoC users from IOTG team is looking forward for a solution to skip
coreboot AP initialization flow and make use of FSPS-UPD to
perform AP reset.

TEST=Assign use_fsp_mp_init=1 to ensure coreboot is not bringing APs
out of reset.

Change-Id: Ibc8cd411e802fb682436a933073922b2693ba994
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-22 01:58:17 +00:00
qeed b775a62bb9 inteltool: Add PCI IDs for the C220 PCH series
Adds missing PCI IDs to allow tool to dump the
C220 PCH (8 series) southbridge.

Intel Document 328904 is the datasheet for this PCH.

Change-Id: I07a8f2e9cb0ee8677c8fe2c51881147ed81c1a35
Signed-off-by: Quan Tran <qeed.quan@gmail.com>
Reviewed-on: https://review.coreboot.org/27168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-21 17:39:48 +00:00
Patrick Rudolph e66b10f3e1 tianocore: Fix RPM package name
The packge uuid-devel doesn't provide the required files,
but libuuid-devel does.

Change-Id: I61d537e4f1fca0d7172c129a75e13aa58452763f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/27136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-21 17:28:55 +00:00
Bora Guvendik 7fe9e8edea soc/intel/apollolake: unify definition for spi base address
Use SPI_BASE_ADDRESS instead of PRERAM_SPI_BASE_ADDRESS like
big core in order make common code implementation straightforward.

Change-Id: Ibcb013fc95de29234253e89c9ca100cc468d44f6
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/27097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-21 15:55:05 +00:00
Subrata Banik 90d3b2b0c0 soc/intel/common: Make infrastructure ready for Intel common stage files
Select all Kconfig belongs into Intel SoC Family basecode/stage files
and include required headers from include/intelbasecode/ files.

BUG=None
BRANCH=none
TEST=Code is compiling with cannonlake configurations and also booting
on cannonlake RVP.

Change-Id: Iac99b4346e8bf6e260b00be9fefede5ad7b3e778
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-21 15:54:48 +00:00
Arthur Heymans 2e464cf3b0 sb/intel/i82801xx: Use common RCBA MACROs
Change-Id: I61fb3b01ff15ba2da2ee938addfa630c282c9870
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-21 15:51:48 +00:00
Arthur Heymans 8d0e88db34 sb/intel/common/rcba_pirq.c: Use common RCBA acces MACROs
Change-Id: I2fe8d8388cb96e42af4f9be251a41cceeb2e4710
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27042
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21 15:51:38 +00:00
Arthur Heymans 1f2ae91074 sb/intel/common: Make RCBA manipulation MACROs common
No Change in BUILD_TIMELESS.

Change-Id: I634526269d45ebdc6c31cdc28d9ec846b397211d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-21 15:51:12 +00:00
Arthur Heymans 58a8953793 Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location"
In the end it does not look like RCBA register offsets are fully
compatible over southbridges.

This reverts commit d2d2aef6a3.

Is squashed with revert of "sb/intel/common: Fix conflicting OIC
register definition" 8aaa00401b.

Change-Id: Icbf4db8590e60573c8c11385835e0231cf8d63e6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-21 15:50:16 +00:00
Arthur Heymans 4dfb5f1055 util/abuild: Fix building when not in coreboot root dir
Change-Id: Ibe54096f275a05bda745ae2cc76c0109281c0c4b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-21 15:47:44 +00:00
Richard Spiegel 35282a0f1b soc/amd/stoneyridge/southbridge.c: Store PM related registers in cbmem
PM registers used for generating SWS values are being stored in a static
variable within southbridge.c. In order to have it available for any source
involved in building the platform, move the storage to cbmem, using id
CBMEM_ID_POWER_STATE. Also add a variable that informs from which state
the system is waking from, extracted from register ACPI_PM1_CNT_BLK. This
variable will later be useful in detecting failed S3 resume.

BUG=b:80119811
TEST=Add code to print SWS parameters and state it's waking from. Build
and boot grunt, suspend and resume, check output for valid values. Remove
the print code.

Change-Id: Ib27a743b7e7f8c94918caf7ba5efd473f4054986
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27109
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21 15:47:31 +00:00
Arthur Heymans cd7dfaf3b0 drivers/ati/ragexl: Remove dead code
Is unused in the tree.

Change-Id: I8a5308b6c7773d791d47832e620558394f1d727e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22132
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21 15:46:37 +00:00
ren kuo 26a4b9d063 google/lars,lili: Add SPD mapping for Hynix 8GB config
Upstreaming Chromium commit 0bc6c43:
Lili: Update Memory IDs

TEST=Build and boot up on lili board

Original-Change-Id: I6da1e97820b1bf2e751102384eed07236143fe2b
Original-Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/956782
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>

Change-Id: Icf6588582da3b4a7861bced539d51a914b011dc4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27135
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21 15:46:09 +00:00
Nico Huber bb10ec3d41 payloads/external/GRUB2: Use pkg-config over freetype-config
`freetype-config` is gone and was obsolete for a long time.

Change-Id: Id3058e55b1630f43225d3cd1ad91801c4085874f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/26822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-21 14:57:13 +00:00
Nico Rikken 28cdd4c8d3 mb/lenovo/t520: Add Dual Graphics CMOS support
Adds the CMOS option for Dual Graphics, as is present in more Lenovo models
already. Enabling this option ensures that the NVIDIA GPU is powered.

More PCI devices can be observed when activating this setting. It was verified
on a W520, also by loading a VGA option ROM and achieving a working Dual
Graphics system.

The CMOS default has been kept to 'Integrated Only', as the usage of Dual
Graphics requires an option ROM and drains the battery more quickly.

Change-Id: I41ccabd4554ca019684edd6f8b1c23679212c59f
Signed-off-by: Nico Rikken <nico@nicorikken.eu>
Reviewed-on: https://review.coreboot.org/26114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-06-21 09:45:34 +00:00
Nick Vaccaro 91b76f19f4 mb/google/poppy/variants/nocturne: add two new memory options
- add K4E6E304EC-EGCF and K4EBE304EC-EGCF to memory strapping table
- add SPD files for K4E6E304EC-EGCF and K4EBE304EC-EGCF

BUG=b:110277021
BRANCH=none
TEST=none

Change-Id: If1322311bd91842d6d32725822d91fd6d9e8077c
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-21 09:44:28 +00:00
Sathyanarayana Nujella 881ff66183 mb/google/poppy/variants/nocturne: Update Slave Addresses of Max98373 Amp's
When played Left Only Audio and Right Only Audio, we observed that Audio
got swapped. Left Data played on Right Speaker and Viceversa.

This patch fixes the above issue.

BUG=b:73635449
TEST=Play Left only & Right only Audio and cross check Audio.

Change-Id: Ie9c417ad0634a76fc8a4126ee75886603f1b3da0
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/27167
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21 09:43:37 +00:00
Cole Nelson 63b6fea5c9 soc/intel/{skl,kbl}: ensure C1E is disabled after S3 resume
C1E is disabled by the kernel driver intel_idle at boot.  This does not
address the S3 resume case, so we lose state and C1E is enabled after S3
resume.

Disable C1E for SKL and KBL.  This gives a coherent state before
and after S3 resume.

TEST='iotools rdmsr cpu 0x1fc'. Returns the same value after boot and S3
resume with bit [1] set to zero (0x20005d).

Change-Id: I1343f343bfac9b787f13c15b812c0a201dcccb38
Signed-off-by: Cole Nelson <colex.nelson@intel.com>
Reviewed-on: https://review.coreboot.org/27125
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21 09:43:19 +00:00