Enable Acoustic noise mitigation for redrix and set slew rate to 1/8
BUG=b:204009588
TEST=build and verified by power team
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I0fc0bb68c4de6fca60ee290eb46a77200d748ca8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Related to https://review.coreboot.org/c/coreboot/+/58555
commit-id: 35b7e0a2d82ac
In 58555, we added the SOC ID for Stoneyridge in amdfwtool
command line. But it raised building error because it then called
"set_efs_table" without setting SPI mode. So we skipped calling that.
But in set_efs_table, it has case for Stoneyridge. The boards also
need to have this setting. So we remove the skipping and give the
proper SPI mode in mainboard Kconfig.
Change-Id: I24499ff6daf7878b12b6044496f53379116c598f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Fix the CL:
https://review.coreboot.org/c/coreboot/+/58942
The type comboable was int but set as true.
Change-Id: Id2c43378735c089a27a5aa683b55a0f7ec3677de
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
For combo layout, this is for combo header.
For non-combo layout, this is for PSP directory.
Change-Id: Ie7b5aec6b511ad61972908d1d22a13aeb7dd73a9
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Update Delta Lake document following the publish of OCP blog
and the Wiwynn press release.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I3eaa765bf9918988b4b5cb01e8607a5c27b9bd17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Windows (10/11) freaks out and generates an interrupt storm
if two ACPI devices are enabled and share an interrupt, even
when only one device is actually present. To mitigate this,
mark Cyan's touchpad/touchscreen interrupts as SharedAndWake
rather than ExclusiveAndWake.
Test: build/boot Windows 10 on Relm, observe normal CPU
usage in Task Manager for System Interrupts task when
touchpad/touchscreen in use.
Change-Id: I09bc878318f9fa6252f65a42ad46109418805fa0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
When fetching antirollback information for the kernel, it is not always
known ahead of time what the current size of the kernel secdata area
is. If the incorrect size is passed, the TPM will return back the
correct size, but at the cost of an extra transaction; when using cr50
over I2C, this can be as much as 20ms. Currently, the first attempt uses
the minimium size (aka version 0 or 0.2), and if another size is used
(which is the case for all modern cr50-based boards, version 1 or 1.0),
then a transaction is wasted on every boot.
Therefore, change the default size sent to the TPM to be the default one
used in the VB2 API instead of the minimum one.
BUG=b:201304784
TEST=verify TPM initialization time drops by ~20ms. Also the Kernel NV
Index is read correctly in the BIOS logs.
src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
504:finished TPM initialization 99,953 (65,606)
Change-Id: I22d9c0079bb1175f24ff7317d116e79aa5ba08ed
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
As per the TPM spec, if offset and the size field of data add to a value
that is greater than the dataSize field of the NV Index referenced by
nvIndex, the TPM shall return an error (TPM_RC_NV_RANGE). Handle the TPM
error and map it to an appropriate vboot error.
BUG=None
TEST=Build and boot to OS in Guybrush.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I8b403e2f33cc1368065cc21f73df1102695f73eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Correct GPE settings so touchpad can wake up DUT.
BUG=b:206526991
TEST=emerge-brya coreboot and builds without error
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I1978e9220ad7a275d351ad5eeff7036131926b24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Used H1 firmware where the last version number is 0.0.22, 0.3.22 or
less to production that will need to disable autonomous GPIO power
management and then can get H1 version by gsctool -a -f -M
BUG=b:205315500
TEST=emerge-brya coreboot and test that DUT can boot to OS.
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Ib26797fa2d4d0b1a6eb28c5d79b9ac0a6054abd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This reverts commit 1399442289.
Reason for revert:
Some Cr50 chips with old firmware version (x.y.22) don't support
long pulse interrupt command, requiring dynamic GPIO PM to be disabled
to intercept short pulse interrupt.
Due to this coreboot needs to expose SGPM, RGPM and EGPM ACPI methods
to support power gating of GPIO communities from the kernel when dynamic
GPIO PM is disabled.
BUG=b:204832081
BRANCH=None
Test= S0ix works with dynamic PM disabled.
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Change-Id: I2b5b00878062f8a499641d7a47db54ed078cd6cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
SSD sometimes can't be detected in in warm/cold boot stress.
M.2 spec describes SSD_PERST# should be sequenced after power enable.
BUG=b:199967106
TEST=SSD was always discovered in warm/cold boot stress.
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I74c21cd96cf1c4518c4ed7c0b3b39e915b6b1ff7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add VBTs for all hatch variants currently supported by
ChromeOS recovery images. For variants which use multiple
VBTs and select at runtime, ensure these are added directly
to CBFS.
Change-Id: I3c62ce204e3272e778ba0a34f7a47a65d8125f53
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
TypeC AUX configuration is variant specific. So move into variant level.
BUG=b:205235144
TEST=No typeC port 0 AUX in felwinter.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I02bfea462cf4c6359fd8d5cca4368786ee03bc8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Make psp verstage initialization more granular be splitting
verstage_soc_init into separate functions. Specifically, create
soc init functions for espi, i2c spi, and aoac.
BUG=b:200578885
BRANCH=None
TEST=Build and boot guybrush
Change-Id: I489889a0dfd4016aa4f2b53a2c6a7a1ea4459e60
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Add VBTs for all octopus variants currently supported by
ChromeOS recovery images. For variants which use multiple
VBTs and select at runtime, ensure these are added directly
to CBFS.
Change-Id: I4b5c4268f9255d658f9762d94488db66e0677830
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Windows (10/11) freaks out and generates an interrupt storm
if two ACPI devices are enabled and share an interrupt, even
when only one device is actually present. To mitigate this,
mark Peppy's interrupts as Shared rather than the default
of Exclusive.
Test: build/boot Windows 10 on Peppy, observe normal CPU
usage in Task Manager for System Interrupts task when
touchpad in use.
Change-Id: Ida78ddec3105cef6581cdde78da2e2c97d983a0a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This board does not have a LPC or eSPI connection to the NC FPGA anymore
and therefore IO port 0x80 is not useable for POST codes anymore. Enable
the feature of sending the POST codes to the NC FPGA via PCI so that the
POST codes are visbile again in coreboot.
Change-Id: I9043e4ec9a2ad6b946e373bb3dce9da3d42d00d1
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
So far POST codes were mapped on IO port 0x80 inside the NC FPGA which
was connected via the LPC bus to the host CPU. On recent x86 generations
the LPC bus was replaced with eSPI and not all Siemens boards have the
eSPI routed to the NC FPGA. In order to have POST codes visible on those
boards the display is accessible via PCI in addition.
This patch adds the feature of sending the POST codes to the NC FPGA via
a PCI mapped register.
Change-Id: Ie15686de49cface17830365d78fe7c54cce183a0
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This patch adds cbfs_get_size() and cbfs_get_type() helper functions
(and _ro_ variations) to look up the size or type of a CBFS file without
loading it. Generally, use of these should be discouraged because that
tends to mean that the file needs to be looked up more than once, and
cbfs_alloc() or cbfs_type_load() are usually the more efficient
alternative... but sometimes they're unavoidable, so we might as well
offer them.
Also remove the <cbfs_private.h> header which had already become sort of
unnecessary with previous changes. cbfs_boot_lookup() is now exported in
<cbfs.h> for use in inlines, but should not be used directly by other
files (and is prefixed with an underscore to highlight that).
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I8092d8f6e04bdfb4df6c626dc7d42b402fe0a8ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Initialize SPM (System Power Management) in RAM stage.
This adds 55ms to the boot time.
TEST=program counter of SPM is correct value(0x250) after booting up
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I822417f7a679107760b202dd43fb79d1934940bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This patch adds support for loading SPM firmware from CBFS to SPM SRAM.
SPM needs its own firmware to enable SPM suspend/resume function which
turns off several resources such as DRAM/mainpll/26M clk when linux
system suspend.
TEST=program counter of SPM is correct value(0x250) after booting up
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia13e5a2ecf09561856b7e958128cd2f045c39f33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59341
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SSPM is "Secure System Power Manager" that provides power control in
secure domain. The initialization flow is to load SSPM firmware to
its SRAM space and then enable.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I92eb501a1e48dd02d2f94ff392933261e6a42391
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Setting of MSDC is defined by soc, so we move them to soc folder.
TEST=emerge-cherry coreboot; emerge-asurada coreboot
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I84ad8a4cde120c97024870ebf750d44b36c2284d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
DCM (dynamic clock management) can dynamically slow down or gate clocks
during CPU or bus idle. Enable DCM settings on the MT8186 platform.
TEST=build pass and check register ok
BUG=b:202871018
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com>
Change-Id: I82add5ae629d59f7d6773e26ac9cba9d54ab8caf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This patch modifies the pch_get_ltt_value() function return type from
uint16_t to uint32_t to accommodate platforms with more than one thermal
threshold.
For example: Alder Lake PCH Trip Point = T2L | T1L | T0L
where T2L > T1L > T0L.
BUG=b:193774296
Change-Id: I5f46ccb457b9cfebf13a512eabb3fb0fab8adb39
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Update board type to 4 as per MRC team's input. This
fixes LP5 sagv point 3 being clipped from the expected
5200Mhz to 4800Mhz.
TEST=Boot to OS, verify frequency locked.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I9472aec41537425c1ed648b949f484939ee9ff99
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Begin comments with # instead of ## to match the Makefile.inc generated
by spd_tools.
BUG=None
TEST=None
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: If2d716a7338fd5af8216b2bcd894fc88a9df137e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
In next phase build, the audio codec will change to ALC5682I-VS
BUG=b:205883511
TEST=emerge-brya coreboot chromeos-bootimage and check audio function
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I5906ef9bb88da7fe450a986bf7dd1ee701227f95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This will enable preloading ramstage. By preloading the file into
cbfs_cache we reduce boot time.
BUG=b:179699789
TEST=Boot guybrush to OS and see 12ms reduction in boot time.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ibe12de806449da25bc0033b02fcb97c3384eddc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Now that CBFS has this functionality built in, we no longer need to
manually code it.
payload_preload used to use the payload_preload_cache region to store
the raw payload contents. This region was placed outside the firmware
reserved region, so it was available for use by the OS. This was
possible because the payload isn't loaded again on S3 resume.
cbfs_preload only uses the cbfs_cache region. This region must be
reserved because it gets used on the S3 resume path. Unfortunately this
means that cbfs_cache must be increased to hold the payload. Cezanne is
the only platform currently using payload_preload, and the size of
cbfs_cache has already been adjusted.
In the future we could look into adding an option to cbfs_preload that
would allow it to use a different memory pool for the cache allocation.
BUG=b:179699789
TEST=Boot guybrush and verify preloading the payload was successful
CBFS DEBUG: get_preload_rdev(name='fallback/payload') preload successful
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Idc521b238620ff52b8ba481cd3c10e5c4f1394bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
eGPIO is a scheme which allows special power island domain IOs to be
reused as regular chip GPIOs by muxing regular TLMM functions with
Island Domain functions. Allow the eGPIO to be configured via
gpio_configure API to be used as a TLMM gpio.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Change-Id: Ib2598a41ba3bb8a8a2acff8253b5bb78633f89f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Some eMMCs need 80+ms for CMD1 to complete. And the payload may need to
access eMMC in the very early stage (for example, depthcharge needs it
20ms after started) so we have to start initialization in coreboot.
TEST=boot kernel from eMMC ok
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I3bc06b1fc506b1d6f54f7f456117d22477a87e29
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The Corsola reference design has both eMMC and SD Card interfaces
so we have to configure both in RAM stage.
TEST=boot kernel from eMMC and SDCard ok
BUG=b:202871018
Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Change-Id: I0fa8712eb61685a305dc5dd49cc2e55f1f0eecd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The Corsola reference design has both eMMC and SD Card interfaces
so we have to configure both in RAM stage.
TEST=build pass
BUG=b:202871018
Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Change-Id: I2f26a8a11edd29a80a7195e3a324151d66ecb293
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Wisley Chen