- Fix some poor programming practice (breaks of strict aliasing as well
as not checking the return value of read)
- Use PRIx64 instead of %llx to prevent compilation warnings with both
32bit and 64bit compilers
- Use same compiler command options when linking inteltool and when
detecting libpci for inteltool
Change-Id: I08b2e8d1bbc908f6b1f26d25cb3a4b03d818e124
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/752
Tested-by: build bot (Jenkins)
Reviewed-by: Mathias Krause <minipli@googlemail.com>
The inline assembly for cpuid() was 32 bit specific. Additionally a
format string referencing a size_t argument wasn't using the %z length
modifier.
Change-Id: Iac4a4d5ca81f9bf67bb7b8772013bf6c289e4301
Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
Reviewed-on: http://review.coreboot.org/211
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
See http://www.coreboot.org/DirectHW for more information
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6454 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Add support for dumping the MSRs on model_f2x and dumping GPIOs and PM
registers on ICH5. Add ICH5 and i865 to the supported chips list.
Enable the dumping of BAR6 on i865.
Sample output:
Disabling memory access:
$ sudo setpci -s 6.0 0x04.b=0x0
$ sudo ./inteltool -m | head -n 9
Intel CPU: Processor Type: 0, Family f, Model 2, Stepping 7
Intel Northbridge: 8086:2570 (i865)
Intel Southbridge: 8086:24d0 (ICH5)
============= MCHBAR ============
Access to BAR6 is currently disabled, attempting to enable.
Enabled successfully.
BAR6 = 0xfecf0000 (MEM)
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Acked-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6197 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- pmbase is on southbridge function 3 on I82371XX
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6128 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Both are tested and appear to be working, however I'm not 100% clear
on if the NM10 has any other PCI IDs.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Paul Menzel <paulepanter@users.sourceforge.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5709 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
northbridge. Also add support for the very similar Q963/965 northbridge.
Tested:
D510: confirmed working, with MCHBAR enable code
Q965: writes to bit 0 to enable MCHBAR access are ignored, all other functions work
Untested:
D410/D525/N400: should be the same northbridge
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Paul Menzel <paulepanter@users.sourceforge.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5632 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
ICH6 Southbridge,
82915 Series Northbridge,
P4 6xx Series CPU
to inteltool
Tested on my Clevo D900T, based on ICH6 and i915P, with a p4 630
installed.
Signed-off-by: Pat Erley <pat-lkml@erley.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5469 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The registers are (as far as I can tell) unchanged with respect to those
of the PM965.
Signed-off-by: Loïc Grenié <loic.grenie@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4905 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
Some minor modifications to allow 64bit/32bit compilation on Darwin
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4621 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Add identification for X58 and ICH10R.
Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4380 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* PMBASE dumping now knows the registers.
* Add support for i965, i975, ICH8M
* Add support for Darwin OS using DirectIO
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3794 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
immensly when they know more systems / cpus / chipsets
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
have different register meanings, so they get their own lookup tables.
This is a trivial patch.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3307 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Stefan Reinauer