No board uses AMD PI 00630F01, so drop it. And drop a single reference
to the now-removed `NORTHBRIDGE_AMD_PI_00630F01` Kconfig option inside
the `drivers/amd/agesa/acpi_tables.c` file.
Change-Id: Ibc45a4a6041220ed22273c1d41f9b796e1acb901
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54897
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TEST=boot Debian with Linux 4.14 on apu2 4GB ECC and apu3 2GB no-ECC
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I0387071748262fdeaa5f4d9a71bb87d4d83241b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52761
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Not all resources were being reported, add them.
TEST=boot Debian with Linux 4.14 on apu2 4GB ECC and apu3 2GB no ECC
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ia57ab026218f4aae0a98c2081412c4a9ebb7f57a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52927
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the DRAM reporting to read_resoures function before the resources
are being set. Use generic PCI domain resource allocation functions
to read and set domain resources.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I9605f7fad30eb093bddf9bc34e31dea9f5f846ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Remove obsolete resource assigning functions. IO and MMIO address
registers are currently set by amd_initcpuio to cover whole PCI hole
under 4G to MMIO and IO 0x0000-0xFFFF is configured to be routed to
southbridge already. Use generic PCI and resource allocation functions
wherever possible to set northbridge resources.
TEST=boot Debian with Linux 4.14 on apu2 4GB ECC and apu3 2GB no ECC
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I8dd5e40bce513c5ba7f1d42a06e7ab0846666942
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Memory region 0xa0000 to 0xc0000 was not reserved, the first
PCI memory resources might get assigned in this space.
FIXES: aopen/dxplplusu PCI EHCI 0:1d.7 memory resource.
Change-Id: Ia17025bde83b91d71ad719de6348197cf92e267e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The CMOS option system does not support negative integers. Thus, retype
and rename the option API functions to reflect this.
Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Do not use get_dram_base_mask to calculate system DRAM limits. Shift
operation around values operating on base and mask were causing
overflows and thus incorrect system DRAM limit. Another function
returning base and limit in KiB has been developed to avoid data loss.
Keep DRAM high base and limit in calculations only for Trinity where
the physical CPU address bits is 48. Although it is almost impossible
to have a non-zero value there, the platform would have to support
nearly 256GB of RAM.
TEST=boot PC Engines apu1 2GB, apu2 4GB and apu3 2GB and boot Debian
with Linux 4.14
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I3b5c1df96c308ff50c8de104e213219a98f25e10
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Now the bootblock is not limited to 64K so integrating vboot into the
bootblock reduces the binary size.
Change-Id: Ic92ecf8068f327a893d20924685ce571752d379f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52787
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This macro contains a cast on the and-mask, which can suppress actual
type overflow issues. Replace it with wrapper functions around the
existing macros in device/mmio.h which still contain a type cast, but
it is a non-issue because the wrapper functions now allow compilers to
check for overflows.
Change-Id: I975bf8152fc961767f0292bff4a03aecd8c65f56
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51886
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that all code has been switched to make use of the new accessors,
the old ones can be dropped. Follow-ups will clean up bitwise accessors.
Change-Id: Ib4cb24ca71f3c3717ea50d147ddca74aaf0288fa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
To keep the "main" haswell.h header short and simple, move PEG register
definitions into a separate file, as done with most other registers.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: Ibfca00456115a4a0c861dd6738605214a7d43fd9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51891
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These accessors were defined as macros in order to allow verifying the
patches that replaced the accessors using BUILD_TIMELESS=1. Now that all
replacement is done, turn the new accessors into static functions to let
the compiler perform overflow checks on the arguments.
Change-Id: Iaa2ba208fba11c4a00f2b8a05eb1129a32c6c092
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52816
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove leading and trailing underscores and change `RAMINIT_H` to be
more consistent with other headers.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: Ie20fcaa0f9393eb0a34054eda53b9bade63cc0d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51890
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop unused chipset type macros, remove unnecessary guards and
reorganize contents so that headers can be included at the top.
Also drop the inclusion from ASL, as it is no longer necessary.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: I6fcc0d428d0fdbf410bcbeb6ae4809870b7b498f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51889
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 4447996cc5.
It looks like the patch repurposed the `memory_reserved_for_heci_mb`
variable as an indicator if the ME firmware is fine. The change to
setup_heci_uma() made it bail out early, even though the implementation
is obviously prepared to set things up even if the requested UMA
size is 0. This also leaves the code in an inconsistent state: The
second if's condition is always true.
Resolves: https://ticket.coreboot.org/issues/305
Change-Id: Ie5a98be3f660078a85a79b5551e86f90f148974f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52426
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Ott <coreboot@desire.ch>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of counting consecutive matches (in `j`), check for a second
match directly in the control flow. Also, add some dedicated variables:
* `tap`: Keeps track of the tap value that resulted in a match and
is eventually programmed into the hardware.
* `tap2`: Is just temporarily used to search for another edge.
Keeping `tap` sync'ed with the hardware has the benefit that we don't
need to read the programmed value back for later fixups.
Change-Id: I3ae541c39efdc695f5ca74bc757b2f009239ec93
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Move the last block of the sync DLL programming up. It's independent
of the switch/case statement that it's moved around.
Change-Id: I71bc1ca1c629e4f2f4a13474c7e2c22d1a3b65d9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
There is no nb/amd/pi northbridge left in coreboot that could be paired
with the Bolton FCH, since the remaining nb/amd/pi northbridges all use
an integrated FCH (Avalon on Mullins and Kern on Carrizo) while Bolton
is a discrete FCH. I ran into this when verifying if the common soc/amd
GPIO functionality that gets added by selecting
SOC_AMD_COMMON_BLOCK_BANKED_GPIOS is valid for all chips selecting it
and that code isn't valid for Bolton that uses the old GPIO 100
interface.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iffe876bee96e42645e1be10730b78959b1c06d59
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52222
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Wrap `r` in parentheses to avoid unexpected behavior with compound
expressions. Fortunately, all uses of this macro do not cause issues.
Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.
Change-Id: Id0f05a507c5e7e8c50e9765261d86bae73c7b5a6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Some cases break reproducibility if refactored, and are left as-is.
Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.
Change-Id: I163995c0b107860449c2f36ad63e4e4ca52decb2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51878
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `CLKCFG_UPDATE` macro is copied from gm45 and unused. Correct it and
use the CLKCFG macros instead of magic values.
Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.
Change-Id: I17e972eba21282ac84c7afe10b7149cd1131fd07
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51877
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Breaking strings across multiple lines hurts greppability. Refactor the
code a bit to drop one indentation level, and then reflow the strings.
Change-Id: I0accdfd0d2c5f58e4da493ba0d4b5c6a067d92c3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51876
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Bit 4 needs to be set then polled for after changing sync DLL taps.
Change-Id: I61b73998dec84710eec0d2561a6f4d88068e3373
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51872
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These changes are not reproducible for some reason.
Change-Id: If1fcd0285c3a14686f7deb70d83a4c63d57d62fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51871
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These changes are not reproducible for some reason.
Change-Id: I43b445b8af8871db87fb86747db8a35cec75716a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51867
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are some cases in `northbridge_topology_init` where condensing the
operation using one macro changes the binary, and have been left as-is.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: I59c7d1f8d816b95e86d39dcbf7bc7ce8c34f0770
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51865
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The {MCH,DMI,EP}BAR macros can be used for both reading and writing.
While this can sometimes be useful, compile-time overflow checking is
limited. Moreover, and-masks need to be bit-wise negated, which is easy
to forget and may result in spurious overflow warnings, and silencing
them with a cast also suppresses true integer overflow issues.
To address these limitations and for consistency with the existing MMIO
API (arch/mmio.h and device/mmio.h), these macros will be replaced with
prefixed wrappers around MMIO API functions. However, existing platform
code needs to be refactored, and the risk of introducing regressions is
substantial. To minimize the risk of breakage, the bulk of the platform
code changes will be verified using reproducible builds.
This patch introduces the new accessors, to be put to use in follow-ups.
These accessors are implemented as macros so that subsequent commits can
be verified using reproducible builds. They will be replaced with actual
functions after refactoring all platforms.
Change-Id: I85376a9e2f6cd042b41036f90de7f9edc7ad4508
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51864
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These p-suffixed helpers allow dropping pointer casts in call-sites,
which is particularly useful when accessing registers at an offset from
a base address. Move existing helpers in chipset code to arch/mmio.h and
create the rest accordingly.
Change-Id: I36a015456f7b0af1f1bf2fdff9e1ccd1e3b11747
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51862
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Haswell MRC.bin can return zero even when raminit did not complete
successfully. When this happens, the memory controller will not have
acknowledged raminit: the mc_init_done_ack bit in the MC_INIT_STATE_G
register will be zero, and memory accesses will lock up the system.
To handle this situation more gracefully, check the mc_init_done_ack bit
after running MRC. If the bit is not set, log a fatal error and halt.
Tested on Asrock B85M Pro4:
- With badly-seated DIMMs, MRC raminit fails and coreboot dies.
- After reseating the DIMMs, the board still boots successfully.
Change-Id: I144bf827f65cd0be319c44bf3d407ddc116b129d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
There's no good reason to use values smaller than 2 GiB here. Well, it
increases available DRAM in 32-bit space. However, as this is a 64-bit
platform, it's highly unlikely that 32-bit limitations would cause any
issues anymore. It's more likely to have the allocator give up because
memory-mapped resources in 32-bit space don't fit within the specified
MMIO size, which can easily occur when using a discrete graphics card.
Change-Id: If585b6044f58b1e5397457f3bfa906aafc7f9297
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52072
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's no good reason to use values smaller than 2 GiB here. Well, it
increases available DRAM in 32-bit space. However, as this is a 64-bit
platform, it's highly unlikely that 32-bit limitations would cause any
issues anymore. It's more likely to have the allocator give up because
memory-mapped resources in 32-bit space don't fit within the specified
MMIO size, which can easily occur when using a discrete graphics card.
Change-Id: I6cdce5f56bc94cca7065ee3e38af60d1de66e45c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52070
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `pdwm` part was supposed to be an abbreviation of `power down`, but
it is neither self-explanatory nor properly-spelled. Rename the enum.
Change-Id: I7b83c71d4534b62e18ced04eebe6a65089e1d874
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Use the actual value as it is more informative.
Change-Id: Id3bd8ccdf79d1e3fdf97cda049f81271bb017ef7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
