Commit Graph

52841 Commits

Author SHA1 Message Date
Daniel R. Franzini def14b60f1 doc/tutorial/part1.md: Fix package name to install qemu on Debian
Fix package name to install qemu on Debian. It used to be 'qemu'
only but it is now called 'qemu-system'.

Signed-off-by: Daniel R. Franzini <danielt3@usp.br>
Change-Id: Ibae9031a3e397925db95b7283fa8c6573f6d5858
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74894
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-02 12:41:52 +00:00
Subrata Banik 65b64b3f03 soc/intel/alderlake: Select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN config
At present the problem has only been reported with Alder Lake and
Raptor Lake FSP where MultiPhaseSiInit API is unable to return any ERROR
status. Hence, this patch ensures to select applicable W/A config to
read FSP return status from the FSP Reset HOB.

BUG=b:278665768
TEST=Able to select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN for ADL/RPL SoC
code and call into this API to know the return status from
MultiPhaseSiInit FSP API.

Without this patch:

  IshInit() Start
  IshDisable() Start
  IshPerformGlobalReset()
  ....
  ....
  FSP returning control to Bootloader with reset required return
       status 40000003
  FspMultiPhaseSiInit Index-1 returned 0 <-- after control returns
       into coreboot, the `status` from the FSP API is reset to `0`
       instead 0x40000003. Hence, coreboot avoid hitting the reset.

With this patch:

  IshInit() Start
  IshDisable() Start
  IshPerformGlobalReset()
  ....
  ....
  FSP returning control to Bootloader with reset required return
       status 40000003
  FSP: handling reset type 40000003 <-- coreboot is able to understand
                                        the reset request in proper.
  GLOBAL RESET!
  global_reset() called!
  HECI: Global Reset(Type:1) Command

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I18a918cca7e19e03ed6020c55c86c64a94212963
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74785
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-02 10:51:33 +00:00
Subrata Banik 25d100243c drivers/intel/fsp2_0: Apply FSP Reset Status W/A for MultiPhaseSiInit
This patch calls into fsp_get_pch_reset_status() to get the
MultiPhaseSiInit API return status if
FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN is enabled.

Ideally FSP API should be able to return the status (both success and
error code) upon exiting the FSP API but unfortunately there are some
scenarios in ADL/RPL FSP where MultiPhaseSiInit API is unable to return
any ERROR status. Hence, this function can be considered as an
additional hook to read the FSP reset status by reading the dedicated
HOB without relying on the FSP API exit status code.

Any SoC platform that selects the FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN
config will call into this newly added API to get the FSP return status
from MultiPhaseSiInit.

BUG=b:278665768
TEST=Able to select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN for ADL/RPL SoC
code and call into this API to know the return status from
MultiPhaseSiInit FSP API.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I749c9986e17e4cbab333b29425c9a4a4ba4128fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74784
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
2023-05-02 10:51:17 +00:00
Subrata Banik da7d00ef21 soc/intel/common: Introduce API to get the FSP Reset Status
This patch creates a function to read the FSP API Reset Status. This
function relies on the FSP Scheduled Reset HOB which holds the reset
type (warm/cold/shutdown) information along with any platform specific
reset need (like global reset).

Ideally FSP API should be able to return the status (both success and
error code) upon exiting the FSP API but unfortunately there are some
scenarios in ADL/RPL FSP where MultiPhaseSiInit API is unable to return
any ERROR status. Hence, this function provides an additional hook to
read the FSP reset status by reading the dedicated HOB without relying
on the FSP API exit status code.

Additionally, create FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN config option
to handle broken FSP API return status issue.

Any SoC platform that selects the `FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN`
config will call into this newly added API to get the FSP return status
from MultiPhaseSiInit.

BUG=b:278665768
TEST=Able to select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN for ADL/RPL SoC
code and call into this API to know the return status from
MultiPhaseSiInit FSP API.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ief5d79736cc11a0a31ca2889128285795f8b5aae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-02 10:51:01 +00:00
Kyösti Mälkki 72e63d5e9c protectcli/vault_bsw: Drop USB power control bits in GNVS
There is no platform-level implementation for USB port power management
in various sleepstates. This mainboard never evaluates the set GNVS
variables S3U0, S3U1, S5U0 and S5U1 in ASL or in its SMI handlers.

Change-Id: Ic7af2d608d95c6691f31ef1b8af72f96da20787c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-01 17:34:10 +00:00
Kyösti Mälkki 167ccc7e65 mainboard/*: Drop USB power control bits in GNVS
There is no platform-level implementation for USB port power management
in various sleepstates. The mainboards changed here never evaluate the
set GNVS variables S3U0, S3U1, S5U0 and S5U1 in ASL or in their SMI
handlers.

Change-Id: Ia1bc5969804a7346caac4ae93336efd9f0240c87
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
2023-05-01 17:33:31 +00:00
Kyösti Mälkki 96581b3217 SMBIOS: Group Kconfig dependency
Change-Id: I5a75a7230fd78c0a9926adc491059f55647cc9a3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-01 17:32:06 +00:00
Matt DeVillier 03220d6023 mb/google/volteer/Kconfig: Alphabetize variants, Kconfig selections
Change-Id: I634af65cd41e0d70e673d550ed8063abc6eea6d4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-05-01 14:48:06 +00:00
Matt DeVillier 7e6f323d98 mb/google/volteer: Add VBT data files for variants
Add data.vbt files for all variants supported by current volteer
recovery image. Several boards use the same VBT, so place the "common"
VBT under the baseboard directory and set it as the default.
For variants with a unique VBT, override the default and use the file in
their respective variant directory. Select INTEL_GMA_HAVE_VBT for all
variants which have a VBT file.

TEST=build/boot various volteer variants

Change-Id: I728ab81938c78f600ff8931a8073d1f7de152c09
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74852
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-01 14:47:31 +00:00
Matt DeVillier 71fee41ef5 soc/intel/adl: Unhide PMC, IOM ACPI devices from OS
These were hidden because no Windows drivers existed, but now that
they do, the ACPI devices need to be visible in order for the
drivers to properly attach.

TEST=build google/banshee, boot Windows, verify Windows drivers
correctly attach to PCM/IOM devices.

Change-Id: Idbbaee29bffb49059d8450abd09e0c3f7b490fae
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74850
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-05-01 14:47:10 +00:00
Matt DeVillier 3d85d6b292 soc/intel/tgl: Unhide PMC, IOM ACPI devices from OS
These were hidden because no Windows drivers existed, but now that
they do, the ACPI devices need to be visible in order for the
drivers to properly attach.

TEST=build google/drobit, boot Windows, verify Windows drivers
correctly attach to PCM/IOM devices.

Change-Id: I1520a71e318674baa234fc6a2126d1d17933d983
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-05-01 14:47:04 +00:00
Matt DeVillier c259d71928 soc/amd/stoney/acpi: Unhide PCI0 root device from OS
In order for Windows to detect/load drivers for any child devices,
the PCI0 root device status must be enabled and visible.

TEST=build google/liara, boot Windows, verify PCI child devices
visible in Device Manager.

Change-Id: I3fb1ba11247f0811120a4cf8a4fd99342ae201de
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-01 14:43:09 +00:00
Anil Kumar afb926ab0a soc/intel/cmn/cse: Decouple ME_RW compression from CSE RW Sync
The change 'commit Iac37aaa5ede5e1cd ("Add Kconfigs to indicate
when CSE FW sync is performed")' adds support to choose CSE FW update
to be performed in ROMSTAGE or RAMSTAGE. The patch also introduced a
dependency on ME_RW firmware compression.

This patch removes the dependency between CSE FW sync in RAMSTAGE and
ME_RW firmware compression as these two are not related and should be
decoupled to support CSE FW sync in RAMSTAGE without the requirement
to compress ME_FW.

Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I5ca4e4a993e4c4cc98b8829cbefff00b28e31549
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74796
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-05-01 14:42:53 +00:00
Grzegorz Bernacki 042ac352ea acpi: Add missing cbfs_unmap()
cbfs_map() can allocate memory, so cbfs_unmap() should be
called before leaving the function.

BUG=b:278264488
TEST=Built and run with additional debugs on Skyrim device
to confirm that data are correctly unmapped

Change-Id: Ibf7ba6842f42404ad8bb415f8e7fda10403cbe2e
Signed-off-by: Grzegorz Bernacki <bernacki@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
2023-05-01 14:41:45 +00:00
Jimmy Su f127becbf1 mb/google/nissa/var/craask: avoid camera LED blinking during boot
Camera LED will blink several times as sensor is being probed during kernel boot.

Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips
initial probe during kernel boot and prevent privacy LED blink.

BUG=b:274634319
TEST=Build and boot on Craask. Verify & observe Camera LED blinking behavior.

Change-Id: I78ed5efe1e2c071d817c1e0455271886e89e63c7
Signed-off-by: Jimmy Su <jimmy.su@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74728
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-01 14:40:45 +00:00
Werner Zeh 572004879f mb/siemens/mc_ehl: Remove wrong comment regarding spd.bin
The support for a spd.bin from CBFS was removed for all mc_ehl boards in
commit 833bb448c5 (mb/siemens/mc_ehl: Remove spd.bin from CBFS).
There is still a remaining comment in romstage_fsp_params.c referring to
the removed capability. This fix removes the spd.bin related part of the
comment to stay consistent with the code.

Change-Id: I669ee1c33d1d1c47764640982f71129195e63f14
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74801
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-05-01 14:40:03 +00:00
Arthur Heymans 2bc4a62965 vendorcode/mediatek/mt8192: Cast enum types
Clang warns about using the wrong enum types as arguments.

Change-Id: Idfebf2f6deec7d531cbda6667384b5f591bdc3cb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74546
Reviewed-by: Xixi Chen <xixi.chen@mediatek.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
2023-05-01 14:38:43 +00:00
Arthur Heymans b1c1996b1c mb/prodrive/atlas: Enable/disable sleep states based on EC
With the profile ATLAS_PROF_REALTIME_PERFORMANCE it is desired to not
have the option to be able to enter sleep. The reason is that Microsoft
Windows goes to sleep after 30min of inactivity by default.

TEST: See that Microsoft Windows 11 has no 'Sleep' option in the start
menu.

Change-Id: I424db7e712a705c628aa3a10a486d3313404987a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74421
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-01 06:38:45 +00:00
Arthur Heymans 0eb5974def acpigen: Add a runtime method to override exposed _Sx sleep states
This allows mainboards to override available sleep states at runtime.
This is done by adding a IntObj in SSDT that DSDT consumes to override
the available _Sx states.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ic21830c1ef9c183b1e3005cc1f8b7daf7e9ea998
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74762
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-01 06:38:36 +00:00
Sean Rhodes cd48c7ece3 mb/starlabs/starbook: Let coreboot configure ASPM
FSP is fractionally faster at configuring ASPM (1,118,688 vs 1,122,205)
but coreboot's configuration results in lower power consumption of
approximately 0.5W when idling - the reason why is unknown.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib15eaede956f0aa55118d093fdff0fd9487df250
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74520
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-29 19:45:06 +00:00
Kyösti Mälkki 5fc0afbc17 asus/p2b, emu/qemu-i440fx: Use acpigen_write_processor_device()
FADT duty_width/duty_offset fields, together with P_CNT (previously
P_BLK) IO address are provided with _PTC entry.

FADT p_lvl2/3_lat fields had values that disabled C2/C3 state
transitions so _CST entries are not required.

Change-Id: I629cd0793f6a64e955e197400efaa7d9d898e775
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-29 02:36:27 +00:00
Tarun Tuli d1211cb3de mb/google/poppy/variant/nami - Ensure power cycle of FPMCU on startup
Add functionality to ensure that the FPMCU is power cycled long enough
on boot to ensure proper reset.

This solution relies solely on coreboot to sequence the power and reset
signals appropriately (150ms on boot).

-Confirmed power is off for 150ms on boot.
-Confirmed RCC_CSR of FPMCU indicates power cycle occurred.
-Confirmed reset is de-asserted approx 3ms after power application
(target >2.5ms)


BUG=b:245954151
TEST=Confirmed FPMCU is still functional on Nami and timings are
as expected.

Change-Id: I0a23bda96bc2ea90be81a2310605f75c55c0a839
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-29 02:32:02 +00:00
Tarun Tuli 39c279acf8 mb/google/poppy: Add support for variant SKU romstage GPIO configs
Add functionality that allows a variant SKU to have a specific set of
GPIO configs in romstage (modeled after the existing one in
ramstage)


BUG=b:245954151
TEST=builds

Change-Id: I593a23951306908fadc00e6bc8d9d310f09c5e4b
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-29 02:31:36 +00:00
Kapil Porwal 337f38ae09 mb/google/rex/variants/screebo: Generate RAM IDs
Generate RAM IDs for -
MT62F512M32D2DR-031 WT:B (LP5)
H9JCNNNBK3MLYR-N6E (LP5)
MT62F1G32D2DS-026 WT:B(LP5x)
H58G56BK7BX068 (LP5X)

BUG=b:276814951
TEST=Run part_id_gen tool without any errors

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I0fb2e488c06ed74d3fd493e5ca0ab89a825a9349
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74802
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-29 02:30:32 +00:00
Kyösti Mälkki 02a1901091 sb,soc/amd,intel: Drop include <cpu/x86/smm.h>
I forgot to remove these in commit 0fe36db154eb ("ACPI: Make FADT
entries for SMI architectural").

Change-Id: Ib1bc1dad6053ddb0454d4510917fd2bcf0901f35
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74811
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-29 01:21:23 +00:00
Kyösti Mälkki 240baa31e8 ACPI: Make FADT entries for RTC/CMOS architectural
For AMD, replace name RTC_ALT_CENTURY with RTC_CLK_ALTCENTURY
that points to same offset. Since the century field inside
RTC falls within the NVRAM space, and could interfere with
OPTION_TABLE, it is now guarded with config USE_PC_CMOS_ALTCENTURY.

There were no reference for the use of offset 0x48 for century.

Change-Id: I965a83dc8daaa02ad0935bdde5ca50110adb014a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74601
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-29 01:20:54 +00:00
Fred Reitberger 097f540460 soc/amd/phoenix: Populate type 0x63 entry with right MRC Cache
On boards with RECOVERY_MRC_CACHE FMAP section, populate type 0x63 BIOS
directory entry in RO with that section. If the RECOVERY_MRC_CACHE
section is not present, then fall back to RW_MRC_CACHE.

BUG=b:270569389

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ic5ac87685eaa5fec717e3efa4df7af511b4ce8aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-04-28 22:11:35 +00:00
Felix Held 932cd22487 soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct PCI MMIO BAR window
This ports back commit d75ee46d3c ("soc/amd/picasso/acpi: Change PCI0
BAR window") to Stoneyridge so that the correct end of the non-fixed
MMIO region gets reported in PCI0's _CRS method.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I19153947cbb1b1b684291765eb1902caac65b9ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-04-28 20:14:02 +00:00
Felix Held 0de53be394 soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct number of PCI buses
This ports commit 8c28e51a16 ("soc/amd/picasso: fix host bridge bus
numbers") back to Stoneyridge so that the correct number of PCI buses
gets reported from PCI0's _CRS method. The MCFG ACPI table already had
the correct last bus number.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I40121ab0e0438281192b6a0bec8dbecdc1749379
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-04-28 20:13:47 +00:00
Sean Rhodes 4c98dfb4e3 mb/starlabs/starbook/adl: Correct the number of NID entries
The number of NID entries was too high for the Realtek
and Intel sound cards, preventing the verb table from
loading. Now the values are correct; it loads as intended.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I79825313a4801c120a0a2a321cbabab7c728aa71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-04-28 15:38:00 +00:00
Sean Rhodes c45cfadf36 ec/starlabs/merlin: Change the fallback value for fn_ctrl_swap
Change the fallback value of the `fn_ctrl_swap` option to 0, which
is disabled.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9fcbb497f14ed0c97ff05c6c01a3929522786781
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-28 15:30:25 +00:00
Sean Rhodes 7e300f51ac ec/starlabs/merlin/acpi: Don't attempt to change EC values
The EC will constantly update the battery variables approximately
every 60 seconds; they should be used unmodified, rather than
trying to change them.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3cff0ac6a322018cbca33b5f90dd62b3475da25c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-28 15:29:51 +00:00
Sean Rhodes 820a2e175c mb/starlabs/starbook/adl: Correct port for Hot Plug
Commit 5103b87a4d ("mb/starlabs/starbook/adl: Add an option to
enable Hot Plug") introduced an option to enable Hot Plug for the
SSD. The port was set to 4 (RP5) which is the wireless card. Change
this to 8 (RP9) which is the SSD.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I884f4997d73e31bd422477952466f168afad66a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74738
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-28 15:28:51 +00:00
Fred Reitberger a194e6252f amdfwtool: Increase MAX_PSP_ENTRIES
The MAX_PSP_ENTRIES constant reserves space for the psp directory table
entries. This table is aligned to 4K and the next binary is also aligned
to 4K. The number of psp directory entries on Birman exceeds the
previous limit, so increase it to the maximum that will fit in a 4K
block.

TEST=timeless builds for Birman unchanged

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I297edc9cccffde0ad1ce7461b375542f9f2f7c23
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bao Zheng <fishbaozi@gmail.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-04-28 15:12:47 +00:00
Christian Walter bf0b87d813 soc/intel/common/block/pmc: Sort Kconfig in alphabetical order
Change-Id: I7392ede4226a940896c805fc0b0bc0dd615a964c
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74810
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-28 13:38:59 +00:00
Jan Samek edda0f94e5 treewide: Add missing include guards to chip.h
Some of the chip.h files in the tree are missing the include guards.

This patch adds them in order to avoid potential redefinions of symbols
contained in these headers, when they are included multiple times in
static.c generated by sconfig.

Change-Id: I550a514e72a8dd4db602e7ceffccd81aa36446e3
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-28 13:38:33 +00:00
Kun Liu 8ba2ecf2b4 mb/google/rex/var/screebo: Add initial setup for gpio config
add the initial gpio configuration for screebo initial variant

BUG=b:276814951
TEST=emerge-rex coreboot

Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Change-Id: Ib96e03f47bc1d6e5628ae459c3e1eb4dc18849c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74475
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-28 09:59:23 +00:00
Hsuan Ting Chen 26a9555073 vga: Change the arguments of vga_write_text to support extended ASCII
VGA defined the extended ASCII set based on CP437, but the function
vga_write_text() accepts a signed char array.

This will cause unnecessary confusion that if we want to print u with
umlaut (code=129 in CP437), we need to explicitly cast it to -127 in
signed char.

Since we still want to leverage the built-in string utilities
which only accepts const char*, we still need to cast it to signed char
while processing, and cast it back to unsigned once we write into the
frame buffer.

BRANCH=brya
BUG=b:264666392
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Change-Id: If555bbc05f40ce3f02339c0468afff6dda8b7ded
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-04-28 09:39:06 +00:00
John Su 533f1e78d6 mb/google/skyrim: Enable SPL fusing on Markarth
Because SPL fuse needs to be set before the FW lock. So enable
Markarth project to send the fuse SPL (security patch level)
command to the PSP.

BUG=b:279499511
BRANCH=none
TEST=FW_NAME="Markarth" emerge-skyrim coreboot chromeos-bootimage
Then get "PSP: SPL Fusing Update Requested." in the firmware log.

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I8fbbd89d11b1bdb2c95c761955c10bedb366fd70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74753
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-28 00:20:38 +00:00
Julius Werner d69ccaf027 arch/x86: Disable walkcbfs_asm code when CONFIG_CBFS_VERIFICATION is set
walkcbfs_asm is a simple CBFS implementation in assembly to find a file
on a system with memory-mapped SPI flash. It seems to be mostly unused
nowadays and is only still called for early microcode loading on some
old systems (e.g. FSP 1.1 and older).

Using this implementation with CONFIG_CBFS_VERIFICATION is unsafe
because it does not verify the hashes the way the normal CBFS code does.
Therefore, to avoid potential security vulnerabilities from creeping in,
this patch makes sure the code cannot be compiled in when
CBFS_VERIFICATION is active. That means it won't be supported on the old
boards using this for microcode loading.

Ideally CONFIG_CBFS_VERIFICATION should have a `depends on` to make this
dependency more obvious in menuconfig, but the configs actually using
this code are not easy to untangle (e.g. CONFIG_MICROCODE_UPDATE_PRE_RAM
is just set everywhere by default although only very few boards are
really using it, and a lot of different old Intel CPU models are linking
in src/cpu/intel/car/non-evict/cache_as_ram.S without being united under
a single Kconfig so that's not easy to change). To keep things simple,
this patch will just prevent the code from being built and result in a
linker error if a bad combination of Kconfigs is used together. Later
patches can clean up the Kconfigs to better wrap that dependency if the
affected boards are still of enough interest to be worth that effort.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I614a1b05881aa7c1539a7f7f296855ff708db56c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-04-27 23:18:57 +00:00
Rex Chou 5a802b32ea mb/google/skyrim/var/winterhold: Add support for K3KL6L60GM-MGCT
Update Samsung 4G K3KL6L60GM-MGCT support

BRANCH=None
BUG=b:243337816
TEST=emerge-skyrim coreboot

Change-Id: I89b9798c16635a32dff12f1c0b65737d3c16cd59
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-04-27 20:45:55 +00:00
Maximilian Brune 2c895aaac3 util/ifdtool/ifdtool.c: Fix default FMAP generation
According to SPI programming guide, a region limit of 0 as well as
region base of 7FFFh indicates an unused/reserved region.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I790d7f5631ecef3043b2c17c41430dc4fd854f72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-04-27 20:45:14 +00:00
Subrata Banik 1f58b6a2a5 mb/google/rex: Add USB4 ANX7452 Rev 2 to USB_DB FW_CONFIG
This patch adds new USB_DB FW_CONFIG to enable support for USB4 ANX7452
Rev 2.

BUG=b:279647370
TEST=Able to build and boot google/rex with Proto 2 SKU

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I878b591e5919d05d3c5fc2eefdeb492e95d4f7b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-27 15:34:10 +00:00
Chris Wang 544e2aa215 mb/google/skyrim/var/winterhold: adjust the eDP panel power sequence
Set edp_panel_t9_ms to 8ms which means it  will delay 8ms
between backlight off and vary backlight off.

BUG=b:271704149
BRANCH=Skyrim
TEST=Build; Verify the UPD was passed to system integrated table;

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I952d05b18e29cf30256f43562a5052007c5c6268
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74790
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-27 14:40:48 +00:00
Chris Wang f927026536 soc/amd/mendocino: update FSP parameters for eDP power sequence adjustment
Add UPD parameter for eDP power sequence adjustment.

The edp_panel_t9_ms parameter is set for bloff to varybloff.

BUG=b:271704149
BRANCH=Skyrim
TEST=Build; Verify the UPD was pass to system integrated table.

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Id651c9cc4d6f4e27f6c78ca10ca12936d66ef43b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74789
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-27 14:40:38 +00:00
Chris Wang 78790c872c vc/amd/fsp/mendocino/FspmUpd: Add UPD to set eDP panel T9 vaule
Add UPD edp_panel_t9_ms for eDP panel sequence adjustment.

BUG=b:271704149
BRANCH=Skyrim
Test=Build/Boot to ChromeOS

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Idc1a212e9c203584a6497fd6cbd3f995eeb030f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74788
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-27 14:40:27 +00:00
Chris Wang c2059fa72a soc/amd/mendocino: rename pwr_on_vary_bl_to_blon to edp_panel_t8_ms
Rename the UPD pwr_on_vary_bl_to_blon to edp_panel_t8_ms to
match the eDP sequence timing in milliseconds.

BUG=b:271704149
BRANCH=Skyrim
Test=Build/Boot to ChromeOS

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Iecdfe47cd9142d8a1ddeee0ec988d37b2a11028e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74787
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-27 14:40:17 +00:00
Felix Held 31e5133b63 arch/x86/include/pci_io_cfg: introduce PCI_IO_CONFIG_[INDEX,DATA] define
Instead of having multiple instances of the same magic numbers in the
code, introduce and use the PCI_IO_CONFIG_INDEX and PCI_IO_CONFIG_DATA
definitions.

TEST=Timeless build for Mandolin results in identical image.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If6f6f058180cf36cae7921ce3c7aaf1a0c75c7b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-27 13:45:11 +00:00
Christian Walter b3076e5566 configs/builder: add default config for Intel Archer City CRB
which is based on Intel Sapphire Rapids Scalable Processor chipset
which was product launched on Jan. 10 2023.

The site-local/* files are Intel binaries that are not published yet
but coreboot build validation system would skip these binaries when
they are in "site-local" directory.
Please make sure you have the correct Intel binaries for your AC CRB
and place them to the right location accordingly.

CONFIG_PAYLOAD_FILE="site-local/archercity/linuxboot_bzImage" is
LinuxBoot payload, there are several ways to build it, one way is to
build it from the x86_64 qemu example from osf-builder:
git clone https://github.com/linuxboot/osf-builder
cd examples/qemu; make kernel

commit ae90fc0bb (soc/intel/xeon_sp/spr: Default to X2APIC support)
would enable DEFAULT_X2APIC_RUNTIME, your LinuxBoot kernel needs to
enable X2APIC support, otherwise need to set CONFIG_XAPIC_ONLY=y in
your defconfig.

Change-Id: I15aefc3edb2d22fc00d854850e948fe2048a992e
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71969
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-27 13:43:59 +00:00
Tony Huang 0f8c03b593 mb/google/nissa/var/yavilla: Add elan touchscreen support
Update devicetree to support ELAN I2C generic touchscreen.

BUG=b:273791621
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: I2779c2930d89ff42233f9b20bd8abdf6dc00c0e0
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74776
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
2023-04-27 13:02:57 +00:00