Commit Graph

52841 Commits

Author SHA1 Message Date
Kyösti Mälkki 4aa8593ecc sb/intel/i82801ix: Drop __ASSEMBLER__ guard
No longer needed, this was used with old SMM relocate code.

Change-Id: I7c913e10eb965419c7d2ddede744f8140a5b7976
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-07 07:14:30 +00:00
Kyösti Mälkki 7fddb6b996 sb/intel: Drop redundant defines
Change-Id: I7655de5a8fcd5ac5c820938059bbb8b1ad877db7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-07 07:14:12 +00:00
Kyösti Mälkki 8647153222 sb/intel/common: Fix corner-case with Kconfig
To select COMMON_SMM should not imply COMMON_PMBASE, it's
really a depencency. Select them both explicitly for i82801dx.

Change-Id: I387ade9cfd38b6555ed9e37c1b9178a6da2d7260
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-07 07:13:57 +00:00
Kyösti Mälkki 47af801133 mb/intel/kblrvp: Clean smihandler
Change-Id: I0ada381883aa65d36434486dcce6b2331599e5c3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-06 06:06:52 +00:00
Kyösti Mälkki 129e45eb99 mb/google/jecht: Clean smihandler
Change-Id: I47ec05aa87e4e7c02b19817b2f703eca492008e6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-06 06:06:41 +00:00
Subrata Banik 792ce81973 soc/intel: Do CSE sync in romstage, unless ramstage chooses otherwise
This patch makes CSE sync in romstage default enabled unless ramstage
config (SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE) chooses to override it.

TEST=Able to build google/marasov with this change where CSE sync is
performed early inside romstage.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3f5017fbcf917201eaf8233089050bd31c3d1917
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-05-06 05:36:44 +00:00
Kun Liu 199728b4d2 mb/google/rex/var/screebo: Add DDR DQ map config
Add DDR DQ map config for screebo

BUG=b:276814951,b:272218757
TEST=emerge-rex coreboot

Change-Id: I993ae4024689b9cedbea247689a760bd83cd0d45
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74961
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-05-06 00:40:23 +00:00
Jon Murphy b4a47a26b9 mb/google/myst: Add variant makefile
Add variant makefile to support including the memory folder for Myst.

BUG=b:273383819
TEST=Builds in chromium with blobs

Change-Id: I03b0cd91dd66f357b15522da36f5118867b6b14c
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74964
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-05 19:53:55 +00:00
Matt DeVillier 13eb237b45 mb/google/fizz: Override SMBIOS product name based on OEM ID
Use the OEM ID from CBI to determine the correct OEM board name.
ID mapping taken from ChromeEC source, branch firmware-fizz-10139.B.

TEST=build/boot multiple fizz variants, check that board name reported
correctly in SMBIOS tables.

Change-Id: I06251974ac73570b911920ed566a175e8e733710
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-05-05 15:39:20 +00:00
Matt DeVillier 1a3e6381d3 mb/google/poppy/var/nami: Override SMBIOS product name
Override SMBIOS product name with sub-variant name based on board SKU.

TEST=build/boot multiple nami variants, verify SMBIOS product name
reports correctly.

Change-Id: I2125bfb6436469405378f9c983d7cfcb2f85f916
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-05-05 15:39:09 +00:00
Matt DeVillier 1db8c57470 vc/google: Decouple DSM_CALIB from CHROMEOS
DSM (Dynamic Speaker Management) uses calibration parameters stored in
a VPD (Vital Product Data) FMAP region to configure the audio output
via an ACPI _DSD table. This has no dependency on a ChromeOS, and can
be used by Linux/Windows drivers if appropriately configured.

Remove the dependency of DSM_CALIB (and the calibration file) on
CHROMEOS and replace it with VPD, so that non-CHROMEOS builds
can utilize this feature as well. Move files from underneath
vc/google/chromeos to underscore the point.

TEST=build/boot google/nightfury, dump ACPI, verify DSM calibraton
parameters present in _DSD table.

Change-Id: I643b3581bcc662befc9e30736dae806f94b055af
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74812
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-05-05 15:38:53 +00:00
Kyösti Mälkki b78e462037 Convert literal uses of CONFIG_MAINBOARD_{VENDOR,PART_NUMBER}
Only expand these strings in lib/identity.o.

Change-Id: I8732bbeff8cf8a757bf32fdb615b1d0f97584585
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-05 13:56:34 +00:00
Angel Pons f574c3305a soc/amd/cmn/acpi/sleepstates.asl: Align with sb/amd
Adjust a few things so that the sleepstates.asl file is the same for
sb/amd and soc/amd. These adjustments don't have a functional impact.

Change-Id: I0cc9462b326cdc371ffdbf5759d8adc42456ce74
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74960
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-05 13:22:17 +00:00
Angel Pons 3321bb3eb3 {sb,soc}/amd/cmn/acpi/sleepstates.asl: Hook up configs
Commit cbc5d3f34b ("soc/intel: Don't
report _S1 state when unsupported") added the `ACPI_S1_NOT_SUPPORTED`
option and commit 0eb5974def ("acpigen:
Add a runtime method to override exposed _Sx sleep states") added a
mechanism to override the enabled sleep states at runtime. However,
these were only hooked up to Intel sleepstates. so the options would
not have any effect on AMD platforms.

Apply the changes from these two commits to AMD sleepstates so that
both options can be used on AMD platforms as well.

Change-Id: I7d5ef2361e36659ac5c6f54b2c236d48713a07c9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74959
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-05 13:21:43 +00:00
Maximilian Brune 27900ea9f8 src/soc/intel: Document meaning of variables
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Iaf88f34cedd09e2461bb05050392e178ec84d5d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-05 12:36:29 +00:00
Lean Sheng Tan 03bf97ad16 MAINTAINERS: Add Benjamin, Matt, Sean, Sheng for EDK2 payload
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I914a7f665e246e7490c127078a5a9795c8334d92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-05-05 12:19:59 +00:00
Frank Chu 3cb09273c1 mb/google/brya/var/marasov: Disable Tccold Handshake
The patch disables Tccold Handshake to prevent possible display
flicker issue for marasov board. Please refer to Intel doc#723158
for more information.

BUG=b:279117758
BRANCH=firmware-brya-14505.B
TEST=Boot to OS on marasov.

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I286e88e5bec240d64e6c801648f6483ad2b0939c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74931
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-05 12:18:52 +00:00
Jonathon Hall 2606acfd4b mb/purism/librem_cnl: Configure SuperIO for Librem Mini v1/v2
Configure the SuperIO and logical devices in the device tree.  This
overrides the power-on default state.

UART1 was already enabled, and if ENABLE_EC_UART1 was selected in
Kconfig, the LPC UART1 I/O range was also already enabled.

The RTC/BRAM interface was enabled (and the BRAM1 base was 0x360 by
default), but the LPC I/O range was not opened previously.  Now it is
open and BRAM bank 1 is accessible.

Mouse/Keyboard are not wired to anything on this board and are now
disabled.

UART2, SMFI, power channel 1, and power channel 2 were enabled
previously, but their LPC I/O ranges were not opened and they were not
accessible to the OS.  Fan control is performed by the EC on this board
so there is no change.

SWUC and power channels 3-5 were disabled by default, no change.

Change-Id: I58a5a427737f4a2caa64326c110eb53ec00b347d
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-05-05 05:14:00 +00:00
Tarun Tuli 1800ad5498 mb/google/poppy/variant/nami - Move FPMCU IO setup back to ramstage
variant_board_sku() is missing dependences in order to work correctly
in romstage.  Rather than more intrusive rework as its use is limited,
move the FPMCU early GPIO init back to ramstage.  We still meet
sufficient power off time to fully power cycle the MCU.

BUG=b:245954151
TEST=Confirmed FPMCU is still functional on Nami and FP tests all pass
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: Ia428ec5aec1a0438e91bc48903bda043046b740e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74695
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-05 05:13:43 +00:00
Matt DeVillier 9e2b29d87d mb/google/octopus: Disable unused devices in devicetree
The image processing unit/GMM and xDCI are not used on octopus boards;
additionally, enabling xDCI can cause some problems with USB ports in
both booting from the payload and in the OS.

Change-Id: I1ee99b5c45881a4cf3624bf487bc9d83fb3d07a1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-05 05:12:27 +00:00
Felix Singer 51d8b25984 soc/intel/spr: Fix copy paste issue in error messages
The commit a0b199c6b4 ("soc/intel/xeon_sp/spr: Add soc
set_cmos_mrc_cold_boot_flag") introduced a copy-paste issue in two error
messages. The error messages should mention the Intel platform SPR
instead of CPX. Fix that.

Change-Id: I4de61ec2cf9fbd98263a7a7a588938d548148656
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74956
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-05 00:12:07 +00:00
Matt DeVillier 1d8763806c mb/google/puff: Add SOF chip driver
Add SOF chip driver entries for all variants, so that the correct audio
config is passed to the OS drivers.

TEST=build, boot Windows on wyvern variant, verify headphone output
and microphone functional under Windows using coolstar's SOF drivers.

Change-Id: I421c070eac321c2fc160b8f26868bcb1ec13001e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74815
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-05-04 21:03:15 +00:00
Matt DeVillier 8e883c11b4 mb/google/volteer: Add SOF chip driver
Add SOF chip driver entries for all variants, so that the correct audio
config is passed to the OS drivers.

TEST=build, boot Windows on several volteer variants, verify audio
functional under Windows using coolstar's SOF drivers.

Change-Id: I62a96149cec9eeb7b2da8a2337083969a1b0fce0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74816
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-05-04 21:03:02 +00:00
Matt DeVillier 3f3dc504e9 mb/google/brya: Add SOF chip driver
Add SOF chip driver entries for all variants, so that the correct audio
config is passed to the OS drivers.

TEST=build, boot Windows on banshee and osiris variants, verify audio
functional under Windows using coolstar's SOF drivers.

Change-Id: I12614b85f9779cc40d83a9c868cc46b110f26af6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74817
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-05-04 21:02:44 +00:00
Matt DeVillier 35470e1604 mb/google/dedede: Add SOF chip driver
Add all SOF chip drivers to baseboard and use FW_CONFIG to determine
the correct option, to ensure the correct audio config is passed to the
SOF OS drivers.

TEST=build, boot Windows on several dedede variants, verify audio
functional under Windows using coolstar's SOF drivers.

Change-Id: I9452b11af614d8727aa8dd448e37f7a06faa450d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74818
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-05-04 21:02:34 +00:00
Felix Held 1591f8437c soc/amd/common/block/lpc/lpc: simplify index handling in read resources
Now that we don't need to find a specific resource in the set resources
function any more, there's no need to use hard-coded indices for the
fixed resources. Instead use an index variable that gets incremented
after each fixed resource got added. The index now starts at 0 instead
of at 1, but now the only requirement is that those indices are unique.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ida5f1f001c622da2e31474b62832782f5f303a32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74849
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-05-04 19:06:09 +00:00
Mario Scheithauer b70b980dda mb/siemens/mc_ehl: Remove subdir 'spd' from Makefile
Since commit 833bb448c5 ("mb/siemens/mc_ehl: Remove spd.bin from
CBFS"), the subdir 'spd' is no longer necessary.

Change-Id: Ibaf44e3181b2167aa83cffcc59835196e4cb5cdb
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-05-04 13:41:25 +00:00
Jonathon Hall cc991c58cf mb/purism/librem_cnl: Remove unneeded explicit PNP enable for UART
Remove explicit PNP 6e.1 configuration for UART.  This had no effect,
the SuperIO is actually on I/O port 2e.  Enabling the 8250IO driver is
sufficient to use the UART, the UART device is enabled by default.

Test: Build Mini v2 with and without CONFIG_ENABLE_EC_UART1, boot and
check output on serial.

Change-Id: Idbb39c81cadd633f4718f0682d231dc578d20325
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74362
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-03 21:51:01 +00:00
Sean Rhodes 543bba8f8f ec/starlabs/merlin: Change the fallback value for fn_ctrl_swap
Change the fallback value of the `fn_ctrl_swap` option to 0, which
is disabled.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I76329ec59ba630c987a122bffb8045150facdf08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-05-03 21:50:36 +00:00
Felix Held 6a41b99a4a soc/amd/common/block/lpc/lpc: drop custom lpc_set_resources
Drop the custom lpc_set_resources implementation that does some register
access that has no effect and then calls pci_dev_set_resources and use
pci_dev_set_resources for set_resources in amd_lpc_ops instead.

The SPI controller's base address got configured early in boot in the
lpc_set_spibase call and the enable bits got set early in boot in the
lpc_enable_spi_rom call.

TEST=The contents of the SPI_BASE_ADDRESS_REGISTER at the beginning and
at the end of the call stay the same, so it's simply a no-op.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7a5e3e00b2e38eeb3e9dae6d6c83d11ef925ce22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-03 16:17:17 +00:00
Felix Held bd9db8d9e4 soc/amd/common/block/lpc/lpc: report HPET MMIO
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I77471d464dddffc63bb2f005fef3a33c84ff5f5e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-03 16:17:03 +00:00
Felix Held 4d70daf305 soc/amd/common/block/lpc/lpc: use mmio_range to report FCH IOAPIC MMIO
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I813a27e392a842188dc474018f82e10309783260
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-03 16:16:57 +00:00
Felix Held 19d1c16c32 soc/amd/common/block/lpc/lpc: report eSPI MMIO
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I63fb70da3e9ded6c05354f94ee69bc6dd04e58f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-03 16:15:53 +00:00
Felix Held 026caf5def soc/amd/common/block/lpc/lpc: increase size of SPI BAR to 4kByte
The memory map granularity for those devices is 4kByte.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8806128bdce8988f5cd7c8fa8a342fdb01eb7f42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-03 16:15:45 +00:00
Felix Held 662d7af70b soc/amd/common/block/lpc/lpc: report mapped SPI flash as MMIO range
Since the 16MByte of memory-mapped SPI flash region right below the 4GB
boundary is both a fixed region and isn't decoded on a device below the
LPC device, but assumed to be decoded by the LPC device itself, it
shouldn't be reported as a subtractive resource, but as an MMIO resource
instead.

TEST=On mandolin the 16MByte MMIO-mapped SPI flash now show up as a
reserved region in the e820 memory map which wasn't the case before:

13. 00000000ff000000-00000000ffffffff: RESERVED

The Linux kernel doesn't show any new or possibly related errors.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: Ib52df2b2d79a1e6213c3499984a5a1e0e25c058a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-03 16:15:38 +00:00
Jamie Chen 22b226724e mb/google/brya/var/omnigul: Adjust I2C3 and I2C5 Waveform meet to SPEC
Tuning i2c frequency ,timing ,Waveform meet to SPEC
i2c frequency :
I2C0=>399.8khz / Setup Time:1765ns / Hold Time:82.35ns.
I2C1=>390.4khz / Setup Time:1.788us / Hold Time:70.58ns.
I2C3=>308.7khz / Setup Time:1.482us / Hold Time:0.4us.
I2C5=>390.8khz / Setup Time:1.218us / Hold Time:0.405us.

BUG=b:275061994
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot,
EE check OK with test FW and TP function is normal.

Change-Id: I5b77cd3fd3ff00804f1b8dd5828dc831a9732566
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74880
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2023-05-03 16:08:12 +00:00
Sridhar Siricilla 50931f8ea0 mainboard/intel/mtlrvp: Refactor the kconfig selections
The patch orders MTL RVP board Kconfigs alphabetically.

TEST=Build the code for mtlrvp

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ib8557aab2848a384fba5203e5f3d62407b2566ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2023-05-03 16:07:53 +00:00
Kyösti Mälkki 0d1734eea4 Drop many cases of CONFIG_MAINBOARD_PART_NUMBER
We have largely dropped from filling in mainboard_ops.name
as unnecessary. A common place should be decided where or if
this information is added in the console log.

Change-Id: I917222922560c6273b4be91cd7d99ce2ff8e4231
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-03 16:07:31 +00:00
Matt DeVillier 10e928319d mb/google/hatch: Add SOF chip driver
Add SOF chip driver entries for all variants, so that the correct audio
config is passed to the OS drivers.

TEST=build, boot Windows on several hatch variants, verify audio
functional under Windows using coolstar's SOF drivers.

Change-Id: Ie791fa873fc7bbab84644f5ea5743bdcdc124908
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-05-03 16:06:41 +00:00
Matt DeVillier 3a4ac3a85e drivers/sof: Add new driver to generate ACPI _DSD table
Add a new chip driver for boards which use SOF (Sound Open Firmware)
OS drivers, which will be attached to the HDAS device and generate
entries in an ACPI _DSD table for the OS driver to use. This will allow
the OS drivers to easily determine the correct topology for the speaker
and jack amplifiers and correct microphone configuration.

TEST=tested with rest of patch train

Change-Id: Ie0431b2002287f35245cbf959828e931d7f375b2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-05-03 16:06:32 +00:00
Martin Roth ab05964b91 soc/amd/phoenix: Add default vBIOS ID and location
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Iadc32f4dbf8bd48d8666a213d7b5f3ba42175a90
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-03 16:06:13 +00:00
Matt DeVillier 5f662e9f75 mb/google/reef: Disable unused devices in devicetrees
The image processing unit (Iunit) and SoC UARTS are not used on any
reef boards.

Change-Id: Iacdf93b4952cbc63fc465f07d440463106527b8d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-03 16:05:46 +00:00
Matt DeVillier d095fd8cf1 mb/google/reef: Disable Intel Trace Hub PCI device
It's not particularly useful to end users, and shows up as an unknown
PCI device under Windows Device Manager.

TEST=build reef, boot Windows, verify unknown PCI device no longer
present in Device Manager.

Change-Id: Ie8ec46e2e07b6635bfe9766812ce08b866c71d66
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-03 16:05:40 +00:00
Karthikeyan Ramasubramanian 8d3ca33d15 mb/google/myst: Inject SPD binaries to APCB
Add rules to inject the variant specific SPD binaries into APCB.

BUG=b:273383819
TEST=Build Myst BIOS image. Currently no APCB is present. So no SPD is
injected into APCB.

Change-Id: Ic511cdc4fe0989c9abc0cd0531cc0cae40f8dc34
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74746
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-05-02 21:43:52 +00:00
Karthikeyan Ramasubramanian 7803190d9e mb/google/myst: Add initial memory configuration
Generate the RAM Strap IDs based on the initial memory configuration.

BUG=b:272746814
TEST=Build Myst BIOS image.

Change-Id: I8a4fe9a41f101ac10391756f1b815220c8b98612
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-05-02 21:43:42 +00:00
Joey Peng ea2a38be32 soc/intel/alderlake: Disable C1E on RPL CPUs
Since disabling C1E could improve acoustic noise for RPL, add judgement
in SOC code to disable C1E on RPL CPUs and enabling it on ADL CPUs .

BUG=b:278654939
TEST:emerge-brya coreboot

Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Ic2d2d5d6075de25141c1d08ec18838731c63a342
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-05-02 19:03:38 +00:00
Elyes Haouas 9718e2616a Kconfig: Group dependency on X86EMU_DEBUG
Change-Id: I6b53536a3d673350fa1b46891da2766b0bc149e8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-05-02 18:49:50 +00:00
Sean Rhodes 14e80fd9c5 payloads/edk2: Remove ABOVE_4G_MEMORY option
Remove the ABOVE_4G_MEMORY option as the option was removed in edk2
in commit dc5f2905ebfdf68ae28ce1081d435af0f8641dd9 (UefiPayloadPkg:
Always build MemoryTypeInformation HOB for DXE GCD
- https://github.com/tianocore/edk2/pull/4231).

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I8d5ee79ef3f7ecfcd1463c612aad2e3d629df22a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74336
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-05-02 13:47:11 +00:00
Matt DeVillier a38e2484ac payloads/edk2: Add Kconfig to enable UEFI Secure Boot support
Now that MrChromebox's default edk2 branch supports Secure Boot, add a
Kconfig to enable it, and do so by default when MrChromebox's branch
is used and SMMSTORE_V2 is enabled (which is a prerequisite).

TEST=build/boot google boards link, panther, lulu,reef, ampton, akemi,
and banshee, verify Secure Boot options available in payload, Secure
Boot status reported properly by Linux/Windows.

Change-Id: I4be58c3315cabe08729d717c59203fdc6a3e2958
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74869
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-02 13:46:59 +00:00
Matt DeVillier b8fd41b441 payloads/edk2: Update default branch for MrChromebox repo to 2023-04
Update the default branch used for MrChromebox's edk2 fork from 2022-07
to 2023-04. This updated branch has been rebased on the latest upstream
stable tag (edk2-stable202302), and adds support for UEFI Secure Boot and
TPM 1.2/2.0 management (though it does not currently support Google
CR50/Ti50 TPMs).

TEST=build/boot google boards link, panther, lulu,reef, ampton, akemi,
and banshee with edk2 payload selected.

Change-Id: I096eaa4e065db731a70ba238ba5a3bb49e5db867
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74868
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-02 13:46:51 +00:00