Commit Graph

52841 Commits

Author SHA1 Message Date
Zheng Bao 9203f5ee85 mb/amd/majolica: Add default setting PSP_INIT_ESPI
The board needs this setting to boot.

Change-Id: I7f507c2478b63daf891430e95b008747b9b95a51
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-05-22 12:50:01 +00:00
Karthikeyan Ramasubramanian aa86e5f006 soc/amd/mendocino: Unmap hash table after usage
Earlier the entire SPI ROM is mapped at the start of verstage and then
unmapped at the end of verstage. With CB:74606, this behavior has
changed. So unmap the hash table CBFS file after usage.

BUG=b:240664755
TEST=Build and boot to OS in Skyrim. Perform cold, warm reboots and
suspend/resume cycles for 50 iterations each. Ensured that there is no
impact to boot time.

Change-Id: I5c605f8ba8bbd571b589b3cdf91e9cc71d711c1c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75092
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-22 12:49:27 +00:00
Karthikeyan Ramasubramanian 6f1b03b8f6 soc/amd/common/psp_verstage: Map/unmap boot device on need basis
Currently the SPI ROM is mapped completely when the boot device is
initialized. That mapping remains active throughout the execution time
of PSP verstage. Every 1 MiB of mapped SPI ROM region consumes 1 TLB
Slot in PSP for use during memory mapped or DMA access. With 16 MiB of
mapped SPI ROM + FCH devices + 4 reserved TLB slots, 31 out of 32 total
TLB slots is consumed. This leaves almost no scope for future expansion.
With upcoming programs possibly using 32 MiB SPI ROM, PSP will run out
of TLB slots to support 32 MiB.

Hence instead of mapping the entire SPI ROM upfront, get the SPI ROM SMN
address during the boot device initialization. Update the boot device
region operations to map and unmap the SPI flash with the desired offset
and size using the SVC call. Then anytime a memory mapped SPI ROM access
is performed: map the required area, read the data and immediately unmap
the area. There is no update required when using CCP DMA, since the
concerned SVC call performs mapping and unmapping of the required SPI
flash area implicitly.

With these changes, maximum of 8 slots(size of RO section) might get
used at any point in time during the PSP verstage execution.

BUG=b:240664755
TEST=Build and boot to OS in Skyrim. Perform cold, warm reboots and
suspend/resume cycles for 50 iterations each. Ensured that there is no
impact to boot time.

Change-Id: Icd44ea7b2a366e9269debcab4186d1fc71651db2
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74606
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-22 12:49:06 +00:00
Shelly Chang e17fc5dc0b drivers/ocp/ewl: Add sending Meta's BMC SEL for memory training error
Add sending Meta's BMC SEL for memory training error occurred in EWL
type 3 error.

The detail definition of EWL (Enhanced Warning Log) can be found in the
specification document -- BIOS Data ACPI Table (BDAT) Interface
Specification v4.0 Draft 5:
https://uefi.org/sites/default/files/resources/BDAT%20Specification%20v4.0%20Draft5_0.pdf

Change-Id: I664e9d3da7910b47260881c0df64159c8dbe2dca
Signed-off-by: Shelly Chang <Shelly_Chang@wiwynn.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69147
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-22 12:47:33 +00:00
Tim Crawford 930dbc0d04 mb/system76/rpl: Add Gazelle 18
The Gazelle 18 (gaze18) is a Raptor Lake-H board.

Tested with a custom TianoCore UefiPayloadPkg.

Working:

- PS/2 keyboard
- I2C HID touchpad
- Both DIMM slots
- M.2 NVMe SSD slot
- M.2 SATA SSD slot
- All USB ports
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Internal microphone
- Internal speakers
- Combined headphone + mic 3.5mm audio
- 3.5mm microphone input
- S3 suspend/resume
- Booting Pop!_OS Linux 22.04 with kernel 6.2.6

Not working:

- Discrete/Hybrid graphics

Change-Id: I4599bf12c0f3048f9328f336cc8971400f5fd1a0
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-05-22 12:46:38 +00:00
Karthikeyan Ramasubramanian 2049bb9b2c soc/amd/common/psp_verstage: Always build unsigned PSP verstage
Currently unsigned PSP verstage binary is copied from ELF file only when
required in amdfw*.rom. If a signed PSP verstage binary is supplied
while building amdfw*.rom, then it is dropped. Copy the unsigned PSP
verstage binary always so that it can be used for signing directly from
the CI build infrastructure instead of a locally built binary.

BUG=None
TEST=Build Skyrim BIOS image and ensure that the unsigned PSP verstage
is part of the build artifacts.

Change-Id: If797dcfd20aa2991f3517904ef862406b9b9875c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75334
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-22 12:45:30 +00:00
Leo Chou 4d002f356e mb/google/nissa/var/pujjo: Add WWAN_5G power on sequence
Pujjoteen5 support WWAN 5G device, use variant.c to handle the
power on sequence.

BUG=b:279835626
TEST=Build and check WWAN 5G power on sequence.

Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I7dc72f2c705bcb41745f4bf08bef286773fe8b13
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75327
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-22 12:44:58 +00:00
Tony Huang efe035183a mb/google/nissa/var/yavilla: Config I2C frequency
Measured the I2C frequency meets spec
1. I2C0  (TPM): 976.1 Khz
2. I2C1  (TouchScreen); 394.0 Khz
3. I2C2  (WCAM); 377.9 Khz
4. I2C3  (Audio): 390.0 Khz
5. I2C5  (Touchpad): 389.3 Khz

BUG=b:283374537
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
and check all I2C devices measurement result

Change-Id: If6e3a4a2b1ac642561015a290e6579238c3c2b1b
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
2023-05-22 12:44:38 +00:00
Mark Hasemeyer 4c96747138 mb/google/skyrim: Enable DmaProperty on WLAN device
Set the DmaProperty in the device's _DSD so that the OS can treat the
device as untrusted.

BUG=b:278310256
TEST=cat /sys/bus/pci/devices/<wifi>/untrusted == 1
     iperf3 -c <iperf3-server> -t 60 (No performance regressions seen)

Change-Id: I06369a19afa5b881b26f5c1eb243e2db41a9bb36
Signed-off-by: Mark Hasemeyer <markhas@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75095
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
2023-05-22 12:43:56 +00:00
Sean Rhodes bfe2cd402d soc/intel/common: Add an error for missing ramtop CMOS entry
Show an error if an option table is used, and the ramtop entry is not
defined on a platform that uses it.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie48f0766b29be8e1fb0c1f71c4b2ce6ed20e6207
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-22 12:42:54 +00:00
Krystian Hebel 9ab3a1fe4a util/kconfig: Fix default value getter for integer options
CB:37152 was supposed to be uprev to Linux's kconfig, but it got this
one case wrong, Linux never returned "0" [1]. As a result, when an
option has default value different than 0, and it was changed to 0,
savedefconfig skips saving it. However, during the build from such
defconfig the option is assigned default value.

TEST=Set SEABIOS_DEBUG_LEVEL to 0 and see that savedefconfig writes
it to defconfig file.

[1] 7cf3d73b43

Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Change-Id: I821e45dcec99904fab85f136298cbd0315237ff6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72650
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2023-05-22 12:34:50 +00:00
Martin Roth 050b911141 lib/ubsan.c: Restore Jonas' copyright
During the cleanup of copyright lines, this file was incorrectly changed
to remove the copyright line. It is not originally a part of the
coreboot project, having been pulled in and adapted for use in coreboot.
As such, and with the ISC license specifying that the copyright line
should be maintained, the copyright line has been restored.

See coreboot ticket # 479 for more information.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ia234cebd0a6d49d03e40c5a57cd346a07f3e4b09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-22 12:33:32 +00:00
Michał Żygowski 919cf3db7b mb/msi/ms7d25: Re-enable GpioOverride
Set all GPIOs to their target functions and do not depend on FSP to
configure them. The board support has stabilized and was tested with
many PCIe devices. There is no need to detect CLKREQ signals so we may
hardcode them.

TEST=Boot MSI PRO Z690-A DDR4 to Linux and check if all ASPM and Clock
PM features' state on PCIe root ports are the same before and after
the change.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I01dc83ce23ca27525b8905665da942510f249824
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-22 09:06:46 +00:00
Ruihai Zhou 88acb25a9b mb/google/corsola: Disable backlight before turning on bridge
Disable backlight before turning on bridge, otherwise the bridge will
initialize failed.

Fixes: d5c1e1(mb/google/corsola: Add support for MIPI panel)
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: I7d10bf9e8675b2fb03bfd1e294af66207b9b0620
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75354
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
2023-05-22 08:01:18 +00:00
Simon Zhou 6477d19e64 mb/google/rex/var/screebo: enable fingerprint
BUG=b:278156430
TEST=verify the fingerprint on screebo

Change-Id: I986e470b28145f7b17427e794055929a4283c721
Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75287
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-22 07:24:55 +00:00
Kornel Dulęba 4e4141ac6c mb/google/hatch/jinlon: Add HID to gfx ACPI node
The upstream kernel privacy screen driver uses HID GOOG0010 to look for
firmware node to use. This method is used on other boards, e.g. redrix.
See: drivers/platform/chrome/chromeos_privacy_screen.c in linux sources.
Update jinlon gfx ACPI node to work with that.

BUG=b:279092050
TEST=privacy protection screen works with 5.15 and 4.19 kernels

Change-Id: Icba41e7f2be7292f713fea10dbe69b3ca128bde7
Signed-off-by: Kornel Dulęba <korneld@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75289
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-05-22 06:25:51 +00:00
Robert Chen 721b2ec2dd mb/google/nissa/var/yavilla: Disable unused gpio with fw_config
Disable unused gpio for LTE daughter board, WFC and stylus.

BUG=b:277148122
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: I6cc61321cd96a10dd34ff6cd9fcabe85a64bbfa9
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75293
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-22 06:20:52 +00:00
Michał Żygowski 115aa9421d mb/msi/ms7d25: Disable PCIe hotplug
The support for the board has stabilized and PCIe ports have been
tested with many devices. Although hotplug is not commonly used
and it seems pointless to keep it enabled, so disable it.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I338c55cb57d971badd08235b71626a710fafb829
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-22 06:12:00 +00:00
Bin Meng 60ee6fa398 drivers/emulation/qemu/bochs: Fix the MMIO access to the VGA ioports
The Bochs graphics adapter remaps the legacy VGA ioports
(0x3c0 -> 0x3df) to its MMIO region at offsets 0400 - 041f.
Currently bochs_vga_write() calculates a wrong offset when
accessing these ioports, which causes the boot splash image
not displayed when using the legacy-free pci variant of the
Bochs graphics adapter.

TEST=Build coreboot for QEMU x86 i440fx with a boot splash image
included, boot coreboot.rom with QEMU with '-device secondary-vga'
and verify the boot splash image is correctly displayed.

Fixes: efaf1b32ba ("drivers/emulation/qemu/bochs: Rewrite driver")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Change-Id: I4acc71e3d6ef5161ab62e6714c94b7643c4c0972
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75146
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-21 22:33:39 +00:00
Martin Roth 53b1929e83 Kconfig: Get rid of named choice LAPIC_ACCESS_MODE
The named choice isn't needed here, so get rid of it. This fixes the
build notice:

build/auto.conf:notice: override:reassigning to symbol LAPIC_ACCESS_MODE

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I70628007319a0ee2830dc4c9cb3b635d8190264b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75133
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-05-21 21:19:16 +00:00
Nico Huber 1d95800e32 mb/lenovo/x200: Add VBT files by default
Select INTEL_GMA_HAVE_VBT so VBT files are added by default. This board
has two specific VBT files that are hard-coded in the Makefile. Hence
set an empty INTEL_GMA_VBT_FILE string.

Change-Id: I0508c8016da06b401d6fbefd6e5cec1af018a5c8
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-21 19:51:12 +00:00
Nico Huber 2f7e3db200 nb/intel/gm45/gma: Fix debug note about missing panel data
Reformat the string, fix whitespace, add single-quote before
genitive `s`, and correct the GPU tool name `intel_reg`.

Change-Id: I277603063806927837867a454ae0875578228109
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-21 19:50:56 +00:00
Nico Huber eae75064a8 nb/intel/gm45/gma: Centralize call to gm45_get_lvds_edid_str()
There is only a single place where we need the LVDS EDID string. Let's
call gm45_get_lvds_edid_str() right there. This simplifies the API and
helps to follow the execution flow.

The function is moved to avoid a forward declaration.

Change-Id: I86f3a88e6b661bcf60319edbe301e70304924727
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-21 19:50:45 +00:00
Nico Huber e55825f3c6 nb/intel/gm45/gma: Use res2mmio() directly for GTT access
This is how res2mmio() is supposed to be used and there was no other
use of the `mmio` variable left anyway.

Change-Id: Ifa4645bcc9ae971966587d9b67662b9dc8bae3d0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-21 19:50:35 +00:00
Nico Huber e5888da8de nb/intel/gm45/gma: Probe PCI resource once and first
The PCI resource should only be probed as part of the device
.init process. We can simply do that first and know that we
can use the global `gtt_res` from then on.

This simplifies the signature of gm45_get_lvds_edid_str(), and
makes changes to the API user (lenovo/x200) necessary.

Change-Id: I6c96f715abfa56dcb1cd89fde0fbaef3f1cb63ae
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-21 19:50:24 +00:00
Subrata Banik 9405541b1a soc/intel/meteorlake: Add `.final` to check FSP reset pending request
This patch adds an API to check FSP reset pending requests. This
information is useful to understand if FSP would like boot firmware to
issue any reset to complete the silicon initialization.

As per recent debug it has been found that, FSP is accumulating all
platform resets and executing a single reset from FSP Notify Phase.
As coreboot skipped calling into the FSP Notify APIs hence, it might
have missed the scope to issue the platform reset.

BUG=b:282266168
TEST=Able to build and boot google/rex and able to detect FSP reset
pending request.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibf7c996f09affa099c9124773fe2d581f370d1a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-21 14:53:21 +00:00
Elyes Haouas 04af233f5e payloads/seabios: Update stable from 1.16.1 to 1.16.2
Changes: https://review.coreboot.org/plugins/gitiles/seabios/+/refs/tags/rel-1.16.2

Change-Id: I19b31f89c8fc504284f327c975c159616eb1b241
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-20 19:12:19 +00:00
Felix Singer 531023285e soc/intel/quark: Drop support
As announced in the 4.20 release notes, support for the Intel Quark SoC
is moved to the 4.20 branch and dropped from master.

Change-Id: I8a1ca7a2092aaeaea9c72eac5a8dd8f7d72e8f09
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-05-20 16:27:14 +00:00
Felix Singer 037c25d4dd mb/intel/galileo: Drop support
As announced in the 4.20 release notes, support for the Intel Galileo
mainboard is moved to the 4.20 branch and dropped from master.

Change-Id: I132adf2782721738c954252665fdcd7bb8e1a1cd
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-05-20 16:27:07 +00:00
Sean Rhodes 4265d5265d soc/intel/common: Correct the check for ramtop length
The `ramtop_table` is 10 bytes long, so adjust the check to
account for this.

Also, adjust the wording to make it clear what is required to fix it,
should the error be shown.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If2898c4bb22abb1779035aadc08f32898e9a096b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-19 17:40:39 +00:00
Wisley Chen 443df453bf mb/google/nissa/var/yaviks: Generate LP5 RAM ID for K3KL6L60GM-MGCT
Generate the RAM ID for Samsung K3KL6L60GM-MGCT.

DRAM Part Name                 ID to assign
K3KL6L60GM-MGCT                6 (0110)

BUG=b:281928906
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: Ia5193d3ab3d654f25d519ad9a954f2ca8a15a978
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75152
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@google.com>
2023-05-19 11:09:14 +00:00
Eran Mitrani b7a12982ac mb/google/brya/acpi: Update GC6 sequences
GC6 - Low power mode for system idle on Nvidia GPU

In GC6I Before ramp of PEXVDD:
Deassert FBVDDQ Enable, no delay is needed before or after.
In GC6O After ramp of PEXVDD:
Assert FBVDDQ Enable, no delay is needed before or after.

BUG=b:280467267
TEST=built for Hades and Agah, tested on Agah

Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I0277772b1d2f6f4e6a3f74b92035e8b36f2670ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75302
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-19 10:51:26 +00:00
Dinesh Gehlot 6930b9580e mb/google/rex: Enable stylus support
This patch enables stylus support by configuring the "GPP_D08" irqs for
rex SoC. This allows the SoC to detect a stylus device, when in use.
However stylus is not a wake up source for the rex.

BUG=b:282256460
Test=Stylus is detected on proto1 device.

Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I84a71aa664698e105b738f8680d0a4751ca1fc72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-19 10:45:41 +00:00
Chia-Ling Hou 141d0dfafb soc/intel/jasperlake: Add PsysPmax config
Enable PSYS capability. PSYS is required to safeguard the system
stability if no charger IC.

BUG=b:281479111
TEST=emerge-dedede coreboot chromeos-bootimage & ensure the value is
passed to FSP by enabling FSP log & Boot into the OS

Change-Id: Ibe54acaf80700252558b82f194b9536b6117b84e
Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75196
Reviewed-by: Reka Norman <rekanorman@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-19 10:16:36 +00:00
Won Chung ede5564b3e soc/intel/meteorlake: Add igd device
Add igd device name in soc_acpi_name(), and src/drivers/gfx/generic
can generate device in GFX0 scope in SSDT.

BUG=b:277629750
TEST=emerge-rex coreboot then check SSDT on DUT

Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Id7a136b5234cf5c0f60ecf253ee78c123f1f573b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-19 10:13:58 +00:00
Keith Hui 049e77e6bc nb/intel/i440bx: Roll sdram_set_spd_registers() into parent
Being a static function, compiler is already putting its contents
in sdram_initialize(), its only caller.

Change-Id: Ie74d2283ef672a267d6a0c66d94aa0610f36c4f1
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74033
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-19 10:12:28 +00:00
Keith Hui d118b8e518 nb/intel/i440bx: Compact debug messages
With RAM init debug messages enabled, debug messages take up a lot of
flash space in romstage, with many repeated verbiage. By breaking
them up and factoring out the common verbiage, made possible with
printk(BIOS_DEBUG, "%s", ...), compiler can help deduplicate things
and make the romstage smaller.

When building for asus/p2b-ls with CONFIG_DEBUG_RAM_SETUP, this patch
shrunk romstage by 152 bytes.

Change-Id: I66e39e7901efbeb5ab72494ac02fc4d5e687c3a3
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-05-19 10:12:00 +00:00
Arthur Heymans caf27adb1b device/Kconfig: Reduce PCIe hotplug bus numbers and IO resources
The rationale behind this change is that multiple nested bridges using a
lot of bus numbers and IO resources is not likely to be a common hotplug
setup. When there is a large amount of hotplug ports using 32
subordinate busses results in boot failures (e.g. make qemu). 8K IO
busses for hotplug devices is also excessive in most use cases when only
64K is available in total (again make qemu results in failure to
allocate resources but does boot to payload).

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I8371958037d479e7d2053f49814735e15461ca6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74774
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-19 08:29:53 +00:00
Subrata Banik 3553a16003 soc/intel: Extend fsp_get_pch_reset_status() to all FSP APIs
This patch drops the assert check around
`FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN` config to ensure
`fsp_get_pch_reset_status()` can be used by all other FSP APIs to know
the status of the pending reset.

As per recent debug it has been found that, FSP is accumulating all
platform resets and executing a single reset from FSP Notify Phase.
As coreboot skipped calling into the FSP Notify APIs hence, it might
have missed the scope to issue the platform reset.

Going forward coreboot needs to implement the corresponding logic to be
able to identify any pending platform reset request and execute to
complete the silicon initialization flow.

BUG=b:282266168
TEST=Able to build and boot google/rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I2c9e37fadc27eab820a3121e47e09529de34d10e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75309
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-05-19 08:23:42 +00:00
Felix Held 8c119079d1 vc/amd/fsp/phoenix/FspUsb: update USB config struct for Phoenix SoC
Phoenix has one more Type C port and two more USB2 ports which are used
as the legacy USB part of the two USB4 ports. The USB struct version
numbers have also changed, since it's a newer and incompatible version
of that struct.

TEST=After changing FSP to not hard-code the USB PHY config, but use the
configuration provided by coreboot, and applying this patch, the USB
connector on the USB2 port 4 lines works.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If52934595dd612154b97e7b90dbd96243146017a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73379
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-18 16:23:27 +00:00
Alexander Goncharov 8414eed5a0 cpu/qemu-x86/cache_as_ram_bootblock: drop duplicated post code
Before the bootblock stage starts setting up the CAR mode, it sends
`POST_BOOTBLOCK_CAR` POST code. However, before the definition for
`POST_BOOTBLOCK_CAR` was introduced in the commit
0d34a50a36 , the value `0x20` was used.
At that point, `0x20` means "entry into CAR mode" and `0x21` means
"the cache memory region is cleared". Right now we are sending the
same POST code twice, which makes no sense.

So we can do the following (todo: drop me after we decided which one is
more appropriate):

1) Drop it (current patchset does exactly that)
2) Introduce POST code similar to POST_SOC_CLEARING_CAR and use it
before the cache memory region is cleared.

Change-Id: I5d9014c788abdf5a4338c9e199138d1e514450b3
Signed-off-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-18 16:05:02 +00:00
Martin Roth 2fca0261f1 mb/amd/birman: Don't select the console UART, default to y
Things with prompts should not use selects, but should instead default
to y. If there's a reason they need to be selected, they should be able
to be hidden when they're selected.

This isn't one of those cases where a select is needed, so set the
default to y instead.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If6de339c3a1ceb3cd71008402bba49b5efc4af3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-05-18 08:17:21 +00:00
Martin Roth dd4fa8e603 Myst: Update Makefile to remove SPD injection
The SPD format in the APCB has changed for Phoenix, and the injection
tool 'apcbtool' needs to be updated to match. Until this happens, the
APCB will be built containing the correct SPD.

BUG=b:281983434
TEST=Build

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If575f98511c796e93c5a12cd450a3a7985e39806
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-05-18 08:16:47 +00:00
Felix Singer fb03140757 util/docker: Add Dockerfile for Arch Linux
Add a minimal Dockerfile that pre-installs necessary software which is
needed to work with coreboot.

Change-Id: I85f3dc7b28b77989f0f1400d1282ed4b17082f65
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-05-17 19:55:18 +00:00
Keith Hui 6554873850 nb/intel/i440bx: Clear memory errors before ending raminit
i440BX datasheet says all memory errors reported during RAM init
should be ignored. Do as it says.

Change-Id: Iaf85fde813aa083ae62218a2df5aec303e3c9f8c
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73952
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-17 13:10:10 +00:00
Keith Hui a491f2fa45 nb/intel/i440bx, mb/asus/p3b-f: Abolish disable_spd()
This hook is specifically for asus/p3b-f so its mainboard code has
a chance to put SPD away after RAM init completes. What it intends
to do is done when GPO gets programmed in ramstage (and it's safe
to do so), and no other board needs this hook, so drop it.

Change-Id: Ib7874b4d2b69fdaa5f3c5a3421a62a629c4154a4
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-05-17 13:09:04 +00:00
Cliff Huang f97598f22f acpi: Warn on timeout in write_delay_until()
Make ACPI code print a debug warning message when a timeout is
detected in a loop waiting for a condition.

This timeout message won't be displayed when this function is used as
delay loop (ie. without checking variable condition).

The following is required to get this log in kernel log buffer:

    echo 1 > /sys/module/acpi/parameters/aml_debug_output

Here is an example of generated code when waiting for variable L23E to
be 0.

    Local7 = 0x08
    While ((Local7 > Zero))
    {
        If ((L23E == Zero))
        {
            Break
        }

        Sleep (0x10)
        Local7--
        If ((Local7 == Zero))
        {
            Debug = "WARN: Wait loop timeout for variable L23E"
        }
    }

BRANCH=firmware-brya-14505.B
TEST=Boot to OS and check that the Debug print is added to the
     function.

Change-Id: I3843e51988527e99822017d1b5f653ff2eaa7958
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73348
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-17 11:30:30 +00:00
Leo Chou ea49357e90 mb/google/nissa/var/pujjo: Add GPIO setting for WWAN_5G
Pujjoteen5 support WWAN 5G device, add GPIO setting for WWAN 5G device

BUG=b:281943398
TEST=Build and check serial log

Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Ie2e0ea34c54a453645d626f892f50654ef5064ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75195
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-17 11:27:26 +00:00
Leo Chou 7538853429 mb/google/nissa/var/pujjo: Enable PCIe port 3 for WWAN_5G
Pujjoteen5 support WWAN 5G device, enable PCIe port 3 for WWAN 5G device

BUG=b:281943398
TEST=Build and boot on pujjo

Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I6d2e8eaecae968ed51095d9497beab492ba7e0c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
2023-05-17 11:26:58 +00:00
Eran Mitrani 24ca5ef618 mb/google/brya/variants/hades: Set up internal pull-up for GPIOs
BUG=b:280843816
TEST=builds

Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I55a85335a34eee227abb6ff355719f7ca2cbf04a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-05-17 11:26:20 +00:00