Remove useless help texts since they don't add any more value.
Change-Id: Iabcaec1bc8abe2c4628105752e49247e946fcfe7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52786
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove useless help texts since they don't add any more value.
Change-Id: Id8a15681a98ceb648814662545f5a3bf0f14b95c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52777
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These are mostly copied from picasso code with exception for
bl_syscall_public.h. For some SVCs svc number and/or prototype has been
changed.
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I6b431fdbf34fca2747833980ae53c06244905f93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Provide a SOC_INTEL_SKYLAKE_LGA1151_V2 option to select correct defaults
for the combination of a Union Point PCH with LGA1151v2.
As of the year 2021 it's common for motherboards with Z370, H310C
or B365 PCHs, which are meant to be paired with Coffee Lake CPUs.
Intel provides AmberLakeFspBinPkg to support this combination,
which implements Intel FSP External Architecture Specification v2.1.
Details:
1) Provide SOC_INTEL_SKYLAKE_LGA1151_V2 option that selects
PLATFORM_USES_FSP2_1, SOC_INTEL_COMMON_SKYLAKE_BASE and
SKYLAKE_SOC_PCH_H.
2) Add Amberlake FSP support.
If SOC_INTEL_SKYLAKE_LGA1151_V2 is set, use AbmerLakeFspBinPkg instead
of KabylakeFspBinPkg.
3) Enable Coffee Lake CPUs support.
If SOC_INTEL_SKYLAKE_LGA1151_V2 is set, select
MAINBOARD_SUPPORTS_COFFEELAKE_CPU.
4) Increase stack and heap size in CAR.
If FSP_USES_CB_STACK is set (it's selected by PLATFORM_USES_FSP2_1),
update DCACHE_BSP_STACK_SIZE and FSP_TEMP_RAM_SIZE values.
5) Update maximal number of supported CPUs.
If MAINBOARD_SUPPORTS_COFFEELAKE_CPU is set, set MAX_CPUS to 16.
Signed-off-by: Timofey Komarov <happycorsair@yandex.ru>
Change-Id: I7b6b9c676da55088cb5a12a218ea58d349ee440c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The Z370, H310C and B365 PCHs use the same silicon as 200-series
PCHs and they are supported by soc/intel/skylake codebase
(not by soc/intel/cannonlake). Mentioned PCHs are meant to be paired
with Coffee Lake CPUs, so add the corresponding microcodes.
Signed-off-by: Timofey Komarov <happycorsair@yandex.ru>
Change-Id: I479c648e40c4c607d29f8cdd913fdbd6d7d7d991
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Inspired by discussion in CB:22822.
If I2C bus step response has not been measured, assume the layout to
have been designed with a minimal capacitance and SCL rise and fall
times of 0 ns. The calculations will add the required amount of
reference clocks for the host to drive SCL high or low, such that the
maximum bus frequency specification is met.
Change-Id: Icbafae22c83ffbc16c179fb5412fb4fd6b70813a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52723
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Mancomb will have the boot flash on a daughterboard, so the SPI speeds
need to be low for now.
BUG=b:182211161
TEST=Build
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Icacb68d65fb414197d7b8d45799527d8d2568dc7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Guybrush is pretty definitely alive, so this can be removed, as the
TODO line said.
BUG=180721202
TEST=Build
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I14f89f3e6f780c2da2136a838950ef2bcebc4c3a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
There is no lid switch in mancomb so remove it.
Will replace the lid switch with a fake gpio in depthcharge.
BUG=b:182211161
TEST=Depthcharge no longer halts complaining that coreboot didn't sample
the pin
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: Ifd0fcec9557bf7ebad64ce9342d3b50eb511522b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
1. Wrap the long lines.
2. Align the message.
3. Add new SOC name, Cezanne.
4. Fix the cases.
Change-Id: Id537d7c9b77641289274c1b2b6f606e2be37ac6b
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The usage of external oscillator has got nothing to do with Audio
Co-processor (ACP). Hence move it out of common config and put it into
the SoC config where it is being used.
BUG=None
TEST=Build Dalboz and Vilboz mainboards.
Change-Id: I8c5d98addfba750f9ddb87a846599541b4a8340a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add telemetry setting to UPD, the value comes from the SDLE testing.
BUG=b:182754399
TEST=Build & Boot guybrush
Cq-Depend: chrome-internal:3787638
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I9dd3643e9c582a41192130901935eef321b2c67e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52733
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Follow the FP6 IRM(#56328) to set the stapm parameter
and allow other mancomb variants boards can customize those parameters.
BUG=b:1181157669
TEST=build.
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ib3ed76e5212a5a8b5fb4fcc3d6884ceff82377b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
cmocka is currently ignoring the UPDATED_SUBMODULES flag. Move the
cmocka checkout with the other submodule checkouts.
BUG=none
TEST=Make sure cmocka is not checked out if UPDATED_SUBMODULES=1
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I2a1db809368a77d2c0f9c9a796d62555ec476dc7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
The intermediate base and length are not required in ASL.
Change-Id: I0c72e2e4f7ec597adc16dbdec1fd7bbe4e41bfd6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51637
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The boolean is stored in ChromeOS NVS, not GNVS.
Change-Id: I5c424a052d484228a456f8f0ad4fb0bed3165e09
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Configure ADSP domain from 0 to 4 and lock it to prevent
changing it unexpectedly.
TEST=emerge-asurada coreboot
BRANCH=asurada
Change-Id: Ib938ba05e8d0342572c57366c97ebb0185da8aba
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52728
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The existing helpers for reading/writing MSRs (rdmsr, wrmsr) require use
of the struct `msr_t`, which splits the MSR value into two 32 bit parts.
In many cases, where simple 32 bit or 64 bit values are written, this
bloats the code by unnecessarly having to use that struct.
Thus, introduce the helpers `msr_read` and `msr_write`, which take or
return `uint64_t` values, so the code condenses to a single line or two,
without having to deal with `msr_t`.
Example 1:
~~~
msr_t msr = {
.lo = read32((void *)(uintptr_t)0xfed30880),
.hi = 0,
};
msr.lo |= 1;
wrmsr(0x123, msr);
~~~
becomes
~~~
uint32_t foo = read32((void *)(uintptr_t)0xfed30880);
msr_write(0x123, foo | 1)
~~~
Example 2:
~~~
msr_t msr = rdmsr(0xff);
uint64_t msr_val = (msr.hi << 32) | msr.lo;
~~~
becomes
~~~
uint64_t msr_val = msr_read(0xff);
~~~
Change-Id: I27333a4bdfe3c8cebfe49a16a4f1a066f558c4ce
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52548
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Brya uses CBI to store dram part number. So enable the config.
BUG=b:186571840
BRANCH=none
TEST=dmidecode -t 17 can show the dram part number.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I1b4fc4da31d8964763c3e671d84be71996fa5e2a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This adds full EINJ support with trigger action tables. The actual
error injection functionality is HW specific. Therefore, HW specific
code should call acpi_create_einj with an address where action table
resides. The default params of the action table are filled out by the
common code. Control is then returned back to the caller to modify or
override default parameters. If no changes are needed, caller can
simply add the acpi table. At runtime, FW is responsible for filling
out the action table with the proper entries. The action table memory
is shared between FW and OS. This memory should be marked as reserved
in E820 table.
Tested on Deltalake mainboard. Boot to OS, load the EINJ driver (
modprobe EINJ) and verify EINJ memory entries are in /proc/iomem.
Further tested by injecting errors via the APEI file nodes. More
information on error injection can be referenced in the latest ACPI
spec.
Change-Id: I29c6a861c564ec104f2c097f3e49b3e6d38b040e
Signed-off-by: Rocky Phagura <rphagura@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Rocky Phagura
This CL configures TCSS, BT and WiFi related GPIOs based on schematics.
BUG=None
TEST= BT, WIFI and TCSS functionalities validated with this change.
Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Change-Id: Ie0e665275c281fcbad0d02ceb723cea433637711
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50516
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to SED team provided ELAN touch screen SPEC. IRQ trigger
method need set with level trigger, that modify IRQ trigger to level
from edge.
BUG=b:174972088
TEST=Build FW and boot to OS and check with test result.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I9237d9aad6166a5754afe464ce8453129a58d283
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
We no longer lock up if we clear the port 80 bit. I'm assuming this was
fixed when we configured the PSP to no longer setup eSPI.
BUG=b:183974365
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1530d08974d42e0b06eb783521dea32fca752d85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
guybrush and mancomb don't configure any GPIO as PAD_SMI. Since
mainboard_smi_gpi will only get called for a GEVENT that will cause a
non-SCI SMI, this isn't expected to be called. For the unexpected and
very unlikely case that it still does get called, put a printk into
mainboard_smi_gpi to see what is happening there.
TEST=none
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifd6e3348ecc078932bf6cf5b0830b4b034d274bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52360
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
zork doesn't configure any GPIO as PAD_SMI. Since mainboard_smi_gpi will
only get called for a GEVENT that will cause a non-SCI SMI, this isn't
expected to be called. For the unexpected and very unlikely case that it
still does get called, put a printk into mainboard_smi_gpi to see what
is happening there.
TEST=none
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I14c67b21a83b334558cdd54ebf700924aa9d0808
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52359
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Temp stack for verstage is only needed for picasso, so make it optional
in the layout file.
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I44196103a3531e9d01c96ab8f454c8b580fe9807
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
From cezanne we have enough space in PSP so we don't have to worry about
workbuf size. Hence the function only exists in picasso and deprecated
for later platforms.
So wrap svc_get_max_workbuf_size and provide default weak function so
future platforms don't have to implement dumb function for it.
TEST=build and boot zork, check weak function is not called in zork
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I16e8edf8070aaacb3a6a6a8adc92b44a230c3139
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
These addresses will be changed in cezanne. Before start working on
cezanne, move these out to separate header as a clean-up.
TEST=emerge-zork coreboot
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I2499281d250aae701f86bfcc87c7681e5b684b6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Configure Audio Co-processor(ACP) to operate in I2S TDM mode. Also fix
the scope in which ACP is defined in the devicetree.
BUG=b:182960979
TEST=Build and boot to OS in Guybrush. Ensure that the ACPD device is
enabled in the appropriate scope in SSDT.
Change-Id: Ic90fd82e5c34a9feb9a80c4538a45e7c2fb91add
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Audio Co-processor driver is similar for both Picasso and Cezanne SoCs.
Hence move it to the common location.
BUG=None.
TEST=Builds Dalboz, Trembyle, Vilboz, Mandolin and Bilby mainboards.
Change-Id: I91470ff68d1c183df9a2927d71b03371b535186a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
All guybrush boards should have system_configuration set to 2, so
put this in the main devicetree.
BUG=b:185209734
TEST=Build & Boot guybrush
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I1ce2acb3b4ed51aa9a0aa379ed125f0b04f04d31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: chris wang <Chris.Wang@amd.com>
Some platforms which have large amounts of RAM and also write-combining
regions may decide to drop the WC regions in favor of the default when
preserving MTRRs for the OS. From a data safety perspective, this is
safe to do, but if, say, the graphics framebuffer is the region that is
changed from WC to UC/WB, then the performance of writing to the
framebuffer will decrease dramatically.
Modern OSes typically use Page Attribute Tables (PAT) to determine the
cacheability on a page level and usually do not touch the MTRRs. Thus,
it is believed to be safe to stop reserving MTRRs for the OS, in
general; PentiumII is the exception here in that OSes that still
support that may still require MTRRs to be available. In any case, if
the OS wants to reprogram all of the MTRRs, it is of course still free
to do so (after consulting the e820 table).
BUG=b:185452338
TEST=Verify MTRR programming on a brya (where `sa_add_dram_resources`
was faked to think it had 32 GiB of DRAM installed) and variable MTRR
map includes a WC entry for the framebuffer (and all the RAM):
MTRR: default type WB/UC MTRR counts: 13/9.
MTRR: UC selected as default type.
MTRR: 0 base 0x0000000000000000 mask 0x00003fff80000000 type 6
MTRR: 1 base 0x0000000077000000 mask 0x00003fffff000000 type 0
MTRR: 2 base 0x0000000078000000 mask 0x00003ffff8000000 type 0
MTRR: 3 base 0x0000000090000000 mask 0x00003ffff0000000 type 1
MTRR: 4 base 0x0000000100000000 mask 0x00003fff00000000 type 6
MTRR: 5 base 0x0000000200000000 mask 0x00003ffe00000000 type 6
MTRR: 6 base 0x0000000400000000 mask 0x00003ffc00000000 type 6
MTRR: 7 base 0x0000000800000000 mask 0x00003fff80000000 type 6
MTRR: 8 base 0x000000087fc00000 mask 0x00003fffffc00000 type 0
ADL has 9 variable-range MTRRs, previously 8 of them were used, and
there was no separate entry for the framebuffer, thus leaving the
default MTRR in place of uncached.
Change-Id: I2ae2851248c95fd516627b101ebcb36ec59c29c3
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
From ANX7625 spec, the delay between powering on power supplies and GPIO
should be larger than 10ms. Since it takes about 4ms for the previous
GPIO EN_PP3300_EDP_DX to be pulled up, increase the delay from 2ms to
14ms.
BUG=b:157716104
TEST=emerge-asurada coreboot
BRANCH=asurada
Change-Id: If73747bdaec5ac069b048920d27e27178bc3cedc
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This change is needed to update the option API to use unsigned integers.
The CMOS option system does not support negative numbers.
The volume field is only 8 bits long. Do not set the volume if it is out
of range. Also, use an out-of-range value as fallback to skip setting
the volume when it cannot be read using the option API, to preserve the
current behavior.
Change-Id: I7af68bb5c1ecd4489ab4b826b9a5e7999c77b1ff
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Follow L850GL spec to adjust power sequence. RST need to drive low
before power on then drive to high.
SPEC:FIBOCOM_L850-GL Hardware User Manual_V1.0.8
BUG=b:186374631
TEST=WWAN is detected by lsusb.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I13357677bb1ab185abf1d4c915a762a9d6894312
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Rewrite google_chromeec_status_check to use stopwatch instead of a
delay in a while loop. In practice the while loop ends up taking
much longer than one second to timeout. Using stopwatch library will
accurately timeout after one second.
BUG=b:183524609
TEST=Build and run on guybrush
BRANCH=None
Change-Id: I363ff7453bcf81581884f92797629a6f96d42580
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The board can be flashed without adding a diode by just leaving VCC
unconnected. Rework the flashing section to describes that.
Change-Id: I37d55ffdbcfba4f3a1113a82f16ec8766bbb6e6c
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This change replaces --diff and --fast-verify for the supported
equivalent flashrom options
Signed-off-by: Daniel Campello <campello@chromium.org>
Change-Id: I8c48c7f819f968c3ddd94278415e5e9e0ef93924
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
This changes adds the EC_HOST_EVENT_USB_MUX to be dark resume source.
BUG=b:183140386
TEST=In S0ix, remove DP dongle, system does dark resume. AP and EC
synchronized. AP got port partner disconnection.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I53bd4fee21e2e2d1f16f558ab0341a50ef9a0e14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52716
Reviewed-by: Tanu Malhotra <tanu.malhotra@intel.com>
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
vboot has been updated to track main branch, however the
.gitmodules defaults to master branch following the
coreboot default. This impacts the rebase of submodule
git submodule update --remote --rebase 3rdparty/vboot/
With this change the rebase to latest commit is successful
Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com>
Change-Id: I7713aecdec43a5d5623ef81803ac0fc02ce14070
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52664
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The code is already compiled in on all platforms. Use it as it provides
the same functionality. Note that GCAP is no longer R/WO on these
platforms. However, select `AZALIA_LOCK_DOWN_R_WO_GCAP` just in case.
This will be dropped in a follow-up.
Tested on Prodrive Hermes, still detects and initializes both codecs.
Change-Id: I75424559b2b4aca63fb23bf4f8d5074aa1e1bb31
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50795
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Felix Singer