The headers added are generated as per FSP v2081_02.
Previous FSP version was v2081_02.
Changes Include:
- Adjust UPD Offset in FspmUpd.h and FspsUpd.h
- Add UPDs in Fsps.h and Fspm.h
BUG=b:180918805
BRANCH=None
TEST=Build and boot ADLRVP
Change-Id: I69611de8286a570c59a6b4a44b9164384e9be81f
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51632
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
OIPG is a Package. Define the type so it doesn't default to UnknwonObj.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I068ed4ae95967aa884506c4971ee2e2dba7b5e4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51537
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, if `get_wifi_sar_cbfs_filename()` returns NULL, then
`get_wifi_sar_limits()` assumes that the default filename is used for
CBFS SAR file. This prevents a board from supporting different models
using the same firmware -- some which require SAR support and some
which don't.
This change updates the logic in `get_wifi_sar_limits()` to return
early if filename is not provided by the mainboard. In order to
maintain the same logic as before, current mainboards are updated to
return WIFI_SAR_CBFS_DEFAULT_FILENAME instead of NULL in default
case.
Change-Id: I68b5bdd213767a3cd81fe41ace66540acd68e26a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51485
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SAR table in VPD has been deprecated for Chrome OS platforms for > 1
year now. All new Chrome OS platforms have switched to using SAR
tables from CBFS.
This change drops the support for SAR table in VPD from coreboot to
align with the factory changes. `get_wifi_sar_limits()` is thus
updated to look for SAR file in CBFS only.
Anyone building ToT coreboot for an already released Chrome OS
platform with SAR table in VPD will have to extract the "wifi_sar" key
from VPD and add it as a file to CBFS using following steps:
- On DUT, read SAR value using `vpd -i RO_VPD -g wifi_sar`
- In coreboot repo, generate CBFS SAR file using:
`echo ${SAR_STRING} > site-local/${BOARD}-sar.hex`
- Add to site-local/Kconfig:
```
config WIFI_SAR_CBFS_FILEPATH
string
default "site-local/${BOARD}-sar.hex"
```
BUG=b:173465272
Change-Id: I21d190dcc9f3554fab6e21b4498e7588a32bb1f0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Originally, log macro names are too long, and they use
double parentheses style: ((...)), which causes compile
or runtime error easily.
Now, change them to single parenthesis mode (...), and
use shorter name.
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: I2959dc1ba0dd40a8fb954406072f31cf14c26667
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
In RX Gating flow, PI P1 delay is missing, so re-add the initialization.
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: Ic72ccecd205062ee79f6928993fac772fc10f880
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This UPD will be used to pass VBIOS buffer pointer to FSP PEI GOP
driver.
BUG=b:171234996
BRANCH=Zork
Change-Id: I0c5d4a9d96e5c3d47e262072b689ed62e59129b3
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49866
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The headers added are generated as per FSP v2081_02.
Previous FSP version was v2037.
Changes Include:
- Adjust UPD Offset in FspmUpd.h and FspsUpd.h
- Add DevIntConfigPtr and NumOfDevIntConfig UPDs in Fsps.h
BUG=b:180758116
BRANCH=None
TEST=Build and boot ADLRVP
Cq-Depend: chrome-internal:3669105
Change-Id: Ib99748a428709ffad27d47f600e00bd91b70d8f3
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51248
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Mediatek has released the reference implementation for DRAM
initialization in vendorcode/mediatek/mt8192/dramc (CB:50294)
so we want to use it to replace the derived calibration code
in soc folder.
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: I2b2f41d774c6b85f106867144fb0b29a4a1bdfcf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This is the DRAM initialization code from the reference
implementation released by Mediatek for MT8192.
The DRAM calibration code can be taken as a standalone
library, used by different boot loaders for initializing
DRAM and following a different coding style (coreboot was
using Linux Kernel coding style), so we have to put it
in vendor code folder.
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
We will need more FSPS UPD space for PEI GOP changes coming.
BUG=b:171234996
BRANCH=Zork
Cq-Depend: chrome-internal:3609213, chromium:50576
Change-Id: I35d0bb0ee30e04f66882b6103acd9d673d040c07
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
CrashLog is a diagnostic feature for Intel TGL based platforms.
It is meant to capture the state of the platform before a crash.
The state of relevant registers is preserved across a warm reset.
BUG=None
TEST=CrashLog data generated, extracted, processed, decoded sucessfully on delbin.
Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Change-Id: Ie3763cebcd1178709cc8597710bf062a30901809
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
We have adjusted allocation order such that GNVS is available
before ME hash needs to be stored.
Change-Id: I8428dd85f44935938a118a682767f2f8d6d539ab
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The allocation is for the OS. Just need to take care
in the firmware that ChromeOS GNVS is allocated first.
Change-Id: I16db41b31751d7b4a8a70e638602f3f537fe392e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50609
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These files have windows line endings. Change to unix to match the
rest of the tree.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I5bb3338745a6a47b6714aa268d16866aada27790
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add support for MP services2 PPIs, which is slight modification
over MP services 1 PPIs. A new API StartupAllCPUs have been added
to allow running a task on BSP and all APs. Also the EFI_PEI_SERVICES
parameter has been removed from all MP PPI APIs.
This implementation also selects the respective MP services PPI version
supported for SoCs
BUG=b:169196864
Change-Id: Id74baf17fb90147d229c78be90268fdc3ec1badc
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
add UPD for RV2 USB3 phy setting adjust.
Note: it only for RV2 silicon and not available for RV/PCO.
Usb 3.1 PHY Parameters:
1. RX_EQ_DELTA_IQ_OVRD_VAL
-Override value for rx_eq_delta_iq. Range 0-0xF
2. RX_EQ_DELTA_IQ_OVRD_EN
-Enable override value for rx_eq_delta_iq. Range 0-0x1
3. Override value for rx_vref_ctrl. Range 0 - 0x1F
4. Enable override value for rx_vref_ctrl. Range 0 - 0x1
5. Override value for tx_vboost_lvl: 0 - 0x7.
6. Enable override value for tx_vboost_lvl. Range: 0 - 0x1
7. Override value for rx_vref_ctrl. Range 0 - 0x1F
8. Enable override value for rx_vref_ctrl. Range 0 - 0x1
9. Override value for tx_vboost_lvl: 0 - 0x7.
10. Enable override value for tx_vboost_lvl. Range: 0 - 0x1
BUG=b:175192931
TEST=Build/verify the valule will been apply on dirinboz
Change-Id: I1d5f69e840952cc5171af1ce8597628d1bede5cb
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50240
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This allows to compile FSP related tools (like the FSP loader) in
x86_64 mode, but it doesn't add support for properly running x86_32
FSP on x86_64. This is handled in a separate patch.
Change-Id: I0e3099fae1b70bfe9ec0abbdddb4231ab5e2f388
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add new Kconfig symbols to mark FSP binary as x86_32.
Fix the FSP headers and replace void pointers by fixed sized integers
depending on the used mode to compile the FSP.
This issue has been reported here:
https://github.com/intel/FSP/issues/59
This is necessary to run on x86_64, as pointers have different size.
Add preprocessor error to warn that x86_64 FSP isn't supported by the
current code.
Tested on Intel Skylake. FSP-M no longer returns the error "Invalid
Parameter".
Change-Id: I6015005c4ee3fc2f361985cf8cff896bcefd04fb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The recent merge of Intel ADL FSP 2017.00 appears to have introduced a
new dependency within the file MemInfoHob.h. Adding required macros to
resolve the dependency.
BUG=b:178846328
Change-Id: I18370edca481bac5fdd483680cd7b05b216d10fc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50254
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This was used as a means to read the MAC address and dynamically
return it to the ethernet driver via ACPI. The kernel team ended
up going another direction so this became obsolete.
Change-Id: I7065bea4b288c689b41cc969989ec6fd87c75f1f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49902
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
coreboot proper now has a single include for this file
with the guard around it already.
Change-Id: Ice48a6af391170232a0319cc894bdb6c465c5143
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There will be incompatible changes during the further development of the
coreboot+FSP support for Cezanne, but we do need the FSP-M UPD struct
size to match the one in the FSP header. See CB:50241 for details.
Signed-off-by: Justin Frodsham <justin.frodsham@protonmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icade1d7bcab7b85cdd25c4114590eb23b914edcd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50242
Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to Tigerlake TDP specifications (doc #575683, table 4-2),
TGL supports different TDP levels depends on CPU segement/package,
IA Cores and graphics configuration. For example, UP3 4-Core GT2
suppots base TDP=28W, Configurable TDP-Down_1=15W and Configurable
TDP-Down_2=12W. This configurable value can be used to select
suitable TDP level
Change-Id: I4242575807caac172b6cbe667839bf6c9241f3c5
Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
For builds with MAINBOARD_HAS_CHROMEOS=y but CHROMEOS=n, there
is reduced dsdt.aml size and reduced GNVS allocation from cbmem.
More importantly, it's less error-prone when the OperationRegion
size is not hard-coded inside the .asl files.
Change-Id: I54b0d63a41561f9a5d9ebde77967e6d21ee014cd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49477
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add UPDs for eDP power sequence adjust.
BUG=b:171954512
BRANCH=zork
TEST=Build, verify the parameter pass to picasso-fsp
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ic4bafd86ffb7804c4739f9d30beb67549b71d289
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This is a trimmed-down version of the Cezanne FSP integration code, so
for example the UPD definitions are empty, which will be addressed
later. Since coreboot just leaves the UPD values at their default, this
is not a problem during the initial platform bring-up.
Change-Id: Ie0fc30120c2455aa2160708251e9d2f229984305
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
CSE Firmware Sync is being performed in romstage currently. But the CSE
board reset is not included as part of romstage. This causes the CSE
firmware sync to use global reset instead of EC assisted AP reset with
the old Cr50 Firmware version. Include the board specific CSE reset in
romstage.
BUG=b:171731175,b:177795247
BRANCH=dedede,volteer,puff
TEST=Ensured that the Drawlat boots to OS with both old(0.0.22) and
new(0.6.7) Cr50 FW versions.
Change-Id: I5e362271ffb68ffd5884279acd1ab0a462195a8a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49850
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The layout of GNVS has expectation for a fixed size
array for chromeos_acpi_t. This allows us to reduce
the exposure of <chromeos/gnvs.h>.
If chromeos_acpi_t was the last entry in struct global_nvs
padding at the end is also removed.
If device_nvs_t exists, place a properly sized reserve for
chromeos_acpi_t in the middle.
Allocation from cbmem is adjusted such that it matches exactly
the OperationRegion size defined inside the ASL.
Change-Id: If234075e11335ce958ce136dd3fe162f7e5afdf7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
On Coffee Lake systems prog_locate_hook() is called with PROG_POSTCAR.
For this reason the early check is not executed.
Add check for prog->type == PROG_POSTCAR, but execute
verified_boot_early_check() once.
BUG = N/A
TEST = Build and boot on Facebook FBG1701 and Intel CoffeeLake system
Change-Id: Ia3bd36064bcc8176302834c1e46a225937d61c20
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48852
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop the support for the Intel Cannon Lake SoC for various reasons:
* Most people can't use coreboot on Cannon Lake, since the required FSP
binaries aren't publicly available. Given that FSP binaries for several
newer platforms have been released, it's very unlikely that Cannon Lake
FSP will ever be released.
* It seems there is no interest in this, since the reference mainboard
is the only available mainboard in tree.
Also, remove the related reference mainboard intel/cannonlake_rvp and
its FSP headers in intel/fsp2_0/cannonlake.
Change-Id: I8f698e16099acb45444b2bc675642d161ff8c237
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48775
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With Intel CPX-SP FSP ww01 release, CidBitMap field is added to
DimmDevice struct in hob_memmap.h.
The copyright statements were updated to accomodate year 2021.
gpio_fsp.h is not needed any more as coreboot takes over GPIO
configuration.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I3242c8b50401757a28de8a9e9c71fb95bc0515dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Update v 3444 FSP headers for Tiger Lake platform to include the
below 2 UPDs to control TC cold support usb connect or not.
FSPS:
Usb3ComplModeEnable
DisableTccoldOnUsbConnected
BUG=b:173054070
TEST=Build and boot on delbin.
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I68b32730293fc83b5088074f71fa215220574748
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: John Zhao <john.zhao@intel.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The code in soc/amd/common has an implementation of
GPIO register space that is compatible with the hardware
sb/amd/pi/hudson supports.
Change-Id: I86ae40a3cdf335263d7e9e3dcfdd588947cdd9b1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
