Commit Graph

20279 Commits

Author SHA1 Message Date
Lee Leahy ae3fd34e00 src/include: Add space after comma
Fix the following error detected by checkpatch.pl:

ERROR: space required after that ',' (ctx:VxV)

TEST=Build and run on Galileo Gen2

Change-Id: I297bfc3d03dc95b471d3bb4b13803e81963841b5
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18647
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-09 17:19:16 +01:00
Lee Leahy 708fc274b5 src/include: Indent code using tabs
Fix the following error and warning detected by checkpatch.pl:

ERROR: code indent should use tabs where possible
WARNING: please, no spaces at the start of a line

TEST=Build and run on Galileo Gen2

Change-Id: I487771b8f4d7e104457116b772cd32df5cd721a6
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18646
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-09 17:18:42 +01:00
Lee Leahy bb4ae07417 src/include: Add do { } while(0) around macros
Fix the following error detected by checkpatch.py:

ERROR: Macros with multiple statements should be enclosed in a do - while loop

False positives are generated when assembly code is used in a macro.  An
example is:

ERROR: Macros with multiple statements should be enclosed in a do - while loop
+#define post_code(value)        \
+	movb    $value, %al;    \
+	outb    %al, $CONFIG_POST_IO_PORT

False positives are also generated for linker script include files.  An
example is:

ERROR: Macros with multiple statements should be enclosed in a do - while loop
+#define SET_COUNTER(name, addr) \
+	_ = ASSERT(. <= addr, STR(name overlaps the previous region!));
\
+	. = addr;

False positives are also generated for attribute macros.  An example is:

ERROR: Macros with multiple statements should be enclosed in a do - while loop
+#define DISABLE_TRACE_ON_FUNCTION  __attribute__
((no_instrument_function));

TEST=Build and run on Galileo Gen2

Change-Id: I88abf96579e906f6962d558a3d09907f07d00b1c
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18644
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-09 17:18:02 +01:00
Lee Leahy e0f5dfc678 src/include: Move trailing statements to next line
Fix the following error detected by checkpatch.pl:

ERROR: trailing statements should be on next line

TEST=Build and run on Galileo Gen2

Change-Id: I169f520db6f62dfea50d2bb8fb69a8e8257f86c7
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18643
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-09 17:16:35 +01:00
Lee Leahy 0ca2a0654c src/include: Fix unsigned warnings
Fix warning detected by checkpatch.pl:

WARNING: Prefer 'unsigned int' to bare use of 'unsigned'

BRANCH=none
BUG=None
TEST=Build and run on Galileo Gen2

Change-Id: I23d9b4b715aa74acc387db8fb8d3c73bd5cabfaa
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18607
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-09 17:16:09 +01:00
Li Cheng Sooi 75d8d8da47 soc/intel/skylake: Add GPIO macros for IOxAPIC and SCI
Add two GPIO macros:
  1. PAD_CFG_GPI_APIC_EDGE allows a pin to be route to the
     APIC with input assuming the events are edge triggered.

  2. PAD_CFG_GPI_ACPI_SCI_LEVEL to route the general purpose
     input to SCI assuming the events are level triggered.

Change-Id: I944a9abac66b7780b2336148ae8c7fa3a8410f3f
Signed-off-by: Rahul Kumar Gupta <rahul.kumarxx.gupta@intel.com>
Reviewed-on: https://review.coreboot.org/18533
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-09 16:41:18 +01:00
Li Cheng Sooi 6a740539d1 soc/intel/skylake: Add SKL SOC PCH H GPIO support
Add SKL/KBL PCH-H GPIO settings referring from SKL PCH-H
specifications to support sklrvp11.

Split the gpio_defs.h into headers gpio_pch_h_defs.h and
gpio_soc_defs.h for PCH-H specific and SOC specific GPIO
defs respectively.

Change-Id: I5eaf8d809a1244a56038cbfc29502910eb90f9f2
Signed-off-by: Li Cheng Sooi <li.cheng.sooi@intel.com>
Signed-off-by: Rahul Kumar Gupta <rahul.kumarxx.gupta@intel.com>
Reviewed-on: https://review.coreboot.org/18027
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-09 16:38:40 +01:00
Kyösti Mälkki 86ee4db0d8 AGESA: Use printk for IDS output
In all simplicity, with board/OptionsIds.h file having:
  IDSOPT_IDS_ENABLED TRUE
  IDSOPT_TRACING_ENABLED TRUE

And src/Kconfig modified to:
  config WARNINGS_ARE_ERRORS
  default n

With these settings AGESA outputs complete debugging log
where-ever you have your coreboot console configured.

Change-Id: Ie5c0de6358b294160f9bf0a202161722f88059c1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15320
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins)
2017-03-09 12:47:02 +01:00
Kyösti Mälkki 055be5d1e5 AGESA f15: Disable IDS tracing by default
We build with WARNINGS_ARE_ERRORS, while IDS tracing will
raise various (non-fatal) printk() format warnings.

Change-Id: I9dc81c89ee60d17a6556a412380fed1413af66bd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18560
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-03-09 12:46:17 +01:00
Kyösti Mälkki bfa72ce23b AGESA: Make eventlog more tolerant to failures
We have been forced to build AGESA with ASSERT() as non-fatal
for some board, as hitting those errors is not uncommon.

For the cases touched here, abort eventlog operations early
to avoid further errors and dereference of null pointers.

Change-Id: I1a09ad55d998502ad19273cfcd8d6588d85d5e0c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18543
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-03-09 12:45:49 +01:00
Kyösti Mälkki 49b4a89323 AGESA: Fix loop condition for eventlog read
Do not evaluate AmdEventParams if AmdReadEventLog() fails.

Change-Id: I2b8afe827ffe6757e64c00ab005d3bb8cc577321
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18611
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-03-09 12:44:56 +01:00
Kyösti Mälkki 4f74c89592 AGESA: Apply a threshold on event logging
Implement threshold as described in AMD.h, and do not add
entries below STATUS_LOG_LEVEL in the eventlog.

Change-Id: Ic9e45b1473b4fee46a1ad52d439e8682d961dc03
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18542
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-03-09 12:44:28 +01:00
Kyösti Mälkki 50e6daff95 AGESA: Log heap initialisation
This is useful for debugging S3 issues and in general
to understand AGESA memory allocator behaviour.

Change-Id: I422f2620ed0023f3920b8d2949ee1c33a6c227e0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18535
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
2017-03-09 12:44:09 +01:00
Kyösti Mälkki 86690eb0a1 AGESA: Log if memory training result cannot be stored
A problem around CAR teardown time may result with missing
training results at the time we want to save them.

Record this in the logs for debugging purposes, it will
not be possible to use S3 suspend if this happens.

Change-Id: Id2ba8facbd5d90fe3ed9c6900628309c226c2454
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18534
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-03-09 12:43:40 +01:00
Kyösti Mälkki 26929bd71a AGESA: Fix SSE regression and align stack early
When allowing use of SSE instructions, stack must be
aligned to 16 bytes. Adjust x86 entry to C accordingly,
by pushing values to maintain the alignment.

Fixes regression with new toolchain using GCC-6.3 and
  ec0a393 console: Enable printk for ENV_LIBAGESA

For some builds, the above-mentioned commit emitted
SSE instruction 'andps (%esp),%xmm0' with incorrectly
aligned esp, raising exception and thus preventing boot.

Change-Id: Ief57a2ea053c7497d50903838310b7f7800bff26
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18622
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-09 12:42:56 +01:00
Idwer Vollering 171d1a5979 toolchain: fix compilation of GMP on FreeBSD
Built on FreeBSD -CURRENT
Obtained from FreeBSD: bbedec80e3

Change-Id: Ic6b6db8e3a9d86a30c50a09d58566846446031ea
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: https://review.coreboot.org/18675
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-03-09 12:15:56 +01:00
Paul Menzel 7129ccbd23 cpu/intel/model_6{e,f}x: Unify init files
The init files for the Core Duo and Core 2 Duo are very similar. Reduce
the differences, by using the same order for the include statements, the
same blank lines, and the same comments.

Change-Id: I0de060222a61a482377c760c6031d73c7e318edf
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/18506
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-09 10:06:12 +01:00
Furquan Shaikh a89254801c mainboard/google/poppy: Enable cros_ec_keyb device
This is required to transmit button information from EC to kernel.

BUG=b:35774934
BRANCH=None
TEST=Verified using evtest that kernel is able to get button
press/release information from EC.

Change-Id: I8f380f935c2945de9d8e72eafc877562987d02db
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18642
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2017-03-09 07:31:17 +01:00
Furquan Shaikh d4a0a348e4 google/chromeec: Add support for cros_ec_keyb device
This is required to pass button information from EC to kernel without
using 8042 keyboard driver.
1. Define EC buttons device using GOOG0007 ACPI ID.
2. Guard enabling of this device using EC_ENABLE_MKBP_DEVICE.

BUG=b:35774934
BRANCH=None
TEST=Verified using evtest that kernel is able to get button
press/release information from EC.

Change-Id: I4578f16648305350d36fb50f2a5d2285514daed4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18641
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2017-03-09 07:31:04 +01:00
Andrey Petrov b1aded2f0c soc/intel/apollolake: Add check if FPFs are blown
Apollolake platform comes with FPF (field-programmable-fuses). FPF can
be blown only once, typically at the end of the manufacturing process.
This patch adds code that sends a request to CSE to figure out if FPFs
have already been blown.

Change-Id: I9e768a8b95a3cb48adf66e1f17803c720908802d
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/18604
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2017-03-09 04:41:44 +01:00
Andrey Petrov d8db26d6e7 soc/intel/apollolake: Start using common CSE driver
Change-Id: If866453f06220e0edcaa77af5f54b397ead3ac14
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/18603
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2017-03-09 04:40:49 +01:00
Andrey Petrov 04a72c4019 soc/intel/common/block: Add HECI driver
Add common driver that can send/receive HECI messages. This driver is
inspired by Linux kernel mei driver and somewhat based on Skylake's.
Currently it has been only tested on Apollolake.

BUG=b:35586975
BRANCH=reef
TEST=tested on Apollolake to send single messages and receive both
fragmented and non-fragmented versions.

Change-Id: Ie3772700270f4f333292b80d59f79555851780f7
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/18547
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2017-03-09 04:40:12 +01:00
Andrey Petrov fba7489574 soc/intel/apollolake: Prepare to use common HECI driver
Change-Id: Ib284493d886b223e8c85607de5fdb56b698fe5fa
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/18546
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-09 04:40:00 +01:00
Martin Roth 010905ed2f uti/lint/checkpatch: Fix __attribute__ struct errors for OPEN_BRACE
The __attribute__((weak)) lines on structs were being read as functions,
causing a warning that the brace should be on the next line.
Add a check to see if it's a struct with an attribute, and ignore it for
the OPEN_BRACE check if it is.

Change-Id: Ieb0c96027e8df842f60ca7c9de7aac941eed1dc2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18570
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
2017-03-09 04:37:43 +01:00
Martin Roth 2e17eaed1b checkpatch.conf: Update rules
- Remove the "MISSING_SPACE" check which checks for breaks at a space in
a string concatenation.  Most of the time this makes sense, but we
occasionally need to break where there isn't a space, so having a hard
rule doesn't always work.

- Don't check the vendorcode directory for compliance to coreboot's
code format rules.

Change-Id: Ic07677b19520b5d22363834c77f5dee7bba9e429
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18569
Tested-by: build bot (Jenkins)
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-03-09 04:37:28 +01:00
Martin Roth a3cac87ea8 uti/lint/checkpatch: add --exclude to ignore specific directories
checkpatch: add option for excluding directories
when importing code from external sources

Using --exclude <dir> we should be able to exclude a list of well
defined locations in the tree that carry sources from other projects
with other styles.

This comes from the 01org/zephyr project in github:
Original-Change-Id: I7d321e85eed6bc37d5c6879ae88e21d20028a433
Original-Signed-off-by: Anas Nashif <anas.nashif@intel.com>

Change-Id: Icc9e841e7d84026d6ab857ff90b0f093515ccaad
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18568
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-03-09 04:37:11 +01:00
Lee Leahy d638ef4ec4 src/lib: Remove spaces after ( and before )
Fix the following errors detected by checkpatch.pl:

ERROR: space prohibited after that open parenthesis '('
ERROR: space prohibited before that close parenthesis ')'

TEST=Build and run on Galileo Gen2

Change-Id: I586c5731c080282080fe5ddf3ac82252cb35bdd4
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18636
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-09 00:51:26 +01:00
Furquan Shaikh 40d4089f5c mainboard/google/poppy: Add EC_HOST_EVENT_MODE_CHANGE to wakeup source
Allow EC mode change event to wake AP up in S3.

BUG=b:35775085
BRANCH=None
TEST=Compiles successfully for poppy.

Change-Id: I6f1546c60aef6620e22cdce2fab3a2709e6556a1
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18608
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-08 20:52:00 +01:00
Duncan Laurie f8401cddb8 chromeos/elog: Filter developer mode entry on S3 resume
The event log entry indicating developer mode is useful for the
boot path, but is not really useful on the resume path and removing
it makes the event log easier to read when developer mode is enabled.

To make this work I have to use #ifdef around the ACPI code since
this is shared with ARM which does not have acpi.h.

BUG=b:36042662
BRANCH=none
TEST=perform suspend/resume on Eve and check that the event log
does not have an entry for Chrome OS Developer Mode.

Change-Id: I1a9d775d18e794b41c3d701e5211c238a888501a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18665
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2017-03-08 19:08:45 +01:00
Duncan Laurie ac2cbd0ffb intel/skylake: Filter suspend well power failure event for Deep Sx
If Deep Sx is enabled the event log will get entries added on every
power sequence transition indicating that the suspend well has failed.

When a board is using Deep Sx by design this is intended behavior and
just fills the logs with extraneous events.

To make this work the device init state has to be executed first so it
actually enables the Deep Sx policies in the SOC since this code does
not have any hooks back into the devicetree to read the intended setting
from there.

BUG=b:36042662
BRANCH=none
TEST=Perform suspend/resume on Eve device with Deep S3 enabled, and
then check the event log to be sure that it does not contain the
"SUS Power Fail" event.

Change-Id: I3c8242baa63685232025e1dfef5595ec0ec6d14a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18664
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-08 19:08:09 +01:00
Duncan Laurie cb76d50f0d intel/skylake: Add function to read state of Deep S5
Add a function to read the current state of Deep S5 configuration
and indicate if it is enabled (for AC and/or DC) or disabled.

This is similar to the existing function that checks Deep S3
enable state.

BUG=b:36042662
BRANCH=none
TEST=tested with subsequent commits to check Deep S5 state at boot
and filter event log messages if it is enabled.

Change-Id: I4b60fb99a99952cb3ca6be29f257bb5894ff5a52
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18663
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-08 19:07:49 +01:00
Duncan Laurie b2aac85030 intel/skylake: Add devicetree settings for acoustic noise mitigation
Add options to the skylake chip config that will allow tuning the
various settings that can affect acoustics with the CPU and its VRs.

These settings are applied inside FSP, and they can adjust the slew
slew rate when changing voltages or disable fast C-state ramping on
the various CPU VR rails.

BUG=b:35581264
BRANCH=none
TEST=these are currently unused, but I verified that enabling the
options can affect the acoustics of a system at runtime.

Change-Id: I6a8ec0b8d3bd38b330cb4836bfa5bbbfc87dc3fb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18662
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2017-03-08 19:07:37 +01:00
Duncan Laurie 03df460af5 google/eve: Configure GPIOs for new board
A new board revision is making use of two previously unused GPIOs
to drive BOOT/RESET pins to an on-board MCU.

The reset pin is open drain so it is set as input by default, and
the boot pin is driven low by default.

Since these are UART0 pins they also need to be set up again after
executing FSP-S as it will change them back to native mode pins.

BUG=b:36025702
BRANCH=none
TEST=manual testing on reworked board, toggling GPIOs to put
the MCU into programming mode.

Change-Id: Id6f0ef2f863bc1e873b58e344446038786b59d25
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18661
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2017-03-08 19:07:29 +01:00
Patrick Rudolph b854ae2649 libpayload-x86: Enable SSE and FPU when present
Allows to use SSE and floating point in payloads without digging to
much into x86 assembly code.

Tested on Lenovo T500 (Intel Core2Duo).
Both floating point operation and SSE is properly working.

Change-Id: I4a5fc633f158de421b70435a8bfdc0dcaa504c72
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18345
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-08 04:44:12 +01:00
Stefan Tauner f13bd41c50 nb/intel/nehalem/raminit.c: Refine broken comment
Change-Id: Ic5c92d9a2d8bb040a04602e5da2cd37a2ae8db95
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/18052
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-08 04:42:28 +01:00
Wisley Chen e4c85c128a mainboard/google/snappy: Override USB2 phy setting
Fine tune USB2, need to override the following registers.

port#1:
  PERPORTPETXISET=7
  PERPORTTXISET=0

BUG=b:35858164
BRANCH=reef
TEST=built, measured eye diagram on snappy, and reviewed by intel

Change-Id: I461cf8f032b4e70abc9707e6cd3603a62cee448f
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/18590
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-08 04:37:30 +01:00
Huan Truong 8c247a2a79 util/intelmetool: Add support for Wildcat Point LP
This adds support for the Wildcat Point LP for intelmetool.

When the tool detected a Wildcat Point LP,
then the ME will be reported as  difficult-to-remove.

Change-Id: I35423db11cdc1e21e7f02ce90dace7fb4d236c45
Signed-off-by: Huan Truong <htruong@tnhh.net>
Reviewed-on: https://review.coreboot.org/18575
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-03-08 04:36:04 +01:00
Huan Truong 2a1ae05316 util/intelmetool: Fix segfault on edge cases
The intel ME checker tool would segfault if it reaches the end of
the loop without having the dev pointer set. This happens when
it gets to the end of the previous loop without knowing what to do
with any of the devices it sees.

This patch makes sure the pointer is not NULL before accessing it.

Change-Id: Ia13191799d7e00185947f9df5188cb2666c43e2a
Signed-off-by: Huan Truong <htruong@tnhh.net>
Reviewed-on: https://review.coreboot.org/18573
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-08 04:34:34 +01:00
Martin Roth 954338d21b MAINTAINERS: Update list
- Fix whitespace: Change some spaces to tabs
- Add myself as an abuild maintainer
- Add util/xcompile and util/genbuild_h to the BUILD SYSTEM section
- Add new sections for utilities: docker, toolchain, and git
- Remove GENERIC DRAM section
- Remove the mailing list.  We don't want it to be added as a reviewer.

Change-Id: I78692fcac174d7b7c4d65911c85e4e2dacefcfc0
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18578
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-03-08 04:33:30 +01:00
Kyösti Mälkki 97a4b3edf0 binaryPI platforms: Drop any ACPI S3 support
No board with binaryPI currently supports HAVE_ACPI_RESUME. For
platforms with PSP the approach is also very different from what
we previously had here.

Furthermore, s3_resume.[ch] files under cpu/amd/pi do not
distinguish between NonVolatile and Volatile buffers of S3 storage.
This means the Volatile buffer that is maintained and available in
CBMEM is unnecessarily copied to SPI flash. This has been fixed on
open-source AGESA directory, so development of S3 suspend support
with binaryPI is better continued with that.

Unfortunately there are further complications and indications that
open-source AGESA may have always had a low-memory corruption
issue. This has to be investigated separately before restoring
or claiming S3 is supported on binaryPI.

Change-Id: I81585fff7aae7bcdd55e5e95bc373e0adef43ef0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18501
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-03-08 04:08:29 +01:00
Kyösti Mälkki 1b183aa6ce binaryPI boards: Drop any ACPI S3 support
None of the boards currently have HAVE_ACPI_RESUME and
and ACPI S3 support calls should not appear under board
directories anyways.

Change-Id: I1abd40ddba64be25b823abf801988863950c1eb5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18500
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-03-08 04:08:00 +01:00
Kyösti Mälkki 3444a9d716 AGESA fam10: Add missing include
The file is used for fam15.

Change-Id: I7cdf238a8f7be4bf79546bcfc3c9d05bd8986e3e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18635
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-03-08 03:21:01 +01:00
Kyösti Mälkki da74041b2b AGESA: Move heap allocator declarations
Definitions are not part of ACPI S3 feature, nor do
they require any AGESA headers so move them to a
better location.

Change-Id: I9269e9d65463463d9b8280936cf90ef76711ed4f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18616
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-03-08 03:20:27 +01:00
Kyösti Mälkki 8e1f908ce0 AMD geode: Avoid conflicting main() declaration
Declaration of main in cpu/amd/car.h conflicts with the
definition of main required for x86/postcar.c in main_decl.h.

Change-Id: I19507b89a1e2ecf88ca574c560d4a9e9a3756f37
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18615
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-03-08 03:19:46 +01:00
Kyösti Mälkki 07bc9f76bc mainboard/asus: Move F2A85-M_LE variant to F2A85-M.
Note that M and M_PRO had same DefaultPlatformMemoryConfiguration
defined, use one for both.

Change-Id: Ia1925957800a7fe6ef511b2d041f7a863c8fc931
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18606
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-03-08 03:19:21 +01:00
Marshall Dawson 03e6a455a3 amd/pi/hudson: Move APIC enable to CPU file
Relocate the enabling of the LAPIC out of the southbridge source and
surround it with a check for CONFIG_UDELAY_LAPIC (typical for AMD
systems).  The LAPIC is now enabled for all cores; not only the BSP,
and not only when the UART is used.

This solves the problem of APs not having their APICs enabled when
the timer is expected to be functional, e.g. verstage often uses
do_printk_va_list() instead of do_printk() which exits early for
APs when CONFIG_SQUELCH_EARLY_SMP=y.

The changes were tested with two Gardenia builds, one using verstage
and another with CONFIG_SQUELCH_EARLY_SMP=n.

Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 93ffc311165f19d4192a5489051fa4264cd8e0ad)

Change-Id: Ieaecc0bf921ee0d2691a8082f2431ea4d0c33749
Signed-off-by: Marc Jones <marcj303@gmail.com>
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/18436
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-07 23:06:55 +01:00
Marc Jones a0891ee367 amd/pi/hudson/acpi: Only declare S3 if it is supported
Only declare S3 support in ACPI if CONFIG_HAVE_ACPI_RESUME
is set.

Change-Id: I6f8f62a92478f3db5de6feaa9822baad3f8e147e
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/18493
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-07 23:05:59 +01:00
Marshall Dawson 91dea4a648 amd/pi/hudson: Add early SPI setup
Add some generic functions that can configure the SPI interface to
have faster performance.

Given that the hudson files are used across many generations of FCHs,
make sure to refer to the appropriate BKDG or RRG before using the
functions.  Notable differences:
 * Hudson 1 defines read mode in CNTRL0 differently than later gens
 * Hudson 1 supports setting NormSpeed in Cntr1 but Hudson3 allows
   setting FastSpeed as well
 * Kabini, Mullins, Carrizo and Stoney Ridge contain a "new" SPI100
   controller

Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 1922d6f424dcf1f42e2f21fb7c6d53d7bcc247d0)

Change-Id: Id12440e67bc575dbe4b980ef1da931d7bfae188d
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/18442
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-07 23:01:36 +01:00
Marshall Dawson 7b0b9f0d41 amd/pi/hudson: Add SPI definitions to header
Add defines that will be used later for setting the fastest settings
in the SPI controller.

Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 0d2c28b8156dcc1f3dc925b3c3ba15b6b07f202c)

Change-Id: I660cc9ed6910c33042321c80453c7f74912455d9
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/18441
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-07 23:01:15 +01:00
Marshall Dawson d8019a67bf amd/pi/hudson: Consolidate BITn definitions
Remove unused definitions from a .c file and use the BIT(n) macro
found in types.h instead.  Convert existing definitions to BIT(n).

Orignial-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit f403d12b49985ee9d9b339a6659b60ef1560519c)

Change-Id: I24105bf75263236dbdbc2666f03033069d1d36d2
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/18440
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-07 22:58:05 +01:00