Fix the values that were off by one.
This was discovered when using postcar stage that prints with
debuglevel BIOS_NEVER.
Change-Id: I73a077950ed0dc735d89c9747a8da0a25f30822d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Some fam14 boards will need more work on this area,
those are to be addressed with followup patches.
Change-Id: I14208cf8519a4cf71e4944d08a2dae36b7f1f878
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
There have been discussions about removing this since it does not seem
to be used much and only creates troubles for boards without defaults,
not to mention that it was configurable on many boards that do not
even feature uart.
It is still possible to configure the baudrate through the Kconfig
option.
Change-Id: I71698d9b188eeac73670b18b757dff5fcea0df41
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
All thse Option.*Install.h files are about configuring
what eventually is referenced in the final libagesa
build. It's self-contained so isolate these together
with PlatformInstall.h to hide them from rest of
the build.
Change-Id: Id9d90a3366bafc1ad01434599d2ae1302887d88c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It was not intentional to change oem_fan_control() to non-static
with commit
23e5ba9 binarypi mainboards: Clean up IS_ENABLED fan control
Every platform except bettong had its own static version of
oem_fan_control, so remove the definition of oem_fan_control from imc.h,
and move it out of imc.c into bettong's BiosCallOuts.c.
Change-Id: Ie95ac1fd3a57259bb35796903aa8753ef0e70d70
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21189
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove all checks for #if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) around
the imc.h includes. Convert from #if to if() for all fan control
setup code. Where necessary, make functions non-static to match the
prototypes in imc.h.
Change-Id: If88af42d00227285931829441909a982fc292b2b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Remove all checks for #if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) around
the imc.h includes. Convert all #if to if() for fan control setup.
Change-Id: I04a9fbbf6f64f45e1a0b544267bfe840ce7fa1d9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
SSFG was meant to be used as a mask to enable sleep states
_S1 thru _S4. However as a logical instead of bitwise 'and'
operation was used, all the states were enabled if only
one was marked available.
State _S3 is now set conditionally if HAVE_ACPI_RESUME=y.
For pi/hudson this had been fixed already preprocessor.
Note that all boards had SSFG == 0x0D that previously
enabled ACPI S3 sleep state even when it was not available.
States _S1 and _S2 still appear enabled in ASL/AML
but may not actually work.
TEST: 'cat /sys/power/state' and notice choice 'mem' was
removed from the list of available sleep states.
Change-Id: I27d616871c1771f0c87d8fba23d4ce1569607765
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
We define BINARYPI_LEGACY_WRAPPER a method of calling AGESA
via functions in agesawrapper.c file. The approach implemented
there makes it very inconvenient to do board-specific
customisation or present common platform-specific features.
Seems like it also causes assertion errors on AGESA side.
The flag is applied here to all boards and then individually
removed one at a time, as things get tested.
New method is not to call AGESA internal functions directly,
but via the dispatcher. AGESA call parameters are routed to
hooks in both platform and board -directories, to allow for
easy capture or modification as needed.
For each AGESA dispatcher call made, eventlog entries are
replayed to the console log. Also relocations of AGESA heap
that took place are recorded.
New method is expected to be compatible with binaryPI.
Change-Id: I2900249e60f21a13dc231f4a8a04835e090109d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We define AGESA_LEGACY_WRAPPER a method of calling AGESA
via functions in agesawrapper.c file. The approach implemented
there makes it very inconvenient to do board-specific
customisation or present common platform-specific features.
Seems like it also causes assertion errors on AGESA side.
The flag is applied here to all boards and then individually
removed one at a time, as things get tested.
New method is not to call AGESA internal functions directly,
but via the dispatcher. AGESA call parameters are routed to
hooks in both platform and board -directories, to allow for
easy capture or modification as needed.
For each AGESA dispatcher call made, eventlog entries are
replayed to the console log. Also relocations of AGESA heap
that took place are recorded.
New method is expected to be compatible with binaryPI.
Change-Id: Iac3d7f8b0354e9f02c2625576f36fe06b05eb4ce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Calling disable_cache_as_ram() with valuables in stack is not
a stable solution, as per documentation AMD_DISABLE_STACK
should destroy stack in cache.
While we still preserve cache contents (there is wbinvd deep
inside AMD_DISABLE_STACK macro), we now actually do a stack
switch and much more closely meet the specification of CAR
teardown sequence in AGESA specifications.
We now somewhat incorrectly include files from agesa/ tree,
but the whole agesawrapper.c file removal will address the
issue of overall directory layout.
Change-Id: I2bac098099c1caffea181356c63924f4b5a93b54
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We remove this particular header file already while remaining
of include fixes is longterm and pending work.
Change-Id: I869d426c1344290a00e2df60e07e9a4a3ae26887
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This requires to also unify the calling convention for
AGESA functions from
AGESA_STATUS (*agesa_func)(UINT32 Func, UINT32 Data, VOID *ConfigPtr)
to
AGESA_STATUS (*agesa_func)(UINT32 Func, UINTN Data, VOID *ConfigPtr)
On systems running 32bit x86 code this will not make a difference as
UINTN is uintptr_t which is 32bit on these machines.
Change-Id: I095ec2273c18a9fda11712654e290ebc41b27bd9
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
We define AGESA_LEGACY as an implementation of mainboard
that has its romstage main completely under mainboard/
directory. We have learnt from other platforms this approach
has several downsides when it comes to making platform-wide
improvements.
We start by creating per-family romstage.c file, which
boards will gradually take into use by removing the
AGESA_LEGACY Kconfig option we here apply to all of them.
Change-Id: Id01931e185a023039a60af16a678de9966db8d65
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18619
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Martin Roth <martinroth@google.com>
None of the boards currently have HAVE_ACPI_RESUME and
and ACPI S3 support calls should not appear under board
directories anyways.
Change-Id: I1abd40ddba64be25b823abf801988863950c1eb5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18500
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
These definitions do not require AGESA.h include,
and we will eventually remove agesawrapper.h files.
Change-Id: I1b5b78409828aaf2616e177bb54a054960c3869f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18588
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
It's an attempt to consolidate the access code, even if there are still
multiple implementations in the code.
Change-Id: I4b2b9cbc24a445f8fa4e0148f52fd15950535240
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/18265
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since it checks for DDR3 style checksums, it's a more appropriate name.
Also make its configuration local for a future code move.
Change-Id: I417ae165579618d9215b8ca5f0500ff9a61af42f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/18264
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Also make sure that no board changes behaviour because of that by adding
a static assert.
TEST=abuild over all builds still succeeds (where it doesn't if
DIMM_SPD_SIZE isn't set to 128 bytes for boards that use the
device/dram code).
Change-Id: Iddb962b16857ee859ddcf1b52d18da9b3be56449
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/18254
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Make the ending comment associated with "chip ...hudson" match the
appropriate directory name.
Change-Id: I5e0d6d41a2e3f963760aad08ed6108acac5b66b3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17904
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
These headers & comments indicating a lack of functionality don't help
anything. We discourage copyrights and licenses on empty files, so
just clear these.
Change-Id: Id2ab060a2726cac6ab047d49a6e6b153f52ffe6d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17657
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Vendorcode always does PCI MMCONF access once it is
enabled via MSR.
In coreboot proper, we don't give opportunity to make
pci_read/write calls before PCI MMCONF is enabled via MSR.
This happens early in romstage amd_initmmio() for all cores.
Change-Id: Id6ec25706b52441259e7dc1582f9a4ce8b154083
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17534
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Vendorcode always does PCI MMCONF access once it is
enabled via MSR.
In coreboot proper, we don't give opportunity to make
pci_read/write calls before PCI MMCONF is enabled via MSR.
This happens early in romstage amd_initmmio() for all cores.
Change-Id: If31bc0a67b480bcc1d955632f413f5cdeec51a54
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17533
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since commit 3bfd7cc (drivers/pc80: Rework normal / fallback selector
code) the reboot counter stored in `reboot_bits` isn't reset on a reboot
with `boot_option = 1` any more. Hence, with SKIP_MAX_REBOOT_CNT_CLEAR
enabled, later stages (e.g. payload, OS) have to clear the counter too,
when they want to switch to normal boot. So change the bits to (h)ex
instead of (r)eserved.
To clarify their meaning, rename `reboot_bits` to `reboot_counter`. Also
remove all occurences of the obsolete `last_boot` bit that have sneaked
in again since 24391321 (mainboard: Remove last_boot NVRAM option).
Change-Id: Ib3fc38115ce951b75374e0d1347798b23db7243c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/16157
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-by: York Yang <york.yang@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This patch adds two SPD files with different DDR3 clk settings.
The user can choose which setting to use.
Lower clk settings saves power under load.
SoC Model GX-411GA supports only up to DDR3-1066 clk mode.
Both SPD settings were tested with memtest for several hours.
Power saving is around half a watt under heavy memory load.
Payload SeaBIOS 1.9.1 stable, Lubuntu 16.04, Kernel 4.4.0
Change-Id: Ibb81e22e19297fdf64360bc3e213529e9d183586
Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com>
Reviewed-on: https://review.coreboot.org/15907
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
