Add definitions to describe GPIOs in generated ACPI objects and a
method to write a GpioIo() or GpioInt() descriptor to the SSDT.
ACPI GPIOs have many possible configuration options and a structure
is created to describe it accurately in ACPI terms. There are many
shared descriptor fields between GpioIo() and GpioInt() so the same
function can write both types.
GpioInt shares many properties with ACPI Interrupts and the same types
are re-used here where possible. One addition is that GpioInt can be
configured to trigger on both low and high edge transitions.
One descriptor can describe multiple GPIO pins (limited to 8 in this
implementation) that all share configuration and controller and are
used by the same device scope.
Accurately referring to the GPIO controller that this pin is connected
to requires the SoC/board to implement a function handler for
acpi_gpio_path(), or for the caller to provide this directly as a
string in the acpi_gpio->reference variable.
This will get used by device drivers to describe their resources in
the SSDT. Here is a sample for a Maxim 98357A I2S codec which has a
GPIO for power and channel selection called "sdmode".
chip.h:
struct drivers_generic_max98357a_config {
struct acpi_gpio sdmode_gpio;
};
max98357a.c:
void acpi_fill_ssdt_generator(struct device *dev) {
struct drivers_generic_max98357a_config *config = dev->chip_info;
...
acpi_device_write_gpio(&config->sdmode_gpio);
...
}
devicetree.cb:
device pci 1f.3 on
chip drivers/generic/max98357a
register "sdmode_gpio" = "ACPI_GPIO_OUTPUT(GPP_C5)"
device generic 0 on end
end
end
SSDT.dsl:
GpioIo (Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly,
"\\_SB.PCI0.GPIO", 0, ResourceConsumer, ,) { 53 }
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Ibf5bab9c4bf6f21252373fb013e78f872550b167
Reviewed-on: https://review.coreboot.org/14934
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add definitions for ACPI device extended interrupts and a method to
write an Interrupt() descriptor to the SSDT output stream.
Interrupts are often tied together with other resources and some
configuration items are shared (though not always compatibly) with
other constructs like GPIOs and GPEs.
These will get used by device drivers to write _CRS sections for
devices into the SSDT. One usage is to include a "struct acpi_irq"
inside a config struct for a device so it can be initialized based
on settings in devicetree.
Example usage:
chip.h:
struct drivers_i2c_generic_config {
struct acpi_irq irq;
};
generic.c:
void acpi_fill_ssdt_generator(struct device *dev) {
struct drivers_i2c_generic_config *config = dev->chip_info;
...
acpi_device_write_interrupt(&config->irq);
...
}
devicetree.cb:
device pci 15.0 on
chip drivers/i2c/generic
register "irq" = "IRQ_EDGE_LOW(GPP_E7_IRQ)"
device i2c 10 on end
end
end
SSDT.dsl:
Interrupt (ResourceConsumer, Edge, ActiveLow, Exclusive,,,) { 31 }
Change-Id: I3b64170cc2ebac178e7a17df479eda7670a42703
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14933
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Depending on which options are selected there needs to be certain
functions supplied. However, the spi, mmap_boot, and tsc_freq modules
were not included in the SMM builds. Fix the omission.
Change-Id: I25ab42886cfd46770ce0f4beee65f2f4d15649f3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14977
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
An updated descriptor expands the BIOS region while descreasing
the 'device expansion region' utilized by the CSE. Update the
end region marker to reflect this new size as well as the
chromeos.fmd file which needs to be adjusted for logical boot
parition 2 requirement which resides halfway through the BIOS
region. The GBB was moved and shunk to accommodate the change.
Change-Id: I7baa5282d7c608af648b5773c4dfa123060a6e45
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14974
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
The chromeos.c suport needs to be linked into verstage so it will
link.
Change-Id: If85e232a3721443edfbbd278b32f72302f13f3a8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14973
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
There previously was no support for building verstage on apollolake.
Add that suport by linking in the appropriate modules as well as
providing vboot_platform_is_resuming(). The link address for verstage
is the same as FSP-M because they would never be in CAR along side
each other. Additionally, program the ACPI I/O BAR and enable decoding
so sleep state can be determined for early firmware verification.
Change-Id: I1a0baab342ac55fd82dbed476abe0063787e3491
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14972
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
When CONFIG_C_ENVIRONMENT_BOOTBLOCK is employed there's no need for
a chipset specific verstage entry point because cache-as-ram has
already been initialized. Therefore, provide a default entry point
for verstage in that environment.
Change-Id: Idd8f45bd58d3e5b251d1e38cca7ae794b8b77a28
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14971
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
BUG=none
TEST=Boot to OS and verfiy if rtc0 device is created
under /sys/class/rtc/
Change-Id: Idec569255859816fda467bb42a215c00f7c0e16e
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://review.coreboot.org/14883
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since fit.c is the only caller of this function move it out of common.c
and into fit.c.
Change-Id: I64cc31a6d89ee425c5b07745ea5ca9437e2f3fcf
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/14949
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
By design, FSP will send POST codes to port 80. In this case we have
both coreboot and FSP pushing post codes, which may make debugging
harder. In order to get a clear picture of where FSP execution begins
and ends, send post codes before and after any call to the FSP blobs.
Note that sending a post code both before and after is mostly useful
on chromeec enabled boards, where the EC console will provide a
historic list of post codes.
Change-Id: Icfd22b4f6d9e91b01138f97efd711d9204028eb1
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14951
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The previous code harded the suffix of splash file as
"jpg". Actually, SeaBIOS supports both jpg and bmp.
Change-Id: I06c4b14aae7f75be3406652a94612b5f30ce91c2
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/14932
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The NB_DEV_ROOT macro, is almost unreadable, as it depends on other
stringified macros, and acts differently depending on the coreboot
stage. For ramstage, it also hides a function call.
Rewrite the macro in terms of more basic and readable macros.
Change-Id: I9b7071d67c8d58926e9b01fadaa239db1120448c
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14890
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
memmap.c functionality is designed to be used in more than ramstage.
Therefore, it cannot use ramstage-specific APIs. In this case, the
SIMPLE_DEVICE API offers a more consistent behavior across stages.
Change-Id: Ic381fe1eb773fb0a5fb5887eb67d2228d2f0817d
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14953
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
1. Configure GPIO_199 and GPIO_200 as NF2 to work as HPD.
2. Make 20k Pullup and remove duplicate code.
Change-Id: I8c78d867b03d5f2a6f02165c20777ae25e352ce7
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
Reviewed-on: https://review.coreboot.org/14899
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Providing an option to enable or disable ISH interface. Leaving it
disabled for now.
Change-Id: Id4e71d60a6c2da6c6c070d41f66f6c161de38595
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/14895
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Also initialize IshEnable in Silicon Init UPD with the value from
devicetree.cb
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Change-Id: I8f57a7353471cc3efa21c7011cdd0b369d25275d
Reviewed-on: https://review.coreboot.org/14894
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Increase BIOS region size by 512KB since device extension size
is reduced from 1MB to 512KB
BUG=chrome-os-partner:52589
TEST=Build Coreboot and boots
CQ-DEPEND=CL:*259448,CL:345642,CL:*259445
Change-Id: Ib81b117a3afe730aafa54b4ef31b1e9ab1f67111
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/14929
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Provide default handler for some SMI events. Provide the framework for
extracting data from SMM Save State area for processors with SMM revision
30100 and 30101.
The SOC specific code should initialize southbridge_smi with event
handlers. For SMM Save state handling, SOC code should implement
get_smm_save_state_ops which initializes the SOC specific ops for SMM Save
State handling.
Change-Id: I0aefb6dbb2b1cac5961f9e43f4752b5929235df3
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/14615
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When the vboot cbfs selection runs in postcar stage it should be
utilizing cbmem to locate the vboot selected region.
Change-Id: I027ba19438468bd690d74ae55007393f051fde42
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14959
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
The current code was using !__PRE_RAM__ as a proxy for ramstage
conditional compilation. In the face of postcar stage not defining
__PRE_RAM__ (because it's after RAM is up) these code paths
can fail to compile with a __SIMPLE_DEVICE__ defined for the entire
stage. Remedy the current situation by just compiling explicity for
ramstage because that was the original intent. In the future,
the __SIMPLE_DEVICE__ selection for postcar can also be re-evaluated.
Change-Id: I0f887f1e45f0cf5c235ae5144eaa227921e7119b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14958
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Turn on the USB device port.
TEST=Build and run on Galileo Gen2
Change-Id: Ic1fbb2cd51414ce927f2b408ccd27c7edf978744
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14943
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Add initialization for the USB device port.
TEST=Build and run on Galileo Gen2
Change-Id: Icf83747f778f6e1ac976cd448a94311030e79e4f
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14941
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Some exceptions (like from calling a NULL function pointer) are easier
to narrow down with a dump of the call stack. Let's take a page out of
ARM32's book and add that feature to ARM64 as well. Also change the
output format to two register columns, to make it easier to fit a whole
exception dump on one screen.
Applying to both coreboot and libpayload and syncing the output format
between both back up.
Change-Id: I19768d13d8fa8adb84f0edda2af12f20508eb2db
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14931
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Elan trackpad needs greater sda hold time.
Configure IC_SDA_HOLD register to increase
the i2c sda hold time by 0.3us.
Change-Id: I3d966eed62a059ecb6a0a88e9f4e6b4ba7a925e4
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://review.coreboot.org/14922
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move the EHCI errata from QuarkFSP into coreboot.
TEST=Build and run on Galileo Gen2
Change-Id: I424ffd81643fbba9c820b5a8a6809b9412965f8d
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14940
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Rename usb.c to ehci.c since it contains EHCI specific content.
TEST=Build and run on Galileo Gen2
Change-Id: Ifdb7cd937b1dffda1959b76e1c911ffd93f53cb6
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14939
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Switch from using uart_dev to uart_bdf to better describe the value
in use.
TEST=Build and run on Galileo Gen2
Change-Id: If5066b93ea8ccce4a5b89ee3984c7413d5358e71
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14938
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
On apollolake the boot media layout is different in that the
traditional "BIOS" region contains another data structure with
the boot assets such as CSE firmware, PMC microcode,
CPU microcode, and boot firmware to name a few. There's also a
sort of recovery mechanism where there is a second data structure
with similar contents halfway through the "BIOS" region. This
second structure is referred as the logical boot partition 2 (LBP2),
and it's optionally employed.
Add support for writing the LBP2 to a specified FMAP region to
accommodate platforms which require it.
Change-Id: I1959a790f763b409238dea6b62408b42122e590e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14924
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Add a handler for soc/intel/apollolake to return the ACPI path for
GPIOs. There are 4 GPIO "communities" on apollolake that each have a
different ACPI device so return the appropriate name for the different
communities.
Change-Id: I596c178b7813ac6aaeb4f2685bb916f5b78e049b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14859
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a handler for the Intel Skylake SOC to return the ACPI path for
GPIOs. Since all GPIOs are handled by the same controller they all
have the same ACPI path and this is a simple handler that just returns
a pointer to the GPIO device that is defined in the DSDT.
Change-Id: I24ff3a6f2479d9e7eeace65d49e2f6c2e070f3e9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14843
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Add a new function "gpio_acpi_path()" that can be implemented by
SoC/board code to provide a mapping from a "gpio_t" pin to a
controller by returning the ACPI path for the controller that owns
this particular GPIO.
This is implemented separately from the "acpi_name" handler as many
SOCs do not have a specific device that handles GPIOs (or may have
many devices and the only way to know which is the opaque gpio_t)
and the current GPIO library does not have any association with the
device tree.
If not implemented (many SoCs do not implement the GPIO library
abstraction at all in coreboot) then the default handler will return
NULL and the caller knows it cannot determine this reliably.
Change-Id: Iaa0ff6c8c058f00cddf0909c4b7405a0660d4cfb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14842
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Add a global ACPI device name handler for the Skylake SOC that will
translate skylake device paths into an ACPI path that matches the
device objects delcared in the DSDT at soc/intel/skylake/acpi/*.
The skylake implementation uses a global acpi_name handler for the
SOC and it is not necessary to add a function to every device.
This function is used by device drivers calling acpi_device_name()
and acpi_device_path() to generate ACPI AML in the SSDT.
Change-Id: I31cecf7905a51224e7bfc40c6c4ad2487f039097
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14841
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Add a function to "struct device_operations" to return the ACPI name
for the device, and helper functions to find this name (either from
the device or its parent) and to build a fully qualified ACPI path
from the root device.
This addition will allow device drivers to generate their ACPI AML in
the SSDT at boot, with customization supplied by devicetree.cb,
instead of needing custom DSDT ASL for every mainboard.
The root device acpi_name is defined as "\\_SB" and is used to start
the path when building a fully qualified name.
This requires SOC support to provide handlers for returning the ACPI
name for devices that it owns, and those names must match the objects
declared in the DSDT. The handler can be done either in each device
driver or with a global handler for the entire SOC.
Simplified example of how this can be used for an i2c device declared
in devicetree.cb with:
chip soc/intel/skylake # "\_SB" (from root device)
device domain 0 on # "PCI0"
device pci 19.2 on # "I2C4"
chip drivers/i2c/test0
device i2c 1a.0 on end # "TST0"
end
end
end
end
And basic SSDT generating code in the device driver:
acpigen_write_scope(acpi_device_scope(dev));
acpigen_write_device(acpi_device_name(dev));
acpigen_write_string("_HID", "TEST0000");
acpigen_write_byte("_UID", 0);
acpigen_pop_len(); /* device */
acpigen_pop_len(); /* scope */
Will produce this ACPI code:
Scope (\_SB.PCI0.I2C4) {
Device (TST0) {
Name (_HID, "TEST0000")
Name (_UID, 0)
}
}
Change-Id: Ie149595aeab96266fa5f006e7934339f0119ac54
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14840
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
acpigen_write_uuid() will generate a ToUUID() 128-bit buffer object for a
common universally unique identifier that is passed as a string. The
resulting buffer is the UUID in byte format with a specific order of the
bytes as described in the ACPI specification:
ToUUID (uuid)
Compiles to:
Buffer (16) { uuid[3], uuid[2], uuid[1], uuid[0], uuid[5], uuid[4],
uuid[7], uuid[6], uuid[8], uuid[9], uuid[10], uuid[11],
uuid[12], uuid[13], uuid[14], uuid[15] }
Change-Id: Ibbeff926883532dd78477aaa2d26ffffb6ef30c0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14838
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This function will turn a string of ASCII hex characters into an array
of bytes. It will ignore any non-ASCII-hex characters in the input
string and decode up to len bytes of data from it.
This can be used for turning MAC addresses or UUID strings into binary
for storage or further processing.
Sample usage:
uint8_t buf[6];
hexstrtobin("00:0e:c6:81:72:01", buf, sizeof(buf));
acpigen_emit_stream(buf, sizeof(buf));
Change-Id: I2de9bd28ae8c42cdca09eec11a3bba497a52988c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14837
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Certain mainboards, e.g. the ASUS KGPE-D16/KCMA-D8, require
board-specific configuration changes to the SuperIO. Expose
the functions needed to enter and exit configuration mode
on Winbond devices.
Change-Id: Ic86651872ecafcfe1398201be2b0768bbe460975
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14891
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The src/acpi/Kconfig was being sourced close to the top of the Kconfig
tree, which doesn't allow it to be overridden by mainboards or chipsets.
Moving it lower in the tree allows for the defaults to be overridden.
Change-Id: I0b100f5535c5f383e8c6db74d0024c5ff2e8c08d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14878
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Since FSP-M is run in CAR (as opposed to XIP), its default link
address may need to be changed. Since cbfstool can relocate FSP
blobs, take advantage of that feature.
Change-Id: I4353fe09d785c090843ce25ff4e654d45c64c381
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14866
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Follow the convention used on all other platforms and explicitly call
console_init() before any printk(). This call was most likely ommitted
by accident during rebase.
Also remove the "Starting romstage..." message, as console_init() will
print a standardized message. I don't have details on how this message
originally appeared.
Change-Id: Id91f0fc15ecbd3635d67a261907f4c6af9a499ab
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14864
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
We have a timestamp from before cache-as-ram setup saved in the MMX
registers. Recover that timestamp, and use it as the base timestamp
rather than letting lib/bootblock.c use a late timestamp.
This allows more accurate profiling of the boot flow, since CAR setup
time is no longer excluded from the timing information.
Change-Id: I055092c600438c5260ab67509434a38f1eb77fe4
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14863
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is useful, for example, in the bootblock, when a timestamp is
available which predates the call to main() in lib/bootblock.c
Change-Id: I17bb0add9f2d8721504b2e534dd6904d1201989c
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14862
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Duncan Laurie