Commit Graph

25233 Commits

Author SHA1 Message Date
Patrick Georgi b1d26f0e92 util/crossgcc: update to gcc 8.1.0 and binutils 2.30
Also update patches as necessary.

Change-Id: I1e8074954d5d7a4eff590abb7439e9be7d3762aa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/25997
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-28 13:38:13 +00:00
Patrick Rudolph 1ce225b5a3 tianocore: Add more patches
* Fix building BaseTools in hostgcc v8.1.0+
* Fix buidling tianocore on gcc v7.0.0+

Change-Id: I7e2efea930b27749b1097607ab143ce2f91e79ec
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/27137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-28 13:37:56 +00:00
Martin Roth 11f8c9d9be crosgcc/patches: Add make patch for GLIBC glob interface v2
Copied from the GNU make repository
author	Paul Smith <psmith@gnu.org>
commit 48c8a116
configure.ac: Support GLIBC glob interface version 2

Change-Id: Id70a2b98dad6349ee56985d8dd6d4f0d87b470e6
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/26939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-28 09:33:58 +00:00
Elyes HAOUAS 8bffebee3d drivers/intel/fsp2_0: Fix uncountable "information"
Change-Id: I91e13a786b12328f1d9200f76788faa19847bbe7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-28 09:33:02 +00:00
Enrico Granata ede8f2673b nocturne: Fix uid and desc for sx9310
This commit changes the uid and desc fields for the sx9310 entries
in the devicetree to be unique, and correctly identify the position
of the respective sensors.

Change-Id: I501df7d3349fdebc9673c9815f5b1b2458abac6e
Signed-off-by: Enrico Granata <egranata@chromium.org>
Reviewed-on: https://review.coreboot.org/27248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
2018-06-28 09:30:09 +00:00
Marshall Dawson c06ee50d3d amd/common/pi: Remove AGESA support files from bootblock
The stoneyridge bootblock no longer makes AGESA calls.  Remove the
support files from the bootblock build.

TEST=boot Grunt

Change-Id: I14d2336d5fb766a1acf5e812337ae0ab3ca4a6c1
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/27255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-28 09:29:22 +00:00
Marshall Dawson 418c2bb29b amd/common/pi: Remove obsolete heapmanager workaround
Remove residual code that allowed successful building of the heapmanager
code.  Now that stoneyridge no longer makes AGESA calls in bootblock, it
is safe to elimate the workaround.

BUG=b:74518368
TEST=boot Grunt

Change-Id: Ie169a691a177bcd8283c31c8188ce28bcbce82af
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/27254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-28 09:29:16 +00:00
Elyes HAOUAS ebc1e2163f mb/*/*/cmos.layout: Fix coding style
Change-Id: I4f82482595b0e6c6159c6e1c66158bc18b061f04
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-28 09:25:30 +00:00
David Hendricks 0ea93cdc35 fsp_broadwell_de: Add ability to set PCIe completion timeout
This enables the user to set the completion timeout value in PCI
Express Device Control 2 register via devicetree.cb.

Based on corebootBDE-270-iou-complto.patch in Arista EOS 4.20 release.

Change-Id: If0527899bc2047d0e57c11f7801768d07f9a5179
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/26225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-06-28 09:05:19 +00:00
Arthur Heymans 7bea0846db arch/x86: include verstage.c only when verstage is a separate stage
Change-Id: Ia75205001f2443cb8221a0762f182aae01ee615e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26924
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-28 09:02:20 +00:00
Pratik Prajapati 1b25c8efca soc/intel/skylake: clear MCA before booting to OS
mca_configure needs to be called for each core before
booting to OS, else OS would keep dumping MCEs

Change-Id: I95ca46fda7be65d74714bdb344e339922cbb6305
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/26392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-06-28 09:01:56 +00:00
Pratik Prajapati 35cb7851ab intel/common: change mca_configure API's def
add an unused param so that mca_configure can be called
by mp_run_on_all_cpus to run it on all cores.

Change-Id: I2395ee7fbedc829f040959b0021967f800693eeb
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/26391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-06-28 09:01:48 +00:00
Patrick Rudolph 5ccc73145f devicetree: Add method to delete property by name
Will be used on Cavium SoC to delete devicetree entries that aren't
available with the board/configuration.

Change-Id: I7c58a2411206bca62d0e96fa627530e937383ac9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-06-28 09:01:26 +00:00
Raul E Rangel eb5d76a510 smm: Add canary to end of stack and die() if a stack overflow occurs
If CPU 0's stack grows to large, it will overflow into CPU 1's stack.
If CPU 0 is handling the interrupt then CPU 1 should be in an idle loop.
When the stack overflow occurs it will override the return pointer for
CPU 1, so when CPU 0 unlocks the SMI lock, CPU 1 will attempt to return
to a random address.

This method is not foolproof. If code allocates some stack variables
that overlap with the canary, and if the variables are never set, then
the canary will not be overwritten, but it will have been skipped. We
could mitigate this by adding a larger canary value if we wanted.

I chose to use the stack bottom pointer value as the canary value
because:
* It will change per CPU stack.
* Doesn't require hard coding a value that must be shared between the
  .S and .c.
* Passing the expected canary value as a parameter felt like overkill.

We can explore adding other methods of signaling that a stack overflow
had occurred in a follow up. I limited die() to debug only because
otherwise it would be very hard to track down.

TEST=built on grunt with a small and large stack size. Then verified
that one causes a stack overflow and the other does not.

Stack overflow message:
canary 0x0 != 0xcdeafc00
SMM Handler caused a stack overflow

Change-Id: I0184de7e3bfb84e0f74e1fa6a307633541f55612
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27229
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-28 09:01:02 +00:00
Tristan Shieh f78f97e156 mediatek/mt8183: Remove the stub flash driver that planned to use eMMC
The stub flash driver is a temporary hack that planned to adapt eMMC to
SPI flash. Remove the hack since SPI flash is what we really expect.

BUG=b:80501386
BRANCH=none
TEST=Boots fine on Kukui

Change-Id: If29869461fc8c2efe26bb8c901737ee85935d27f
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-06-28 08:59:01 +00:00
Seunghwan Kim bc10d72887 mb/google/poppy/variants/nautilus: Use GPP_B20 to determine SKU
We would use GPP_B20 instead of board id to determine nautilus SKU.

BUG=b:80052672
BRANCH=poppy
TEST=Verified the new coreboot could determine SKU correctly

Change-Id: I1978b544eef7a184a3da191306ee32d862fa8c36
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27220
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-28 08:58:30 +00:00
Justin TerAvest d940050897 mb/google/octopus: Create bobba variant
This creates a bobba variant for octopus.
The devicetree overrides are copied from fleex, otherwise everything
just defaults to baseboard settings.

BUG=b:110781720
TEST=None

Change-Id: Ic30c6b0d955ce26f4a9f40cd7fef1c429ab950fc
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/27223
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-28 08:57:58 +00:00
Sumeet Pawnikar c08e62d7d4 mb/google/poppy/variants/nocturne: Update TSR sensor info
This patch updates TSR sensor info with appropriate names.
Also, updates Charger effect with correct TSR sensor mapping.

BUG=None
BRANCH=None
TEST=Build coreboot for Nocturne board.

Change-Id: Ia3bbc78f8d823e88a91265e0d55c5ac2a4ea31a9
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/27210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-06-28 08:57:27 +00:00
Patrick Rudolph 9554b26f9f vboot: Fix linking error with USE_OPTION_TABLE enabled
Fix a linking problem with VBOOT and USE_OPTION_TABLE enabled.
Make use of cbfs_locate_file_in_region() and always search the
cmos_layout.bin in the 'COREBOOT' region.

With this change applied there's no need to include the vboot_locator
in SMM any more, we can't break NVRAM with different CMOS layouts,
and we keep VBOOT and non VBOOT behaviour the same.

Only include cmos_layout.bin and cmos.default in RO region.

Add notes explaining the decisions.

Tested on Intel Sandybridge, builds and boots with vboot enabled.

Change-Id: I10ae94d7936581bbb5ea49384122062bd4934ea5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-28 08:57:05 +00:00
Subrata Banik 7837c203d6 soc/intel/common/block: Move p2sb common functions into block/p2sb
This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving
common soc code into common/block/p2sb.

BUG=b:78109109
BRANCH=none
TEST=Build and boot KBL/CNL/APL platform.

Change-Id: Ie9fd933d155b3fcd0d616b41cdf042cefe2c649a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-28 08:35:29 +00:00
Angel Pons 210b351df3 Documentation: Add Gigabyte to list of mainboards
Gigabyte was not in the list of vendors in the mainboard-specific
documentation. This made a newly added mainboard page difficult to
locate. This commit adds Gigabyte and links said mainboard in the
mainboard-specific documentation main page.

Change-Id: I8839e1c1176fbdc3dd9da616f68c58e8e1cf1b16
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/27045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-06-28 06:02:35 +00:00
Furquan Shaikh ebee0d4369 soc/intel/apollolake: Remove dead files
Change a86d1b8 (soc/intel/common: Add SMM common code for Intel
Platforms) moved APL to use common SMM code. However, smi.c and smm.h
files under soc/intel/apollolake/ were not removed. This change
removes the dead files since they are not used anymore.

BUG=b:110836465

Change-Id: I1ff213372521fd47e2335de6a4b438d16c74ecd3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-28 05:00:26 +00:00
Furquan Shaikh a00c7774d8 soc/intel/common: Disable GPEs just before enabling SMIs
Call to pmc_disable_all_gpe is required before enabling SMIs to ensure
that we do not end up in a recursive SMI handler loop as mentioned in
change 74145f7 (intel/common/pmc: Disable all GPEs during
pmc_init). Thus, this call was added at the end of
pmc_fill_power_state as we want to ensure that all the GPE registers
are backed up before being cleared for identifying the wake source in
ramstage.

This resulted in a side-effect on APL where pmc_fixup_power_state was
called much later in the boot process. Even though we have got rid of
pmc_fixup_power_state, this change moves the call to
pmc_disable_all_gpe to happen just before enabling SMIs. This helps to
keep the disabling of GPEs logically before the enabling of SMIs and
any clean ups that happen in pmc or soc-specific code should not
affect the state of GPEs.

BUG=b:110836465
TEST=Verified that wake sources are correctly identified on KBL and
APL. Also, no SMI handler issues observed when resuming.

Change-Id: I122a8118edcec117f25beee71a23c0a44ae862ed
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-28 05:00:12 +00:00
Furquan Shaikh 14e8f20edc soc/intel/common/block/pmc: Get rid of pmc_fixup_power_state
Now that APL does not need pmc_fixup_power_state, this function can be
removed from the PMC common code as well.

BUG=b:110836465

Change-Id: I94de41f3e52228bca4b7a5579afe5a23719429be
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-28 05:00:01 +00:00
Furquan Shaikh 344ed02a74 soc/intel/apollolake: Remove call to pmc_fixup_power_state
On APL, call to pmc_fixup_power_state was added because GPE0_EN
registers did not have the right bits set on resume from S3 -- this
was a result of GPE_CFG registers getting reset to their default state
on resume. GPE_CFG registers are programmed as part of pmc_gpe_init
which was previously done only in ramstage.

However, with change a673d1c (soc/intel/apollolake: Initialize GPEs in
bootblock), call to pmc_gpe_init was added to bootblock which means
that GPE_CFG registers will have the right state by the time control
reaches romstage where pmc_fill_power_state is called. Thus, call to
pmc_fixup_power_state is totally redundant and in fact leads to
side-effects because of the call to pmc_disable_all_gpe at the end of
pmc_fill_power_state.

BUG=b:110836465
TEST=Verified on yorp that wake source is correctly identified on
resume from S3.

Change-Id: Ia63ddbe381ce8a59736c231d745fd71d008d5d92
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-28 04:59:53 +00:00
Raul E Rangel e18e5ab5fa smm: Switch from %edx to %ebx
%edx gets clobbered before the c handler is invoked. This is just a
cleanup cl to make the next cl look clean.

BUG=b:80539294
TEST=verified SMI still works on grunt.

Change-Id: I21bf41ed4fdeaaa8737c883f202a39cb57c2b517
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27228
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-27 22:12:28 +00:00
Raul E Rangel 871156898c smm: Push a null stack base pointer
When generating a backtrace we need an indicator when we have hit the
beginning of the stack. The i386 ABI states that %ebp points to the next
stack frame. NULL can be used to indicate the end of the stack.

We could add a NULL return pointer at %ebp+4, but I decided to omit it
since a NULL stack pointer can be used as an indicator that there is no
return pointer.

BUG=b:80539294
TEST=built and tested on grunt

Change-Id: I8a48114d31a5c716335d264fa4fe4da41dc5bf11
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27226
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-27 22:12:18 +00:00
Raul E Rangel 0140541f50 smm: Make local variables relative to ebp
This reduces the cognitive overhead of referencing locals via esp since
it changes with every push.

BUG=b:80539294
TEST=built and booted on grunt.

Change-Id: Ib7eb98ce3483d4fc803696c1b2496d8384317536
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-27 22:11:20 +00:00
Raul E Rangel dd549e1175 smm: Clear SMRAM when debugging
This makes it easier to spot unused RAM.

BUG=b:80539294
TEST=built and tested on grunt. Verified unused memory was set to 0xcdcdcdcd

Change-Id: I335eaf642bd8526f31819eaac95ce80c2df3c300
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-27 22:11:11 +00:00
Matt DeVillier c57a273d4c mb/google/*: Add a few VBT files
These files are directly extracted from the vendor firmware

Change-Id: I1f05c913872c5d2d8c8279d89eac52fd4bf4e35e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-27 15:38:25 +00:00
Matt DeVillier 06c373d162 drivers/intel/fsp1_1: Fix vbt_len type
Type of vbt_len should be size_t, change to fix compiler error

Change-Id: I22798fa0edb98fcb9acc1b2dd52f34a61bc511e9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-27 15:38:12 +00:00
Arthur Heymans 7875dbd981 cpu/intel/p4-netburst: skip caching rom on model_fxx
An unidentified combination of speculative reads and branch
predictions inside WRPROT-cacheable memory can cause invalidation of
cachelines and loss of stack on models based on NetBurst
microarchitecture.

Therefore disable WRPROT region entirely for all family F models.

As an extreme example, just changing the location of a constant string
passed to printk() has been witnessed to make a the boot fail early on
in romstage.

Change-Id: I1df84ad55e2d8d6d4e8dca10125131b5f525f0d7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-27 11:48:53 +00:00
Kyösti Mälkki ce9f422b51 x86/car: Replace reference of copy_and_run location
For cases with POSTCAR_STAGE=y this reference pulled
in the implementation of run_ramstage() which we would
not call.

Using _program results with the same region being marked
as WRPROT-cacheble.

Change-Id: Ie1eaf6f5bb8baa13e946112c4fc3d854dbf750a3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/27232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Keith Hui <buurin@gmail.com>
2018-06-27 10:24:46 +00:00
Kyösti Mälkki c3bc6cbe9d lib/rmodule: Fix indentation
Change-Id: Ieb809a078356f696afd813c39c65da1d7c7482c8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/27231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-27 02:20:33 +00:00
Kyösti Mälkki a8c0cb3512 stage_cache: Disable when APCI S3 is not possible
Don't consume CBMEM for stage cache when we would
never use it.

Change-Id: I606e0457ff3085822554c4041fc56f0d28cc9c2d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/27230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-27 02:20:11 +00:00
Julius Werner e0058e89ab arm64: Reimplement mmu_disable() in assembly
Disabling the MMU with proper cache behavior is a bit tricky on ARM64:
you can flush the cache first and then disable the MMU (like we have
been doing), but then you run the risk of having new cache lines
allocated in the tiny window between the two, which may or may not
become a problem when those get flushed at a later point (on some
platforms certain memory regions "go away" at certain points in a way
that makes the CPU very unhappy if it ever issues a write cycle to
them again afterwards).

The obvious alternative is to first disable the MMU and then flush the
cache, ensuring that every memory access after the flush already has the
non-cacheable attribute. But we can't just flip the order around in the
C code that we have because then those accesses in the tiny window
in-between will go straight to memory, so loads may yield the wrong
result or stores may get overwritten again by the later cache flush.

In the end, this all shouldn't really be a problem because we can do
both operations purely from registers without doing any explicit memory
accesses in-between. We just have to reimplement the function in
assembly to make sure the compiler doesn't insert any stack accesses at
the wrong points.

Change-Id: Ic552960c91400dadae6f130b2521a696eeb4c0b1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-26 23:59:18 +00:00
Julius Werner a98b5bf89b arm64: Switch remaining uses of __ASSEMBLY__ to __ASSEMBLER__
Some arm64 files that were imported from other projects use the
__ASSEMBLY__ macro to test whether a header is included from a C or an
assembly file. This patch switches them to the coreboot standard
__ASSEMBLER__, which has the advantage of being a GCC builtin so that
the including file doesn't have to supply it explicitly.

Change-Id: I1023f72dd13857b14ce060388e97c658e748928f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-26 23:59:08 +00:00
Julius Werner 905e1e763e arm64: Drop dead file stage_entry.S
This file has been dead since commit 7dcf9d51 (arm64: tegra132:
tegra210: Remove old arm64/stage_entry.S), I just forgot to remove it.

Change-Id: I0dd6666371036ecd42c1b256dbbe22a01ae959b8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-26 23:58:56 +00:00
T Michael Turney 1da5fb67b0 cheza: Fix Kconfig TPM items
TPM config items added upstream before ready
SPI/TPM is not functional on Cheza yet

Change-Id: I302e00014dc31279fe2574765763ecdbf326b449
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/27213
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-26 23:58:09 +00:00
Patrick Georgi 095db339f7 util/crossgcc: Allow building a new gcc against new binutils with -D
With -D, the newly built toolchain isn't installed into $prefix/...
but into $DESTDIR/$prefix/... while being built for $prefix alone.

This is useful for distributions, but it breaks down when the build
host already has the toolchain installed in $prefix without proper
build isolation (cf. gentoo):

In such cases libgcc etc are built using the new compiler (as gcc's
build system is smart enough to state the path explicitly), but that
compiler then uses its regular algorithm to determine the path to as,
ld, ...
That makes it use the tools from $prefix, which might differ in formats
(assembly, certain object file flags, ...): nds32le-elf in particular
has rather unstable formats still, and so new compilers can't work
with old binutils.

The approach to deal with this is to take an unused path that's
specified by gcc's build system ($out/gcc/$arch/$version) and symlink
it to the new toolchain - these explicitly given directories take
precedence over the default search path, and so the new binutils
are used.

Change-Id: Ia9a262e73f56cd486a2ae07422b598c205a03aed
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/27241
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-26 20:58:01 +00:00
Furquan Shaikh d1d85e8849 mb/google/octopus: Enable logging of EC wake sources in S0ix
This change adds GSMI callback elog_gsmi_cb_mainboard_log_wake_source
to enable logging of EC wake events in S0ix.

BUG=b:79449585
TEST=Verified that S0ix entry/exit events are added to eventlog:

=========== Lid open ================
62 | 2018-06-25 14:02:36 | S0ix Enter
63 | 2018-06-25 14:02:56 | S0ix Exit
64 | 2018-06-25 14:03:26 | Wake Source | GPE # | 15
65 | 2018-06-25 14:03:32 | Wake Source | GPE # | 65
66 | 2018-06-25 14:03:37 | EC Event | Lid Open

Change-Id: Icc8cd3624966ff66d2cf189871e452cf650cec40
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27235
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-26 20:40:27 +00:00
Furquan Shaikh c83e70eed2 soc/intel/apollolake: Enable logging for wake sources in S0ix
This change adds GSMI callback elog_gsmi_cb_platform_log_wake_source
to enable wake source logging from S0ix on APL/GLK. Additionally,
elog.c is added to smm stage.

BUG=b:79449585
TEST=Verified that S0ix entry/exit events are added to eventlog:

=========== Power button ============
59 | 2018-06-25 14:01:11 | S0ix Enter
60 | 2018-06-25 14:01:30 | S0ix Exit
61 | 2018-06-25 14:02:00 | Wake Source | Power Button | 0

=========== Lid open ================
62 | 2018-06-25 14:02:36 | S0ix Enter
63 | 2018-06-25 14:02:56 | S0ix Exit
64 | 2018-06-25 14:03:26 | Wake Source | GPE # | 15
65 | 2018-06-25 14:03:32 | Wake Source | GPE # | 65
66 | 2018-06-25 14:03:37 | EC Event | Lid Open

=========== Trackpad ================
67 | 2018-06-25 14:04:20 | S0ix Enter
68 | 2018-06-25 14:04:33 | S0ix Exit
69 | 2018-06-25 14:05:03 | Wake Source | GPE # | 15
70 | 2018-06-25 14:05:08 | Wake Source | GPE # | 66

Change-Id: I005de58c73d00dc9d7e64f1459f6d786792b94db
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27234
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-26 20:40:19 +00:00
Richard Spiegel ef73cb88dc soc/amd/stoneyridge/southbridge.c: Fix get_index_bit limit check
Limit is the maximum number of bits to be tested, however it's being checked
against the number of bytes of uint32_t. when it should be number of bits.
Create a macro to provide the number of bits, and use it instead of sizeof.

BUG=b:75996437
TEST=Add debug messages to see code passing beyond the check, build and
boot grunt, check that it passed the limit check, remove debug code.

Change-Id: Id1dfda26d789183b346b20c37fec923d996b80db
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-26 15:20:29 +00:00
Hong Gan 8fb9f23d51 opencellular/rotundu: Add mainboard support
Adds Open Cellular rotundu mainboard supports.

Working:
  - 2x Ethernet support
  - MSATA support
  - CPU init
  - Memory init
  - USB support
  - EMMC but disabled

Not working:
  - TPM support

Create directory structure and Kconfig files for OpenCellular
Rotundu and copy sources from intel/minnowmax.

Change-Id: I391d4bdd485f4bf5396c764fe3f11d98369593e4
Signed-off-by: Hong Gan <hgan@fb.com>
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/22894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-06-26 15:20:15 +00:00
David Hendricks 5f187dbe63 facebook/watson: Initial commit
This adds another camelbackmountain_fsp derivative, along with a .fmd
file for the board. For now it's been tested to build and boot.

Change-Id: I9e8804264967c19f6b51fc44575b0db36f600f88
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/25884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-06-26 15:17:29 +00:00
Rizwan Qureshi c1072f2fc7 cbfstool: Update FIT entries in the second bootblock
Once a second bootblock has been added using topswap (-j)
option, Update the entries in second FIT using -j option with
update-fit command.

Additionally add a -q option which allows to insert the address of
a FMAP region (which should hold a microcode) as the first entry in
the second FIT.

BUG=None
BRANCH=None
TEST= Create ROM images with -j options and update FIT using -q option.
example:
./build/util/cbfstool/cbfstool coreboot.tmp create \
	-M build/fmap.fmap -r COREBOOT,FW_MAIN_A,FW_MAIN_B,RW_LEGACY
build/util/cbfstool/cbfstool coreboot.tmp add \
	-f build/cbfs/fallback/bootblock.bin -n bootblock -t \
	bootblock -b -49152 -j 0x10000
build/util/cbfstool/cbfstool coreboot.tmp add-master-header -j 0x10000
build/util/cbfstool/cbfstool coreboot.tmp add -f build/cpu_microcode_blob.bin \
	-n cpu_microcode_blob.bin -t microcode -r COREBOOT -a 16
build/util/cbfstool/cbfstool coreboot.tmp. update-fit \
	-n cpu_microcode_blob.bin -x 4 -j 0x10000 -q FW_MAIN_A

Also try the failure scenarion by providing invalid topswap size.

Change-Id: I9a417031c279038903cdf1761a791f2da0fe8644
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/26836
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-26 05:59:52 +00:00
Rizwan Qureshi 1dc188fad0 cbfstool: add an option for creating a topswap bootblock
Add an option '-j' which takes the size of topswap boundary.
This option serves both as a bool and a size for creating
a second bootblock to be used with topswap feature in Intel CPUs.
'-j' is also used in conjunction with add-master-header to
update the location of cbfs master header in the second bootblock.

BUG=None
BRANHC=None
TEST=add bootblock entry to the image with -j option specifying different
topswap sizes and also use the -j option for add-master-header.

Change-Id: I3e455dc8b7f54e55f2229491695cf4218d9cfef8
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/22537
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-26 05:51:33 +00:00
Simon Glass 4f16049f17 mb/google/kahlee/variants/grunt: Select low-power mode for BayHub720
Put the PCIe clock pins in power-saving mode for the BayHub eMMC bridge to
save power. This requires use of an additional register (Misc control
register 2) and another bit in the existing 'protect' register. The naming
of bit 0 of that register is incorrect, based on the latest datasheet
(14 June 2018) so fix that too.

BUG=b:73726008
BRANCH=none
TEST=boot without this patch:
iotools mem_read32 0xfed80e00
0x0046ffff

With this patch:
$ iotools mem_read32 0xfed80e00
0x00463fff

Also see that the PCIe clock stops when eMMC is idle and can be started by
starting disk activity.

Change-Id: I5ad1467b2e2e151215d2dfd2ce48cd4a451fe480
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/26515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-25 20:50:14 +00:00
Furquan Shaikh 57ccb9c5e8 util/abuild: Enable abuild to compile a single variant
There are many boards in coreboot which support multiple
variants. When abuild is used to compile a single target, it builds
all its variants. If a target has 5 variants, then abuild takes nearly
10x the time to compile all variants of the target. This change adds
an option -b/--board-variant to enable abuild to compile only a single
variant of the target.

TEST=Verified:
1. abuild builds all variants of the target if -b option is not
provided.
2. abuild builds a single variant if -b option is provided.
3. abuild prints appropriate error message if invalid variant name is
provided.

Change-Id: I3781568c6409c5ec2610a8386a21d86037428e7f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27215
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-25 17:41:26 +00:00
Furquan Shaikh 0be087deee mb/google/octopus: Use the newly added override devicetree feature
Now that sconfig is able to support variant-specific override trees,
this change updates octopus boards to use this feature. Following
devices are moved from baseboard devicetree to variant specific
devicetree:
1. Touchscreen
2. Trackpad
3. Digitizer
4. Audio codec

BUG=b:80081934
TEST=Verified that the right devices show up in static.c for each
variant.

Change-Id: I8df0cdf4dbcd7613aa4ef4042c272eca2915da9e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27219
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-25 17:41:00 +00:00