Commit Graph

31778 Commits

Author SHA1 Message Date
Elyes HAOUAS 6c361d6838 mb/jetway: Use 'Device()' instead of 'Processor()'
Processor() operator is deprecated, use Device() instead.

Change-Id: Ib454fc76db0b45332326772b8d1f295429107133
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27 19:03:03 +00:00
Martin Roth 468d02cc82 src/[northbridge,security]: change "unsigned" to "unsigned int"
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: If6b5930f78c3da6dcefaa7b6202cd0424a24525b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-27 18:12:50 +00:00
Elyes HAOUAS 36fcc85be4 mb/iei: Use 'Device()' instead of 'Processor()'
Processor() operator is deprecated, use Device() instead.

Change-Id: I547be16285787ee3578f855111ca177be047ced2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27 18:12:17 +00:00
Elyes HAOUAS 8484a12a9c mb/gigabyte: Use 'Device()' instead of 'Processor()'
Processor() operator is deprecated, use Device() instead.

Change-Id: Ia27308ba17c6b5c836ada6278f7d26631e09c022
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27 18:11:43 +00:00
Elyes HAOUAS 6908dc8ea8 mb/avalue: Use 'Device()' instead of 'Processor()'
Processor() operator is deprecated, use Device() instead.

Change-Id: I303023a16f8c913c965995794cb627bb9591560b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27 18:09:38 +00:00
Elyes HAOUAS dac4497754 mb/asus: Use 'Device()' instead of 'Processor()'
Processor() keyword is deprecated, use Device() instead.

Change-Id: I162304bdef6562fd660c01fb8fc67037ebe8cfa5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27 18:08:53 +00:00
Elyes HAOUAS 4b0598c35a mb/advansus: Use 'Device()' instead of 'Processor()'
Processor() Keyword is deprecated, use Device() instead.

Change-Id: I805291716ab3395736d8a70a18468f247d9f4edf
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27 18:07:48 +00:00
Elyes HAOUAS af84368591 mb/amd: Use 'Device()' instead of 'Processor()'
Processor() operator is deprecated, use Device() instead.

Change-Id: Ia1d73806b00ec38084fff3989f52227d4c216e65
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27 18:07:10 +00:00
Elyes HAOUAS 2c34892efd cpu/amd/*/*/acpi/: Use 'Device()' instead of 'Processor()'
Processor() operator is deprecated, use Device() instead.

Found-by: ACPICA 20191018
Change-Id: I4541372a98f05d3e915c74bc28f41309754014e4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36258
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-27 18:05:38 +00:00
Elyes HAOUAS 6df210b0c2 mb/(ich7): Use macro instead of magic number
Change-Id: Ida291ed9f3a509e9b96a5c254433db6f8028bfb2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27 17:55:34 +00:00
Elyes HAOUAS ede8dd0b9c src/{device,drivers}: Use 'include <stdlib.h>' when appropriate
Also, including <types.h>, is supposed to provide stdint and stddef.

Change-Id: I99918a5a77e759bc7d4192d2c3fd6ad493c70248
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-27 17:52:05 +00:00
Elyes HAOUAS 0edf6a59f8 src: Use 'include <boot/coreboot_tables.h>' when appropriate
Change-Id: I3d90e46ed391ce323436750c866a0afc3879e2e6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36359
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-27 17:48:30 +00:00
Stefan Reinauer 7385b656c2 buildgcc: ACPICA: build more utilities and in parallel
- honor $JOBS in build_IASL

- Build the following utilities in addition to iasl for easier debugging of
  ACPI issues:

   * acpibin
   * acpidump
   * acpiexec
   * acpihelp
   * acpinames
   * acpisrc
   * acpixtract

Change-Id: I84476da8f9a5ba4860ba4ad0220ec3efb229cc03
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36337
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-27 17:46:37 +00:00
Arthur Heymans b759a4f987 cbmem.h: Align comment with the reality of implementations
cbmem_top() should simply not be called before memory is initialed,
in order for the implementation to return something meaningful.

Change-Id: I8fe32844af290626a0f91279143fda4d3442680f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Michael Niewöhner
2019-10-27 10:39:28 +00:00
Nico Huber eafc81514a Makefile: Switch to `.config` as input for the Ada `CB.Config`
So, this is odd in multiple ways. First of all, we fix something:
We work around a weirdness in `make oldconfig` that adds spurious
entries into the `auto.conf` for choices that were given a symbol
name.

When introducing the Ada config package, it seemed reasonable to
use `auto.conf` as source, but it turned out that we didn't use it
as input, only `config.h` and the original `.config` were used. As
the syntax for `.config` is the same as for `auto.conf` we use the
former now as input for Ada, too. One question remains: If `.config`
already contains all required information, what is this `auto.conf`
and what does it want?

Alternatively, we could try to fix `oldconfig` or add a linter to
forbid named choices. I thought, our build test would reject the
latter already. But the `oldconfig` behaviour is too subtle.

We keep a dependency on the `oldconfig` step, to make sure it runs
first.

Change-Id: If3fe6bc782251cdbd696395d3069a1c0bb0ae802
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36320
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-26 23:04:46 +00:00
Himanshu Sahdev 6a3cf1b6fc util/crossgcc/patches: facilitate successful build of ipxe
New changes in the latest binutils 2.32 lead to assembler errors causes
ipxe build failure. IPXE uses the divide test which requires /dev/null as
input as well as the output file name.

This patch facilitates the /dev/null as an exception to the current
changes in binutils package while building crossgcc for coreboot leads to
successful build of ipxe and further tests to pass based on /dev/null and
applies automatically during the crossgcc rebuild.

Also, this can be reverted once binutils/ipxe provides an updated release
in this respect.

Fixes: https://ticket.coreboot.org/issues/204

Change-Id: I9f664829b8c42420c0b2ab1f2316150f86ac0b1a
Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35098
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-26 16:30:15 +00:00
Michael Niewöhner bc1dbb3cc3 drivers/intel/fsp2_0: move die() calls to the functions
Since there are no calls where we wouldn't die(), move die() calls into
the fsp_find_* functions.

Change-Id: I750a225999688137421bbc560d9d1f5fdf68fd01
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-26 15:49:18 +00:00
Michael Niewöhner 40f893e9f3 soc/intel: common,skl,cnl,icl: drop reserved mmio memory size calculation
Remove the calculation of the Reserved Intel MMIO Memory size from
systemagent and memmap, since it is not needed.

The size is used in SA to calculate the space between cbmem_top and TSEG
without DPR and Chipset Reserved Memory. Since this will always be equal
to 0, the reservation will be skipped and TSEG, DPR and Chipset Reserved
Memory will get reserved alltogether.

By reading the code and pratical testing we figured out that:
- TSEG - DPR - reserved - top_of_memory == 0
- TSEG - DPR - reserved == top_of_memory

This means the whole block will never reserve anything because it is
always 0. Hence the code can be removed for simplification.

Tested successfully on X11SSM-F

Change-Id: I0cc730551eb3a79c78a971b40056de8d029f4b82
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-26 15:48:47 +00:00
Michael Niewöhner b17f3d3d3c soc,mb/intel: clean up remaining FSP2.0 socs/boards
Remove CONFIG_...FSP2.0 based if-switches from FSP2.0-only socs/boards

Change-Id: Iae92dc2e2328b14c78ac686aaf326bd68430933b
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36279
Reviewed-by: Michael Niewöhner
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-26 15:47:49 +00:00
Michael Niewöhner 7ef19036fb soc/intel/skylake: move/rename files after drop of FSP 1.1
Follow-up commit where only files are moved and paths adapted to make
review of the previous commit easier.

Change-Id: Iff1acbd286c2ba8e6613e866d4e2f893562e8973
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35868
Reviewed-by: Michael Niewöhner
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-26 15:47:34 +00:00
Michael Niewöhner fa62e01b90 drivers/intel/fsp1_1: remove orphaned functionality
Remove orphaned functionality from the FSP1.1 driver that only has been
used by skylake, which is now FSP2.0-only.

Change-Id: I732f2d6846788d5c03647c6fb620e45b3b66de5f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36266
Reviewed-by: Michael Niewöhner
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-26 15:39:49 +00:00
Michael Niewöhner 0f91f79447 soc/intel/skylake: drop support for FSP 1.1
This drops support for FSP 1.1 in soc/intel/skylake, after all boards
have been migrated to FSP 2.0, which is backwards compatible.

Any moving of files happens in a follow-up commit to make review easier.

Change-Id: I0dd2eab0edfda0545ff94c3908b8574d5ad830bd
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35813
Reviewed-by: Michael Niewöhner
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-26 15:39:40 +00:00
Praveen Hodagatta Pranesh a9e07f9444 mb/intel/saddlebrook: Enable serial port on SIO
Enable saddlebrook board Serial port on SuperIO by
selecting DRIVERS_UART_8250IO.

TEST=Build, Boot saddlebrook board and verified serial logs.

Change-Id: Ic7b3416f281bfd91416c987c5a720ffac0c89d45
Signed-off-by: Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner
2019-10-26 15:16:59 +00:00
Michael Niewöhner 5e779f9a6c mb/intel/saddlebrook: migrate to FSP 2.0
This patch is part of the patch series to drop support for FSP 1.1 in
soc/intel/skylake.

The following modifications have been done to migrate the board(s) from
FSP 1.1 to FSP 2.0:

- remove deprecated devicetree VR_RING domain (only 4 domains in FSP 2.0)

TODO:
- testing

Change-Id: I7481f3413de6780df01d9b769bd4f16d439f087c
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35923
Reviewed-by: Michael Niewöhner
Reviewed-by: Wim Vervoorn
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-26 15:15:33 +00:00
T Michael Turney fda6cd6d28 trogdor: Provide initial mainboard support
Change-Id: Ic2f0944b92dcad7048a0c38720d2ef3c855ef007
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-10-25 23:38:44 +00:00
Maccraft 0cd098e4e4 mb/lenovo/{t60,r60}: Add ThinkPad R60 support as variant board
- This port should be Reclaim Your Freedom compliant
  (not certified yet).
- Untested on boards with external Radeon graphics adapter.
- Some columns on the left-most side of display are completely
  black on 1400x1050 IPS display[1]. Display works fine on Linux.
  I don't know why it appears like that. So far it has been observed
  only with native graphics initialization.
- Only GRUB2 and SeaBIOS payloads tested for now.
- 2504 docking station USB doesn't work under Linux.
  Can detect pendrive in GRUB2 payload.
- Sometimes it takes 20s of "pretending it's powered off" to run
  coreboot code. Issue is payload agnostic.
  Probably caused by missing one capacitor on my unit.

[1] https://imgur.com/a/0wpMGsm

Change-Id: Ibd9208a5eafd228f8eedbc8fb4f4eb9ed1932a14
Signed-off-by: Maciej Matuszczyk <maccraft123mc@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-25 20:07:16 +00:00
Elyes HAOUAS 9be81b8d4b soc/intel: Drop wrong _ADR objects
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID
object or an _ADR object, but should not contain both."

Change-Id: I09fce1298794f30c1db699438204ac32ee9cb27d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36296
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25 10:07:49 +00:00
Elyes HAOUAS 4d99cdeaf9 src/mainboard: Drop wrong _ADR objects
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID
object or an _ADR object, but should not contain both."

Change-Id: I50cafce0aaf465ee95562ccff6c8f63fb22096c0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-25 10:07:02 +00:00
Elyes HAOUAS 5216b72a99 ec/{compal,google,quanta}: Drop wrong _ADR objects
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID
object or an _ADR object, but should not contain both."

Change-Id: If3ee38f3eaa8e6d1c1b0393d0ba289f708e0ae5e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36293
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25 10:06:45 +00:00
Peter Lemenkov faaea99859 mb/lenovo/x201/smihandler: Remove mainboard_io_trap_handler function
An io_trap_handler on this board is unused in SMM.

Change-Id: Ie922f8f1a10495ae887221735c96807261508041
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-25 07:03:59 +00:00
Peter Lemenkov dbed7865d3 mb/*/*/smihandler: Remove bogus mainboard_io_trap_handler
These mainboard_io_trap_handler functions do nothing compared to a weak
mainboard_io_trap_handler in src/cpu/x86/smm/.

Change-Id: I73ebcc6c3f604a075a946503d51881ccc6820dac
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-25 07:02:50 +00:00
Peter Lemenkov cfc93cbb66 mb/lenovo/{t60,x201,x60}/smihandler: Remove SMM reinitialization
Remove SMM reinitialization since it's already done in src/ec/lenovo/h8.
Untested on a real hardware.

See also commit 8953d4a1 with Change-Id
I33fd829a7e34aefa8f76ca6020cc8e802f7aab17 ("mb/lenovo/*/smihandler: Get
rid of mainboard_io_trap_handler").

Change-Id: Icc582527db15f3a31cdee8948bc5a190240fdc84
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-25 07:02:18 +00:00
Peter Lemenkov b2832e3586 mb/*/*/smihandler: Remove bogus SMM init
I does nothing on these boards. It's just a call a local noop function
which only prints a debug-level message.

Change-Id: Id3fb2e9074db72d9025b95f7d4918417dd488b9e
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-25 07:02:02 +00:00
Himanshu Sahdev 8c09b82cb1 arch/acpi.h: Convert MADT APIC type names to all caps
Convert names to all capital in enum acpi_apic_types. Use of these names in
corresponding type assign for I/O APIC Structure.

Change-Id: Iab2f6d8f645677734df753f8bf59fde4205ce714
Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36197
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25 07:00:37 +00:00
Himanshu Sahdev b0f99ad794 arch/acpi.h: Use the aforementioned typedef acpi_table_header
Use already declared typedef and modify the usage accordingly.

Change-Id: Icf12ab9059be444fbe252b26e70214b1ef062c72
Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36194
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25 07:00:17 +00:00
Furquan Shaikh ca1187faa2 mb/google/{glados,dragonegg}: Configure GPIOs in mainboard chip->init()
mainboard_silicon_init_params() is supposed to be used for only
overriding any FSP params as per mainboard configuration. GPIOs should
be configured by mainboard as part of its chip init(). This ensures
proper ordering w.r.t. any common operations that the SoC code might
want to perform e.g. snapshot ITSS polarities.

This change moves the configuration of GPIOs from
mainboard_silicon_init_params() to mainboard chip->init().

Change-Id: I5d10c01c5b9d5f8ed02274d51dcf9c2a17269685
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36270
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25 06:55:37 +00:00
Furquan Shaikh 514ddef4e5 mb/google/{drallion,sarien}: Configure GPIOs in mainboard chip->init()
mainboard_silicon_init_params() is supposed to be used for only
overriding any FSP params as per mainboard configuration. GPIOs should
be configured by mainboard as part of its chip init(). This ensures
proper ordering w.r.t. any common operations that the SoC code might
want to perform e.g. snapshot ITSS polarities.

This change moves the configuration of GPIOs from
mainboard_silicon_init_params() to mainboard chip->init().

Change-Id: I5cd89c6e24b6a4b0c20fd476915f3781a0d46e0d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36269
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25 06:55:22 +00:00
Furquan Shaikh fb9f320d81 mb/google/{poppy,eve,fizz}: Configure GPIOs in mainboard chip->init()
mainboard_silicon_init_params() is supposed to be used for only
overriding any FSP params as per mainboard configuration. GPIOs should
be configured by mainboard as part of its chip init(). This ensures
proper ordering w.r.t. any common operations that the SoC code might
want to perform e.g. snapshot ITSS polarities.

This change moves the configuration of GPIOs from
mainboard_silicon_init_params() to mainboard chip->init().

Change-Id: Ied0201b954894acd3503801e7739b91a2cc9b4a8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36268
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25 06:55:05 +00:00
Furquan Shaikh 80212aa104 mb/google/hatch: Configure GPIOs in mainboard chip->init()
mainboard_silicon_init_params() is supposed to be used for only
overriding any FSP params as per mainboard configuration. GPIOs should
be configured by mainboard as part of its chip init(). This ensures
proper ordering w.r.t. any common operations that the SoC code might
want to perform e.g. snapshot ITSS polarities.

This change moves the configuration of GPIOs from
mainboard_silicon_init_params() to mainboard
chip->init(). Additionally, this change moves mainboard_ec_init() to
mainboard dev->init().

TEST=Verified that GPIOs are configured properly and hatch boots to
OS.

Change-Id: Ia509471a3678c60454cd4f14625f151860d9b9d2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36267
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25 06:54:50 +00:00
Cheng-Yi Chiang 91c8d35be3 mb/google/hatch: Set DSM parameters for Helios
Set VPD keys for DSM parameters in overridetree.cb for Helios.
RT1011 driver will load values from VPD and set them to device property.

BUG=b:140397934
BRANCH=none
TEST=On Helios, with patch series, check realtek,r0_calib and
realtek,temperature_calib are available to rt1011 codec driver.

Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org>
Change-Id: Ic72fd57becf93e70a1a716dbb76633509f2fd5c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-10-25 03:12:26 +00:00
Cheng-Yi Chiang 9680b84eb1 mb/google/hatch: Fix speaker mapping for Helios
The correct mapping for speakers to their names should be:

uid 0: Woofer Left
uid 1: Woofer Right
uid 2: Tweeter Left
uid 3: Tweeter Right

Also, fix the name to be 4-character.

BUG=b:140397934, b:143192767
BRANCH=none
TEST=On Helios, with patch series, check realtek,r0_calib and
realtek,temperature_calib are available to rt1011 codec driver.
And the speaker mapping is correct.

Change-Id: I353fb9ad0ca8ec85431eb2b59be748b4887278cf
Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36256
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25 03:12:00 +00:00
Ronak Kanabar 489c10ee54 src/vendorcode/intel: Update Comet Lake FSP headers as per FSP v1394
"EnforceEDebugMode" UPD added in FSP_S_TEST_CONFIG

Change-Id: I1583d8583db20b29505e5a7ae4084013334c87c2
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35852
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25 02:05:12 +00:00
Peichao Wang 6536084163 mb/google/hatch/var/akemi: Update DPTF thermal sensor for Akemi
Add thermal sensor: TSR2 to ACPI table, monitor CPU temperature

BUG=b:143046086
TEST=FW_NAME="akemi" emerge-hatch coreboot chromeos-ec
chromeos-bootimage

Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Id150c5c3cb6d07407fd20417237457b5722e6f2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Philip Chen <philipchen@google.com>
2019-10-24 21:58:55 +00:00
Justin Frodsham ddd02da1de soc/amd/picasso: Remove duplicate AMD_PUBKEY_FILE from Kconfig
BUG=b:143229128
Change-Id: I03aa12b16979dc07869b0d33daedcde4fe84bc27
Signed-off-by: Justin Frodsham <justin.frodsham@amd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36281
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24 21:11:09 +00:00
Marty E. Plummer 5fc8805a71 Documentation: trivial typo fix strcut/struct
Change-Id: I5e7d8e8a95e5bef23307eb50456a89e0e23c445a
Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-24 16:27:47 +00:00
Elyes HAOUAS 0688bce81c src/include/console: Get rid of unused deprecated POST codes
Change-Id: Id577b7c1421e9ffc3f51e90fcc9330c8f3be9a56
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-24 16:09:30 +00:00
Tony Huang 81e3b74301 mb/google/octopus: Override VBT selection for Dorp/Vortininja/Vorticon
Add enum for Vorticon sku.

Vortininja/Vorticon will load vbt_vortininja.bin
Dorp will load vbt_dorp.bin

BUG=b:143197918
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage
     check i915_drrs_status shows DRRS supported NO
     when SKU-ID sets to Dorp/Vortininja/Vorticon.

Change-Id: I67d7a8ab62a1838b0a0a05f532d8b067ece686d9
Cq-Depend: chrome-internal:2026287
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-10-24 15:52:52 +00:00
Elyes HAOUAS e4b9a1e156 mb/google/{butterfly,link,parrot}: Drop wrong _ADR objects
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID
object or an _ADR object, but should not contain both."

Found-by: ACPICA 20191018
Change-Id: I8bcdfa7a4dc33c3e3866d3135249a602379b9615
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36265
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24 15:52:41 +00:00
Elyes HAOUAS fe3a19d3f3 src/ec/quanta: Drop wrong _ADR objects
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID
object or an _ADR object, but should not contain both."

Found-by: ACPICA 20191018
Change-Id: Iaa35790a38c36091a228007d739b970cb66a3e1c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36264
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24 15:52:16 +00:00
Elyes HAOUAS d624e3997a (acpi) superio.asl: Drop wrong _ADR objects
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID
object or an _ADR object, but should not contain both."

Found-by: ACPICA 20191018
Change-Id: Ic0bcaa37ac017ab61e1fb4e78d3c7dfbbcc0899d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-10-24 15:52:05 +00:00