Commit Graph

53505 Commits

Author SHA1 Message Date
Patrick Rudolph b403849a43 soc/intel/xeon_sp: Remove invalid comment
The comment is only true if all sockets have working CPUs installed.

Change-Id: I8c3376c9233c33fb770082573e07e9d96abb7855
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76557
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-07-18 06:56:03 +00:00
Patrick Rudolph b096d625d5 soc/intel/xeon_sp: Introduce soc_cpu_is_enabled
Add a function to check if the CPU placed at the specified socket was
found usable during QPI init. This is useful for multi-socket
platforms were a CPU is missing or has been disabled due to an error.

Change-Id: I135968fcc905928b9bc6511e3ddbd7d12bad0096
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-07-18 06:55:27 +00:00
Patrick Rudolph 971ea286dd soc/intel/xeon_sp: Print HOB for all sockets
Use the FSP define to iterate over all sockets as the runtime value of
numofIIO is the detected number of sockets, not the highest working
socket.

This fixes printing the HOB on multi-socket platforms where a CPU has
been removed or has been disabled (4S system running as 3S).

Change-Id: Ieed67cd48d26c7634636c0aae6a56f3b6fbdf640
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76492
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18 06:53:57 +00:00
Yunlong Jia 9e4968a623 mb/google/nissa/var/gothrax: Set up driver as per schematics
Drivers for Pen Garage/SDCard Reader/LTE/SAR/WWAN and I2C for TPM.

BUG=b:274707912
BRANCH=None

Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I1203ca13bd55b8ab96ce5d323a36ffde06860fa9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76104
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyle Lin <kylelinck@google.com>
2023-07-18 05:53:37 +00:00
Kane Chen 70c6fb4251 soc/intel/meteorlake: Enable PCIE_CLOCK_CONTROL_THROUGH_P2SB
On Intel Meteor Lake (MTL), PCIe CLK control register is accessed by
P2SB on IOE/SOC die.
So this patch does:
1. Enable PCIE_CLOCK_CONTROL_THROUGH_P2SB
2. Include pcie_clk.asl
3. Set the correct IOE_DIE_CLOCK_START for MTL-U/H.

BUG=b:288976547, b:289461604
TEST=Test on google/screebo and found the pcie clock is on/off properly
and sdcard PCIe port doesn't block S0ix with RTD3 cold enabled.

Change-Id: I6788ae766f36c9a0d4910fda1d6700f20ce73ea8
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76356
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18 05:31:42 +00:00
Kane Chen fa77ac93c5 soc/intel/common/acpi: Support on/off PCIe CLK by P2SB
In the older platform such as Raptor Lake (RPL), Tiger Lake (TGL), it
needs PMC IPC cmd to turn on/off the corresponding clock.

Now on Meteor Lake (MTL), it control pcie clock registers on P2SB on
IOE or SoC die.

BUG=b:288976547, b:289461604
TEST=Test on google/screebo and found the pcie clock is on/off properly
and sdcard pcie port doesn't block S0ix with RTD3 cold enabled.

Change-Id: Ia729444b561daafc2dca0ed86c797eb98ce1f165
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76347
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18 05:31:15 +00:00
Subrata Banik fadda4ae6b soc/intel/meteorlake: Include IOE PCR register access
This patch includes the ioe_pcr.asl file as Intel Meteor Lake has
support for IOE die.

BUG=b:290856936
TEST=Able to build and boot google/rex.

Change-Id: Ia534dbc0db5e54e173da9cdf475a7eb2bfda9e2f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76410
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-18 05:31:04 +00:00
Subrata Banik 649709c6fc soc/intel/common/acpi: Add IOE PS2B access APIs
This patch implements APIs to access PCR registers from IOE die.

BUG=b:290856936
TEST=Able to build and boot google/rex.

Change-Id: Ief7a00c4e81048f87ee308e659faeba3fde4c9cd
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76409
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-07-18 05:30:52 +00:00
Subrata Banik 5557fbe406 soc/intel/meteorlake: Add IOE P2SB Base Address
This patch introduces a new config named IOE_PCR_BASE_ADDRESS to define
P2SB base address.

BUG=b:290856936
TEST=Able to build and boot google/rex.

Change-Id: I289358f9c53b557a397bd7186e6b7419c5d8c954
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76411
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18 05:30:39 +00:00
Subrata Banik 4a53ba738d soc/intel/common/acpi: Create helper APIs for common P2SB access
This patch creates a helper library to migrate all the common P2SB
access routines. The PCH P2SB ACPI implementation will now rely on the
common library to perform PCR read/write operations. This will make the
code more modular and easier to maintain.

The helper library provides a single interface for accessing P2SB
registers. This makes it easier to port the code to different platforms,
for example: adding support for PS2B belongs to the IOE die for
Meteor Lake SoC generation.

BUG=b:290856936
TEST=Able to build and boot google/rex.

Change-Id: I0b2e7ea416ca7082f68d0b822ebb9a87025b4a8b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76408
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18 05:30:25 +00:00
Arthur Heymans 8554954f9c nb/intel/i945: Rework nb resource reading
- Use newer functions and avoid the * / KiB dance
- Use existing functions for figuring out TSEG and UMA

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I73549b23bd1bfd4009e6467a5bdfeef7de81a0cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76272
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-17 17:21:14 +00:00
Arthur Heymans a5543aeae6 nb/haswell: Use newer function for resource declarations
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ib649943e13b9b319297c4be68b7039b760ebd820
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-07-17 17:20:52 +00:00
Nico Huber 99eee16a13 Center bootsplash on bigger framebuffers
In the JPEG decoder, use `bytes_per_line` instead of `width` for
address calculations, to allow for bigger framebuffers. When
calling jpeg_decode(), add an offset to the framebuffer address
so the picture gets centered.

Change-Id: I0174bdccfaad425e708a5fa50bcb28a1b98a23f7
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-17 14:49:04 +00:00
Arthur Heymans 9b186e0ffe util/xcompile: Add NASM to xcompile
Reason: opensil uses nasm code.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ib8d89354bfd21113f77927186e418e2ec3eab44c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76465
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-17 14:18:29 +00:00
Felix Held 9ab8a78d7e soc/amd/common/acpimmio: factor out IO port access to PM registers
Factor out all functions that use the indirect IO port based access to
the PM registers into a new compilation unit and only select it on
platforms that support this interface.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If9c059e450e2137f7e05441ab89c1f0e7077be9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-17 14:12:57 +00:00
Felix Held 36149888f6 soc/amd/common/pm/pmlib: use PM register mapping in ACPIMMIO region
In all SoC pm_set_power_failure_state gets called either after a call to
enable_acpimmio_decode_pm04() or the ACPIMMIO mapping is already enabled
after reset on the SoC. This allows to use pm_read8 and pm_write8 that
use the ACPIMMIO mapping of the PM registers instead of pm_io_read8 and
pm_io_write8 which won't work on Phoenix and Glinda due to the IO ports
used on older generations to access to the PM registers not being
implemented any more.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id0d0523d2c4920da41b3fb73cf62f22a60f1643a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-07-17 14:12:13 +00:00
Felix Held 0f5f2ceb55 sb/amd/pi/hudson/enable_usbdebug: use pm_io_write8
Use pm_io_write8 instead of open coding the same functionality.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1d9397f2d85e48883f961adbbca0e1e71e825ce0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-07-17 14:11:49 +00:00
Patrick Georgi e4d660b2dc crossgcc: Enable rv32iafc-ilp32 configuration
rv32iafc-ilp32 is compatible with rv32iac-ilp32 for library
implementation, so add a reuse rule allowing the default configuration
to support rv32iafc.

-IAFC is an unusual configuration (much less common than -IMAFC),
but multilib reuse has essentially no cost: this change is useful to
users of platforms that support hardware floating-point but cannot
use hardware multiply/divide for any reason. To avoid generating a
new set of libraries this is limited to the soft-float ABI.

Tested by verifying that `gcc -march=rv32iafc -mabi=ilp32
--print-search-dirs` refers to the rv32iac/ilp32 library directory
as expected, rather than just the root library directory as occurs
when an unsupported target is selected (for instance, rv32id).

Change-Id: Ie056ba6488a138fe0876eebf7cbc59477b3c3518
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-07-17 13:57:12 +00:00
Anand Vaikar 9922a8b363 mb/amd/mayan: Enable the PCIe bridge for DT/M.2 SSD1 slots
Change-Id: I5c5b125ac03e07a22bcc15ad2d34c62edf74ee04
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76452
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-17 03:31:31 +00:00
Felix Held 854491db63 soc/amd/common/lpc/lpc_util: use PM register mapping in ACPIMMIO region
In all SoC lpc_early_init gets called either after a call to
enable_acpimmio_decode_pm04() or the ACPIMMIO mapping is already enabled
after reset on the SoC. This allows to use pm_read8 and pm_write8 that
use the ACPIMMIO mapping of the PM registers to set the PM_LPC_ENABLE
bit in the PM_LPC_GATING register instead of pm_io_read8 and
pm_io_write8 which won't work on Phoenix and Glinda due to the IO ports
used on older generations to access to the PM registers not being
implemented any more.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8b31ec4e03a06796502c89e3c2cfaac2d41b0ed9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76461
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-17 03:27:47 +00:00
Zhongtian Wu 0c9549a058 mb/google/rex/var/screebo: Update I2C timing
Change i2c[0] parameter Thd:dat = 50ns;
Change i2c[1] parameter Thd:dat = 100ns;

BUG=b:287898252
BRANCH=none
TEST=Test success by EE.

Change-Id: Ibdbe4e17cf21c914b48fa6dc7d3eecf8218a2d8b
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76430
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-17 03:25:44 +00:00
Felix Held 5bd68097cb soc/amd/common/acpimmio/mmio_util: drop enable_acpimmio_decode_pm24
None of the platforms that used enable_acpimmio_decode_pm24 is in the
tree any more, so drop this function.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iea345a825c4581bf2acb932692ebcad2a7a5b4ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-07-17 03:25:32 +00:00
Felix Held 8336c72524 soc/amd/glinda/early_fch: don't call enable_acpimmio_decode_pm04
The enable_acpimmio_decode_pm04 function uses the IO port based indirect
access of the PM register space. The PM_INDEX and PM_DATA registers
don't exist any more on Glinda, so the code shouldn't access those.
Since the PM_04_ACPIMMIO_DECODE_EN bit in the
ACPIMMIO_DECODE_REGISTER_04 register is 1 after reset, the ACPIMMIO
space is still accessible.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic6bc0479ea4ea2b9fe3629a6e15940b31b2864d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-07-17 03:25:00 +00:00
Felix Held 9c0bce5f28 soc/amd/phoenix/early_fch: don't call enable_acpimmio_decode_pm04
The enable_acpimmio_decode_pm04 function uses the IO port based indirect
access of the PM register space. The PM_INDEX and PM_DATA registers
don't exist any more on Phoenix, so the code shouldn't access those.
Since the PM_04_ACPIMMIO_DECODE_EN bit in the
ACPIMMIO_DECODE_REGISTER_04 register is 1 after reset, the ACPIMMIO
space is still accessible.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia41f239b023edc094f5cbae63ed7c079649c74da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76437
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-17 03:24:37 +00:00
Subrata Banik 7627208ad7 mb/google/rex: Disable early EC sync
This patch disables early EC sync to avoid an idle delay (~3sec)
without a provision to notify the user about some critical task
in progress.

Doing EC sync at later stage allows us to notify using graphical msg
on screen to make user aware of the WIP task.

BUG=b:279944831
TEST=Able to perform EC sync from depthcharge on google/rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I03ed40827c50e75ceaaf94e30d675014ebf22dac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-07-17 03:23:35 +00:00
Michał Żygowski cd3a99eaf9 mb/msi/ms7d25: Disable DMI ASPM
Disable DMI link ASPM which can degrade performance of overall system.
Desktop does not need to be concerned that much about idle power
consumption.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I60af9d2ab2913db449059e1e007999fa2f307f5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69826
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-17 03:22:46 +00:00
Zhongtian Wu 1f17ba5563 mb/google/rex/var/screebo: Update touchscreen GPIO
Change touchscreen reset_gpio GPP_C01 -> GPP_D07;
Change touchscreen enable_gpio GPP_C00 -> GPP_B17.

BUG=b:289425753
BRANCH=none
TEST=Test success by EE.

Change-Id: I7be6a2b4e87126b281f138c819d2a0a5b1af5821
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-17 03:21:01 +00:00
Tim Crawford 6466281faf drivers/pc80/tpm: Add Infineon SLB9672 ID
Allows the new Infineon TPM chip used on Clevo laptops to be recognized.

Change-Id: I2ee31b787d80c0b9c24c748b1b28906a22a1dee7
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-07-17 03:20:17 +00:00
Rex Chou 50d3a64dcf mb/google/nissa: Create craaskov variant
Create the craaskov variant of the nissa reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)

BUG=b:290248526
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_CRAASKOV

Change-Id: I1d12f7c3d0ef7067f4530c1c69c560f9a83561f6
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2023-07-17 03:18:55 +00:00
Tyler Wang 35e9ffe8cc mb/google/rex/var/karis: Generate SPD ID for supported memory part
Add karis supported memory parts in mem_parts_used.txt, generate
SPD id.

1. MICRON MT62F1G32D2DS-023 WT:B
2. HYNIX H9JCNNNBK3MLYR-N6E
3. HYNIX H58G56BK8BX068
4. SAMSUNG K3KL8L80CM-MGCT

BUG=b:291018417
TEST=Use part_id_gen to generate related settings

Change-Id: I87c2c4f59454dec84d29590ee91379c9fa60ddcf
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76443
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-17 03:18:09 +00:00
Tim Crawford 198c6291e0 soc/intel/adl: Add power limits for RPL-H 4P+8E 45W
Change-Id: I01ae5a484287d2adb1516e1e4551b185b895fdde
Ref: RPL-UPH and RPL-U Refresh Platform Design Guide (#686872, rev 2.1)
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-17 03:14:42 +00:00
Arthur Heymans 22c9335846 soc/intel/denverton: Use newer function for resource declarations
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Id092b6dd9d42f2965801b0327a857a5a4945f793
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76288
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-17 02:20:38 +00:00
Kapil Porwal 400f1aade8 soc/intel/common: Add support for AP initiated mode entry
Add support for AP initiated mode entry. The code flow has been
optimized as below -

Code flow when AP initiated mode entry is disabled:
          +-------+
          | Start |
          +---+---+
              |
              |
    +---------+---------+
    |wait_for_connection|
    |   Is DP ALT mode  |
    |     available?    |
    +---------+---------+
              |
              +--------------->-------+
           Yes|                 No    |
    +---------+---------+             |
    |Skip enter_dp_mode |             |
    +---------+---------+             |
              |                       |
              |                       |
  +-----------+----------+            |
  |wait_for_dp_mode_entry|            |
  |   Is DP flag set?    |            |
  +-----------+----------+            |
              |                       |
              +--------------->--------
           Yes|                 No    |
  +-----------+----------+            |
  |     wait_for_hpd     |            |
  | Is HPD_LVL flag set? |            |
  +-----------+----------+            |
              |                       |
              +--------------->--------
           Yes|                 No    |
  +-----------+----------+            |
  |    Rest of the code  |            |
  +-----------+----------+            |
              |                       |
              +---------------<-------+
              |
          +---+---+
          |  End  |
          +-------+

Code flow when AP initiated mode entry is enabled:
          +-------+
          | Start |
          +---+---+
              |
 +------------+-----------+
 |Skip wait_for_connection|
 +------------+-----------+
              |
     +--------+-------+
     |  enter_dp_mode |
     | Is USB device? |
     +--------+-------+
              |
              +--------------->-------+
           Yes|                 No    |
    +---------+---------+             |
    |   enter_dp_mode   |             |
    |    Send DP mode   |             |
    |   entry command   |             |
    +---------+---------+             |
              |                       |
  +-----------+----------+            |
  |wait_for_dp_mode_entry|            |
  |   Is DP flag set?    |            |
  |  (If not, loop wait  |            |
  |   until timed out)   |            |
  +-----------+----------+            |
              |                       |
              +--------------->--------
           Yes|                 No    |
  +-----------+----------+            |
  |     wait_for_hpd     |            |
  | Is HPD_LVL flag set? |            |
  |  (If not, loop wait  |            |
  |   until timed out)   |            |
  +-----------+----------+            |
              |                       |
              +--------------->--------
           Yes|                 No    |
  +-----------+----------+            |
  |    Rest of the code  |            |
  +-----------+----------+            |
              |                       |
              +---------------<-------+
              |
          +---+---+
          |  End  |
          +-------+

BUG=b:247670186
TEST=Verify display over TCSS and its impact on boot time for
google/rex

Time taken by enter_dp_mode / wait_for_dp+hpd / MultiPhaseSiInit
functions with this patch train:

1. When AP Mode entry is enabled
- With type-c display on C1 and SuzyQ on C0: 6.9ms / 420ms / 616ms
- With USB key on C1 and SuzyQ on C0       : 6.0ms / 505ms / 666ms
- Without any device on C1 and SuzyQ on C0 : 3.7ms /   0ms / 178ms

2. When AP Mode entry is disabled
- With type-c display on C1 and SuzyQ on C0: 1.7ms / 2.5ms / 213ms
- With USB key on C1 and SuzyQ on C0       : 0.9ms / 3.3ms / 177ms
- Without any device on C1 and SuzyQ on C0 : 0.8ms / 1.8ms / 165ms

Without this patch train, wait_for_hpd would cause a constant delay of
WAIT_FOR_HPD_TIMEOUT_MS (i.e. 3 seconds) per type-c port when there is
no device connected.

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I514ccbdbaf905c49585dc00746d047554d7c7a58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-15 12:48:01 +00:00
Kapil Porwal 2ba4b1bebe ec/google/chromeec: Split wait-loop for DP and HPD flags
Split wait-loop for DP and HPD flags as below -
- google_chromeec_wait_for_hpd
- google_chromeec_wait_for_dp_mode_entry

BUG=b:247670186
TEST=Verify display over TCSS and its impact on boot time for
google/rex

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I3e565d6134f6433930916071e94d56d92dc6cb06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76370
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-15 12:47:51 +00:00
Kapil Porwal 1d85464df8 ec/google/chromeec: Call `wait_for_dp_hpd` only in AP mode entry
Wait for DP/HPD flags only in AP initiated mode entry

BUG=b:247670186
TEST=Verify display over TCSS and its impact on boot time for
google/rex

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I5137c346fbf1edabc60a53e0978e32f54885c330
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76369
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-15 12:47:44 +00:00
Kapil Porwal 9a127bf2d1 ec/google/chromeec: Skip TCSS `wait_for_connection` for AP mode entry
Skip TCSS `wait_for_connection` for AP initiated mode entry.

BUG=b:247670186
TEST=Verify display over TCSS and its impact on boot time for
google/rex

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ia04ff470961831237fe851f7ae3feaa5623d4b4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76368
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-15 12:47:12 +00:00
Kapil Porwal c2c5801dcd ec/google/chromeec: Skip unnecessary call to TCSS `enter_dp_mode` cmd
Skip TCSS `enter_dp_mode` command when there is no USB device detected
on the port.

BUG=b:247670186
TEST=Verify display over TCSS and its impact on boot time for
google/rex

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ie6cd84cab3631596d4d7178dae2040e25c621f63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-15 12:47:02 +00:00
Elyes Haouas ba7fee9159 util/intelmetool: Remove useless break after a break
Change-Id: Ifb76d8fa09585ad6da9bfb1488a15bf853c4da99
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-07-15 06:06:48 +00:00
Elyes Haouas 6319ee2cf7 mb/amd/mayan: Remove useless break after return
Change-Id: Iad0244e798c03a26f755024453ecdd745e6286f3
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76473
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-15 06:06:17 +00:00
Elyes Haouas 6fedb56fd4 mb/amd/chausie: Remove useless break after return
Change-Id: Iafc3735b6d903a4496828189db14b09d3c4d2081
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76432
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-15 06:05:48 +00:00
Martin Roth 6ed71fd2ad mb/google/myst: Remove PRESERVE FMD flag for RW_MRC_CACHE
The PRESERVE flag in the FMD file tells futility not to erase the
fmap partition when updating the firmware.  Because of an issue on
myst right now, we want the RW_MRC_CACHE partition to be erased
when the firmware is updated.

BUG=b:290763369
TEST=None

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id586ae057b2fd6d513ddbba5e1284dea39467d95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76478
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-14 23:23:44 +00:00
Felix Held 5d65c819a9 vc/amd/fsp/phoenix/FspmUpd: drop eMMC-related UPDs
Phoenix doesn't have an eMMC controller and those UPDs were carried over
from Picasso. The SoC's fsp_m_params.c didn't write to any of those
fields, so this doesn't change any behavior.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie3640c1493a92c1effba3ce42103d022bd8399ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-14 21:57:34 +00:00
Martin Roth c987d7b7d3 soc/amd/common: Add warning if microcode CBFS filename is in use
Because of the way that the CBFS filename is generated from the contents
of the microcode patch, if a duplicate microcode patch is included in
the build, the makefile would create a second copy of the name, which
doesn't work.  This led to "odd" results where the other attributes of
the first copy were erased, causing cbfstool to fail. The cause of the
failure is not immediately obvious, and is a little difficult to track
down.

This patch causes an immediate failure and gives a reason as to the
cause of the issue.

When a failure is seen, this is the result:
File1: 3rdparty/amd_blobs/phoenix/psp/TypeId0x66_UcodePatch_PHXn4_A0.bin
File2: 3rdparty/amd_blobs/phoenix/psp/TypeId0x66_UcodePatch_PHX4_A0.bin
src/soc/amd/common/block/cpu/Makefile.inc:25: *** Error: The cbfs
filename "cpu_microcode_a740.bin" is used for both above files. Check
your microcode patches for duplicates..  Stop.

TEST=Now checked for both positive and negative failures.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I3d34dc5585182545bdcbfa6370ebc34aa767cae2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76423
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-14 21:42:43 +00:00
Tim Crawford e3bbd72857 soc/intel/cannonlake: Hook up ucode for CML-S
Hook up microcode from 3rdparty repo for:

- 06-a5-03 (CPUID signature: 0xa0653)
- 06-a5-05 (CPUID signature: 0xa0655)

Fixes loading microcode on system76/bonw14.

Change-Id: Ie6789420926fe46fc61ea6773f02dc07dc2e9b5e
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-07-14 18:49:33 +00:00
Tim Crawford 40c1a41b2d mb/system76: Drop VGA_BIOS_ID
System76 boards use the VBT data file, not the VGA optionrom.

Change-Id: Ie4100e09221ae4f301a621e7aac62e38ac04a444
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-07-14 18:49:09 +00:00
Karthikeyan Ramasubramanian 2118fb1f69 soc/amd/phoenix: Disable APOB Cache
There is a data abort in ABL when the memory training data is used from
APOB Cache. Disable APOB Cache until the cause is identified. The
downside of this change is that the memory training happens in every
boot cycle.

BUG=b:290763369
TEST=Build BIOS image and boot to OS in Myst. Trigger a reboot from AP
console and ensure that the system boots to OS.

Change-Id: I20f4f40cdaac68bca6e121e3a238d13fe80d0d3c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-14 18:16:03 +00:00
Felix Singer ebafd4b905 util/crossgcc: Update GCC version from 11.3 to 11.4
Change-Id: Ia9063af4495735a0e47f4cab1179441185d888b3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-07-14 18:04:14 +00:00
Felix Held 2e9a396ffb vc/amd/fsp/glinda/platform_descriptors: add dxio_port_param_type TODO
The dxio_port_param_type enum was copied over from Cezanne, but the enum
on the AGESA/FSP side changed between the generations. Add a TODO as a
reminder that this needs to be updated.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8063ab00a508b045265bab73197c8ca117622800
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76448
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-14 16:49:55 +00:00
Felix Held d1c33aeef4 mb/amd,google/*/port_descriptors: use dxio_link_hotplug_type enum values
Use the proper dxio_link_hotplug_type enum values for the link_hotplug
field in the DXIO descriptors to replace the magic values in the code.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ieb1513737e6022a668287dc80a39d96cda2b18d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76439
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-14 16:49:37 +00:00
Felix Held e479b3e356 vc/amd/fsp/*/platform_descriptor: add dxio_link_hotplug_type enum
Add the dxio_link_hotplug_type enum definition for the link_hotplug
field in the DXIO descriptor struct.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ieeb3e3edaed2c689707edc4df7d25c777005fde2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-14 16:49:18 +00:00