Instead of performing the same tasks in the chipset code move
the common sequences into the FSP 2.0 driver. This handles the
S3 paths as well as saving and restoring the memory data. The
chipset code can always override the settings if needed.
BUG=chrome-os-partner:52679
Change-Id: I098bf95139a0360f028a50aa50d16d264bede386
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15739
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
The amount of reserved memory just below the DRAM limit in
32-bit space is defined in the FSP 2.0 specification within
the FSPM_ARCH_UPD structure. There's no need to make the
chipset code set the same value as needed for coreboot.
The chipset code can always change the value if it needs
after the common setting being applied.
Remove the call in soc/intel/apollolake as it's no longer
needed.
BUG=chrome-os-partner:52679
Change-Id: I69a1fee7a7b53c109afd8ee0f03cb8506584d571
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15738
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Fix issue where zero-sized BIOS region could cause bitshift
for '-1' which is an unspecified behavior.
Change-Id: Icb62bf413a1a0d293657503ef21fe97b5f9a5484
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15727
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since the Integrated Sensor Hub can be disabled through devicetree.cb
as a PCI device, there is no need for a separate register variable.
Remove handling the register and update mainboards' devicetrees. Also
keep ISH disabled on both Reef and Amenia.
Change-Id: I90dbf57b353ae1b80295ecf39877b10ed21de146
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15710
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
1. The hotplug feature needs to be disabled
so that pcie root ports will be disabled by fsp
2. Correct PcieRootPortEn mapping.
The correct mapping should be like below
PcieRootPortEn[0] ==> 00:14.0
PcieRootPortEn[1] ==> 00:14.1
PcieRootPortEn[2] ==> 00:13.0
PcieRootPortEn[3] ==> 00:13.1
PcieRootPortEn[4] ==> 00:13.2
PcieRootPortEn[5] ==> 00:13.3
BUG=chrome-os-partner:54288
BRANCH=None
TEST=Checked pcie root port is disabled properly
and make sure pcie ports are coalesced.
Also make sure the device will still be enabled after coalescence
when pcie on function 0 is disabled devicetree
Change-Id: I39c482a0c068ddc2cc573499480c3fe6a52dd5eb
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/15595
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds the support for gpio_tier1_sci_en bit which
needs to be set before going to sleep so that when
gpio_tier1_sci_sts bit gets set platform can wake
from S3.
BUG = chrome-os-partner:53992
TEST = Platform wakes from S3 on lidopen,key press.
Tested on Amenia and Reef boards.
Change-Id: I3ba79fa53ca8817149d585fa795a8f427c128dcb
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15612
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
FSP is currently setting a hard-coded policy for the interrupt
polarity settings. When the mainboard has already set the GPIO
settings up prior to SiliconInit being called that results
in the previous settings being dropped. Work around FSP's
default policy until FSP is fixed.
BUG=chrome-os-partner:54955
Change-Id: Ibbd8c4894d8fbce479aeb73aa775b67df15dae85
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15649
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
For APIC routed gpios, set the corresponding interrupt polarity
for the associated IRQ based on the gpio pad's invert setting.
This allows for the APIC redirection entries to match the hardware
active polarity once the double inversion takes place to meet
apollolake interrupt triggering constraints.
BUG=chrome-os-partner:54955
Change-Id: I69c395b6f861946d4774a4206cf8f5f721c6f5f4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15648
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The interrupt and timer subsystem (ITSS) sits between the APIC
and the other logic blocks. It only supports positive polarity
events, but there's a polarity inversion setting for each IRQ such
that it can pass the signal on to the APIC according to the
expected APIC redirection entry values. This support is needed
in order for the platform/board to set the expected interrupt
polarity into the APIC for gpio signals.
BUG=chrome-os-partner:54955
Change-Id: I50ea1b7c4a7601e760878af515518cc0e808c0d1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15647
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Internally, apollolake routes its interrupts as active high.
This includes SCI, SMI, and ACPI. Therefore, provide helper
macros such that the user can describe an interrupt's active
high/low polarity more easily. It helps for readability when
one is comparing gpio configuration next to APIC configuration
in different files. Additionally, the gpio APIC macros always
use a LEVEL trigger in order to let the APIC handle the
filtering of the IRQ on its own end.
BUG=chrome-os-partner:54977
Change-Id: Id8fdcd98f0920936cd2b1a687fd8fa07bce9a614
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15644
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Change-Id: I195fd3a9c7fc07c35913342d2041e1ffef110466
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15549
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch adds the handler to enable bit for gpio_tier1_sci_en.
gpio_tier1_sci_en enables the setting of the GPIO_TIER1_SCI_STS
bit to generate a wake event and/or an SCI or SMI#. We are setting
the bit for gpio_tier1_sci_en from the ASL code as OS clears this bit
if set from BIOS. As per ACPI spec _GPE is defined as the Named
Object that evaluates to either an integer or a package. If _GPE
evaluates to an integer, the value is the bit assignment of the SCI
interrupt within the GPEx_STS register of a GPE block described in
the FADT that the embedded controller will trigger. FADT right now
has no mechanism to acheive the same.
Change-Id: I1e1bd3f5c89a5e6bea2d1858569a9d30e6da78fe
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15578
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add the gpio_defs.h reference in chip.h to enable
reef and amenia devicetree.cb to use the definitions from gpio_defs.h.
Change-Id: I333d4e810e42309ac76dd90c19f05cf3e3a517b1
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/15550
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Instead of having all the mainboards put similar logic
into their own code provide common mechanism for memory
SKU selection. A function, meminit_lpddr4_by_sku(), is
added that selects the proper configuration based on the
SKU id and configuration passed in. LPDDR4 speed as well
as DRAM device density configuration is associated for
each logical channel per SKU id.
BUG=chrome-os-partner:54949
BRANCH=None
TEST=Built and used on reef for memory config.
Change-Id: Ifc6a734040bb61a58bc3d4c128a6420a71245c6c
Signed-off-by: Aaron Durbin <adurbin@chromuim.org>
Reviewed-on: https://review.coreboot.org/15559
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The internal pulls for gpio_input_pullup() and gpio_input_pulldown()
were using fairly strong pulls. Weaken them so that external pulls
can override the internal ones. This matches the current assumptions
of lib/gpio.c.
BUG=chrome-os-partner:54949
BRANCH=None
TEST=Built and used on reef for memory config.
Change-Id: Ifda1d04d40141325f78db277eb0bd55574994abf
Signed-off-by: Aaron Durbin <adurbin@chromuim.org>
Reviewed-on: https://review.coreboot.org/15558
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch adds the basic framework for SCI to GPE routing code.
BUG = chrome-os-partner:53438
TEST = Toogle pch_sci_l from ec console using gpioset command and
see that the sci counter increases in /sys/firmware/acpi/interrupt
and also 9 in /proc/interrupts.
Change-Id: I3b3198276530bf6513d94e9bea02ab9751212adf
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15324
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
On Apollolake CSE can be used to fetch firmware from boot media. However,
when this feature is not used, CSE needs to be explicitly notified of it
before memory training is complete. This way it can transition to next
state.
BUG=chrome-os-partner:53876
TEST=CSE can be power-gated during S0iX. Confirmed with LTB.
Change-Id: I5141bff350b6c0bb662424b7b709f0787ec5fd28
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15494
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add the Audio DSP device for apollolake as a PCI driver with a static
scan_bus handler so generic devices can be declared under it.
This is for devices like the Maxim 98357A which is connected on the
I2S bus for data but has no control channel bus and instead just has
a GPIO for channel selection and power down control and needs to
describe that GPIO connection to the OS via ACPI.
Change-Id: Icb97ccf7d6a9034877614d49166bc9e4fe659b12
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/15528
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The P2SB device is device 0xd and function 0. If hidden that
causes the latter pci devices on function >= 1 to not be probed
in the kernel. This is also a problem for coreboot if the P2SB
device is hidden by FSP. That means the coreboot driver won't
be ran. Therefore, provide hide and unhide functions for the
P2SB device.
The other quirk is to allow the GPIO devices to work correctly.
Those devices are ACPI devices. However, their resources are
sub-regions within the P2SB BAR. Sadly, linux doesn't handle
ACPI devices being children of PCI devices. This leads to resource
conflict errors when the P2SB device is visible. For the
time being keep the P2SB device hidden, but also ensure the
resources it is using are accounted for and reserved. The fallout
of that is the PMC and SPI device are no longer probed by the
kernel.
BUG=chrome-os-partner:53017
TEST=Ensured P2SB device is visible and pci resources are allocated
correctly for the devices.
Change-Id: I24e59bbde74310e1ce8425b344a3ad0b88702153
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15530
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There are four GPIO communities in this SOC and they are implemented
as separate ACPI devices. This means the pin number that is used in
an ACPI GPIO declaration needs to be relative to the community that
the pin resides in. Also select GENERIC_GPIO_LIB in the SOC Kconfig
so this function actually gets used.
This was tested on the reef mainboard by verifying the output of the
SSDT for the Maxim 98357A codec that the assigned GPIO_76 is listed
as pin 0x24 which is the value relative to the Northwest community.
Change-Id: Iad2ab8eccf4c91185a075ffce8d41c81f06c1113
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15513
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Support the I2C interfaces on this SOC using the Intel common lpss_i2c
driver. The controllers are supported in pre-ram environments by
setting a temporary base address in bootblock and in ramstage using
the naturally enumerated base address.
The base speed of this controller is 133MHz and the SCL/SDA timing
values that are reported to the OS are calculated using that clock.
This was tested on a google/reef board doing I2C transactions to the
trackpad both in verstage and in ramstage.
Change-Id: I0a9d62cd1007caa95cdf4754f30c30aaff9f78f9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15480
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add support for the soc_acpi_name() handler in the device operations
structure to translate a device path into ACPI name.
In order to make this more complete add some missing devices in
include/soc/pci_devs.h.
Change-Id: I517bc86d8d9fe70bfa0fc4eb3828681887239587
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15479
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Every other platform has global_nvs_t as a typedef. For some
reason apollolake didn't bother following current conventions.
Fix this omission to allow for better code sharing and consistency.
Change-Id: Id596eed517737759a64ce803c89ea2a05cbe2cce
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15502
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
This patch exposes a function to read pmc bar.
PMC bar is read in function read_pmc_mmio_bar which
is defined static in file pmutil.c. This patch exposes
that functionality to call it from other files.
BUG=chrome-os-partner:53438
TEST= Read the PMC bar value properly from outside
pmutil file.
Change-Id: I26ee13e6ab95d3a8991c7f8ea4b3856ceb015d10
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15460
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change PCI macros in such a way they can be transparently used across
romstage and ramstage.
Change-Id: Idc708c1990f2fc1d941bb82efcb0a697524f2eca
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15483
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
New UPDs added to header files as well as many comment fixes. Memory
infor is now defined in FspmUpd.h and added ability to skip CSE RBP
for coreboot. Removes some UPDs that are no longer available from
source.
BUG=chrome-os-partner:54677
BRANCH=none
TEST=built and tested with FSP 143_10 version
Change-Id: I7e1f531ebbe343b45151a265ac715ae74aeffcad
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/15459
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add the audio controller device to ACPI and define the _DSM handler
to return the address of the NHLT table, if set in NVS.
Change-Id: I619dbfb562b94255e42a3e5d5a3926c28b14db3e
Signed-off-by: Saurabh Satija <saurabh.satija@intel.com>
Reviewed-on: https://review.coreboot.org/15026
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
This will allow kernel to trigger a APM SMI to enable\disable SCI
Change-Id: I1be79b7a3082c23fbaf204eff55360c46458e325
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/15347
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Parse the devicetree and pass the unused device to fsp
for disabling the device function.
BRANCH=none
BUG=chrome-os-partner:54325
TEST=device off in devicetree should disable the device.
Change-Id: I784b72a43fda13aa17634bf680205ab2d36e8d09
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://review.coreboot.org/15337
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Add support for vboot_platform_prepare_reboot which is called whenever
vboot requests reboot of the platform. SLP_TYPE needs to be set to S5 in
such conditions since the platform would no longer be in a resuming
state after reset.
Change-Id: I01392bfda90c9274cd52c1004555d250b1d539b7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15340
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Call basic FSP reset handling in FspNotify stage. Handling of reset requests
for other stages need to be implemented as well.
BUG=chrome-os-partner:54149
BRANCH=none
TEST=with FSP that returns reset codes, do cold boot, check
that reboot sequence occurs properly.
Change-Id: I55542aa37e60edb17ca24ac358b61df72679b83e
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15280
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Global reset enable bit is not cleared on reset. Therefore, clear
the bit early. Lock down 0xcf9 so that payload/OS can't issue
global reset.
BUG=chrome-os-partner:54149
BRANCH=none
TEST=none
Change-Id: I3ddf6dd82429b725c818bcd96e163d2ca0acd308
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15199
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Apollolake defines Global Reset where Host, TXE and PMC are reset.
During boot we may need to trigger a global reset as part of platform
initialization (or for error handling). Add functions to trigger
global reset, enable/disable it and lock global reset bit.
BUG=chrome-os-partner:54149
BRANCH=none
TEST=none
Change-Id: I84296cd1560a0740f33ef6b488f15f99d397998d
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15198
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Looks like we need to do real cold reset in some FSP flows, so
reverting this.
This reverts commit 6f762171de.
Change-Id: Ie948d264c4e2572dab26fdb9462905247a168177
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15331
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
get_bios_size returns the value of bios_size. Use this function to
calculate bios_size for caching in bootblock.
BUG=chrome-os-partner:54563
Change-Id: I2e592b1c52138bd4623ad2acd05c744224a8e50b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15292
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Instead of hard-coding the BIOS region start and end addresses, read
BIOS_BFPREG to determine the base and limit for the mapped BIOS
region.
BUG=chrome-os-partner:54563
Change-Id: Iddd3d4cc945f09e8f147e293bb9144471a6a220d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15269
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This makes it clearer that the read/write operations are being performed
on the host controllers registers.
Change-Id: Id63d778a4a03c461d97e535c34b85ada3ae469de
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15281
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
