- create temp files and move them afterwards
- remove dummy option -b
- fix usage
- drop implicit creation of .c file if no --option is specified.
Now let's see if this fixes the issue. :-) We don't want to take 24s
instead of 6s to build an image reliably (Yes, yes, I know Tiano takes
over 20 minutes)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3783 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Jason Wang<Qingpei.wang@amd.com>
Reviewed-by: Joe, Bao <Zheng.Bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3782 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
unsupported functions, giving the user the impression that the
unsupported functions are tested.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3780 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This has been tested by Uwe Hermann on an RS690/SB600 board.
Signed-off-by: Jason Wang <Qingpei.Wang@amd.com>
Reviewed-by: Joe Bao <zheng.bao@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3779 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
With this patch it's possible to
- determine the according source code line for each asm statement
(objdump -dS)
- determine the source code file for each asm statement
(objdump -ddl)
This isn't exactly trivial because cache_as_ram_auto.c gets compiled to
assembly and converted by a perl script afterwards.
This patch solves the problem
- by extending cache_as_ram_auto.inc with debug information and line
numbers
- by correcting the perl calls (".text" --> "\.text")
- by creating a disassembly with source code and line numbers.
(ctr0.disasm and
coreboot.disasm)
There's one minor downside to the patch: A complete abuild run takes up
around 1.6G instead of about 700MB now. But I'm sure this is quite
reasonable for the benefits.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Please commit while this is being worked out.
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
running twice at the same time, overwriting its output files. This caused
a depending rule to produce an object file with no symbols in it.
This should silence up the regularly happening build failure messages on
the mailing list since we moved to the newer, much faster server.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3777 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This is the first chip which uses the infrastructure for alternative
erase commands, namely spi_chip_erase_60_c7().
Signed-off-by: Jason Wang <Qingpei.Wang@amd.com>
Reviewed-by: Joe Bao <zheng.bao@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3776 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- probe_spi_rdid with opcode 0x9f, usually 3 bytes ID
- probe_spi_res with opcode 0xab, usually 1 byte ID
We are missing the following probe function:
- probe_spi_rems with opcode 0x90, usually 2 bytes ID
RDID provides best specifity (manufacturer, device class and device) and
RES is supported by quite a few old chips. However, RES only returns one
byte and there are multiple flash chips with different sizes on the
market and all of them have the same RES ID.
REMS is from the same age as RES, but it provides a manufacturer and a
device ID. It is therefore on par with the probing for parallel flash
chips and specific enough.
The order in which chips should be detected is as follows:
1. RDID
2. REMS
3. RES
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3775 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
which support all commands, but may not exist.
For controllers which support only a subset of commands, it will fail in
unexpected ways. Even if a command is supported by the controller, it
may be unavailable if the controller is locked down.
The new logic checks if RDID could be issued and its return values made
sense (not 0xff 0xff 0xff). In that case, RES probing is not performed.
Otherwise, we try RES.
There is one drawback: If RDID returned unexpected values, we don't
issue a RES probe. However, in that case we should try to match RDID
anyway.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: FENG yu ning <fengyuning1984@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3774 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
memory controller.
Also, drop some unused '#if 0' code.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3773 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
After running make clean, most of build/ directory gets deleted.
It is (re)created in the "prepare" make target, but that was libpayload.a
dependency after the $OBJS, while OBJS building already needs to dump its
created object files there.
Simply rearrange the make target dependencies to get at least "make clean;make" working.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Jordan Crouse <jordan@cosmicpenguin.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3771 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
And some more notes in TODO.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3770 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
File util/flashrom/flash.h already had correct ID for that part.
Signed-off-by: Tero O Peippola <xeropp@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3769 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Rename the generated config file to libpayload-config.h to differenciate
it from other config.h files. Move the default location of the file to
$(src)/include so that LIBPAYLOAD_PREFIX= users can access the file
without staging it.
Signed-off-by: Jordan Crouse <jordan@cosmicpenguin.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3768 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
msrtool can decode MSRs and print the value of every field in human
readable form. It can also be used to save a set of MSRs to a file,
and at a later time compare the saved values with current values in
hardware.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3766 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
as well as most (all?) combinations thereof.
Drop some unused code, the unused row_offset variable, and obsolete comments.
Also, fix a typo (thanks to Stefan Reinauer for noticing).
This is tested on the MSI MS-6178 with a number of different DIMM
combinations and so far all of them worked fine.
Signed-off-by: Elia Yehuda <z4ziggy@gmail.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3765 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Intel 810 chipset (and all boards using it). This isn't required for this
chipset as there's only one memory controller.
This also helps a lot with romcc register usage, you should see the dreaded
"too few registers" less often.
Build-tested with all three boards using the Intel 810 chipset.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3764 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
don't have one (by fixing it for amd/serengeti_cheetah and copying the
same file to all other broken targets)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3763 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This is a school book example of why trivial indent patches just suck
big time.
This error was introduced by a trivial self-acked indent patch and was
never detected (because of a missing Config-abuild.lb)
So, indenting the code for no reason can make it a lot worse (read:
break it) instead of improving it.
I ask everyone to keep this in mind when going on indent-frenzy again.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3762 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
the Lippert Cool SpaceRunner LX which is already in svn).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3761 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
values for different DIMM configurations. This should be converted to a
table or code later on and actually be used for BUFF_SC.
Many thanks to Elia Yehuda <z4ziggy@gmail.com> for testing and collecting
the table entries.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3759 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
SPI opcodes should be placed in which location. Move to a less
optimistic implementation and actually use the generic SPI read
functions. They're useful for abstracting exactly this stuff and that
makes them the preferred choice.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3758 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
does not have a mechanism to signal command failure, the SPI host may be
unable to send a given command over the wire due to security or hardware
limitations. The current code ignores these mechanisms completely and
simply assumes almost every command succeeds. Complain if SPI command
execution fails.
Since locked down Intel chipsets (like the one we had problems with
earlier) only allow a small subset of commands, find the common subset
of commands between the chipset and the ROM in the chip erase case. That
is accomplished by the new spi_chip_erase_60_c7() which can be used for
chips supporting both 0x60 and 0xc7 chip erase commands.
Both parts of the patch address problems seen in the real world. The
increased verbosity for the error case will help us diagnose and address
problems better.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Otherwise: Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3757 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
AT25DF021
AT25DF041A
AT25DF081
AT25DF161
AT25DF321A
AT25DF641
AT25F512B
AT25FS010
AT25FS040
AT26DF041
AT26DF081A
AT26DF161
AT26DF161A
AT26DF321
AT26F004
I double-checked the data sheets and am confident this will work.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3756 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Tested fully on a ThinCan DBE61A
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3755 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The AT45 series SPI chips are DataFlash EEPROMs which means they have
odd (non-power-of-two) sector sizes, but some of the DataFlash chips can
be configured or ordered with power-of-two sector sizes.
Add probe support for the following Atmel SPI chips:
AT25DF021
AT25DF041A
AT25DF081
AT25DF161
AT25DF321A
AT25DF641
AT25F512B
AT25FS010
AT25FS040
AT26DF041
AT26DF081A
AT26DF161
AT26DF161A
AT26DF321
AT26F004
AT45CS1282
AT45DB011D
AT45DB021D
AT45DB041D
AT45DB081D
AT45DB161D
AT45DB321C
AT45DB321D
AT45DB642D
Add an explanation why the following chips can't be probed:
AT45BR3214B
AT45D011
AT45D021A
AT45D041A
AT45D081A
AT45D161
AT45DB011
AT45DB011B
AT45DB021A
AT45DB021B
AT45DB041A
AT45DB081A
AT45DB161
AT45DB161B
AT45DB321
AT45DB321B
AT45DB642
Add the ID, but no probing function for this chip:
AT25F512A
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Tested-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Tested-by: Andriy Gapon <avg@icyb.net.ua>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3754 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also, use the more generic and buildrom-friendly '../payload.elf' as
the default payload location.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3753 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marcj303@yahoo.com>
Acked-by: Chris Lingard <chris@stockwith.co.uk>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3751 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
IT8780F, and Fintek F71863FG.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3750 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Robert Millan <rmh@aybabtu.com>
Acked-by: Jordan Crouse <jordan@cosmicpneguin.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3745 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Rename the "coreboot" menu "firmware", and add a module to parse
the multiboot table. For now, just parse memory, but it can be
expanded as needed.
Signed-off-by: Jordan Crouse <jordan@cosmicpenguin.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3744 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Add a new infrastructure for returning system information to payloads.
First up - a pointer to the multiboot table.
Signed-off-by: Jordan Crouse <jordan@cosmicpenguin.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3743 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
enable may do printk()s which result in a 2 minute delay on some boards.
Fix this on all boards which currently do smbus_enable() before enabling
the serial console.
Thanks to Elia Yehuda <z4ziggy@gmail.com> for tracking this bug down.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3742 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also, add missing C1DRA2 #define (as per public datasheet).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3738 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Per report from Mario Rogen. Thanks!
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3736 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also, fix BIOS_CNTL, which is 0xdc on ICH7.
Build-tested with kontron/986lcd-m.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3733 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Stefan Reinauer