Commit Graph

41469 Commits

Author SHA1 Message Date
Frans Hendriks 53fe0a2529 mb/facebook/fbg1701/vboot-rw.fmd: Expand RO_SECTION
The romstage does not fit in RO_SECTION.

Increase the CBFS size in RO_SECTION.

BUG = N/A
TEST = Boot Facebook FBG1701 with VBOOT enabled.

Change-Id: I2f1020acb3ec99d4cddbaa05b0998fe32b470d3e
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-04-06 07:00:49 +00:00
Jakub Czapiga 084ad93663 include/rules.h: Add ENV_TEST definition
Some functions/macros like assert() require redefinition for testing
purposes. ENV_TEST is introduced to make it possible without using
bypass hacks.
This patch also adds a global __TEST__ define to TEST_CFLAGS for
all test targets in order to enable ENV_TEST.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ib8f2932902a73a7dbe181adc82cc18437abb48e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-04-06 06:58:05 +00:00
Jakub Czapiga f5c0021e05 tests: Add lib/uuid-test test case
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I7f8498ad3d9d0d68b34aa0b48daca60545ec3f4e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-04-06 06:56:47 +00:00
Michael Niewöhner 08dc4cf439 mb/ocp/tiogapass: use IPMI driver functionality for "POST complete"
Replace the mainboard-specific code for "POST complete" signalling with
devicetree entries for using the newly introduced IPMI driver
functionality.

Test: Boot the machine via the BMC web interface and check that sensors
get read correctly by the IPMI firmware when the payload starts.

Change-Id: I7503dec4e72810db8dfe74f72638b466a3d66748
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48671
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06 06:56:11 +00:00
Michael Niewöhner 61469c7a35 mb/ocp/tiogapass: correct "POST complete" pad initial value
On OCP Tioga Pass the pad GPP_B20 is used as output for signalling "POST
complete" to the BMC. According to the schematics and the code in
`ramstage.c`, the signal is active-low. There is an external pull-up
resistor.

To make the signalling work as it should, set the initial output value
to `high`.

Change-Id: I82fbda1caba9163ba3b2e38f494a0cefa27e657f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48670
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06 06:56:01 +00:00
Frans Hendriks 71491a6176 drivers/tpm/Kconfig: TPM_INIT for measured boot only
TPM_INIT depends on VBOOT but should also depend on
VENDORCODE_ELTAN_xBOOT.

Add dependency. TPM_INIT will be enable for measured boot only.

BUG = NA
TEST = Boot Facebook FB1701 with possible combinaties of VBOOT, measured
boot and eltan security.

Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Change-Id: I03f8457731c73c653bd82b1042bda3fc2d797feb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2021-04-06 06:53:54 +00:00
Wim Vervoorn e48bd3adb4 include/cbfsglue.h: Use BIOS_INFO for LOG macro
The ERROR() and LOG() macros both used BIOS_ERR as the error level.
The messages generated by the LOG() macro are informational items.
Change to BIOS_INFO to reflect that.

BUG=N/A
TEST=tested on facebook monolith

Change-Id: I3827a7d65a9d70045a36fb8db4b2c129e1045122
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-04-06 06:53:17 +00:00
Aamir Bohra c63a9fb757 mb/intel/shadowmountain: Add Cr50 support
This patch includes changes to add Cr50 support over GSPI0.

BUG=b:175579964
TEST=Verify TPM init is done and boots to kernel

Change-Id: I33f7427d1675190f65acf14679be93546e6db69a
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51086
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06 06:53:10 +00:00
Nico Huber 56d51b69ca util/kconfig_lint: Drop exception for paths without quotes
The tree is clean at the moment.

Change-Id: I1be3b6c2f3b54b5c10ad3d5c6f0a6fd7e490c6bc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52066
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06 06:51:40 +00:00
Nico Huber c48784069f mb/msi/h81m-p33: Put MAINBOARD_DIR in double quotes
Change-Id: I73160985c025cb0945a4ac16c8c3ebb988d3858f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52065
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06 06:51:29 +00:00
Tim Wawrzynczak 3b7b06dfbb mb/google/brya: Move early GPIO config earlier
The recent refactor of console UART GPIOs to mainboard's bootblock
caused brya boards to lose the first ~5 lines of the logs from
bootblock. Rename bootblock_mainboard_init to
bootblock_mainboard_early_init so that the UART pads will be ready
by the time the console is initialized.

BUG=b:184319828
TEST=First lines from report_platform.c are now seen in UART output

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I4a4fadcc091bf9b1c9894f9afaf42baff63c73a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-04-06 06:50:48 +00:00
Tim Wawrzynczak c556dffe98 lib: Add obvious definition for `calloc`
The calloc() function is useful in addition to malloc and friends, so
add the obvious definition.

Change-Id: I57a568e323344a97b35014b7b8bec16adc2fd720
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51949
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06 06:50:38 +00:00
Angel Pons 8aedb34501 mb/prodrive/hermes: Properly pack EEPROM structures
To pack a struct, the `__packed` attribute must come after the `struct`
keyword. Moreover, unions cannot be packed (structs inside unions can,
though). Correct uses of `__packed` so that EEPROM structs get packed.

Change-Id: I39d2c9ebc370605d5623b134189aa95a074ec7c3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: <wouter.eckhardt@prodrive-technologies.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-06 06:49:59 +00:00
Piotr Szymaniak 5b5b8afdf1 Docs/mb/lenovo/t420: List working, tested and non-working features
Signed-off-by: Piotr Szymaniak <szarpaj@grubelek.pl>
Change-Id: I6fb4a8da44125b4280d37d0cf7c372f8024fb2d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-06 06:47:29 +00:00
Piotr Szymaniak 49236d4430 mb/lenovo/t420: Copy HDA verbs from vendor firmware
Background story (I think that's what great in opensource -
ppl leave there part of their lives):  ;-)
While trying to fix audio jack not working with coreboot and
Windows 10 with some help from hell__ and nico_h on IRC nico_h
discovered that t420 and t430 hda_verb.c are the same:
<nico_h> oddly, in coreboot source T420 and T430 have the same
  numbers for very different codecs... I suspect copy-pasta
Difference between /sys/class/sound/cardX/hwCXDY/init_pin_config
in vendor BIOS helped with the updated config. Connecting audio
jack now works flawless both in Linux and Windows.

Audio-related keyboard buttons: volup, voldown, mute works fine
both in Linux (Debian-based) and Windows 10. mutemic button works
(tested ie. with xev) but both in Linux and Windows 10 wont light
up or makes any effect.

+-----------------------------------+
|   init_pin_config dump from:      |
+----= VENDOR =---+---= coreboot =--+
| 0x19 0x04211040 | 0x19 0x04211040 |
| 0x1a 0x61a19050 | 0x1a 0x61a19050 |
| 0x1b 0x04a11060 | 0x1b 0x04a11060 |
| 0x1c 0x6121401f | 0x1c 0x6121401f |
| 0x1d 0x40f001f0 | 0x1d 0x40f001f0 |
| 0x1e 0x40f001f0 | 0x1e 0x40f001f0 |
| 0x1f 0x90170110 | 0x1f 0x90170110 |
| 0x20 0x40f001f0 | 0x20 0x40f001f0 |
| 0x22 0x40f001f0 | 0x22 0x40f001f0 |
| 0x23 0x90a60170 | 0x23 0x90a60170 |
+-----------------+-----------------+

Tested-by: Piotr Szymaniak

Signed-off-by: Piotr Szymaniak <szarpaj@grubelek.pl>
Change-Id: Ie5eba84e5ea590b7db00e189cd68e714bee7e410
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51612
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06 06:47:14 +00:00
Angel Pons 736a1028fb drivers/intel/fsp1_1: Drop dead MMA code
The only FSP 1.1 platform with MMA support is Skylake. As it now uses
Kaby Lake FSP 2.0, this code is no longer useful. Drop it.

Change-Id: I819c3152bdea0fdad629793d96136ef134429fbd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-06 06:46:41 +00:00
Kevin Chiu f0fd3e2269 mb/google/zork: update DRAM table for morphius
Add Micron DDR4 memory part MT40A1G16RC-062E-B 16Gb
index was generated by gen_part_id

BUG=b:184024142
BRANCH=zork
TEST=emerge-zork coreboot

Change-Id: I890a2da38c8cd1963e9ee7c5df9410b2b2538e9f
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-04-06 06:46:27 +00:00
Kevin Chiu e1da21f687 util: Add DDR4 generic SPD for Micron MT40A1G16RC-062E-B 16Gb
Add SPD support for Micron DDR4 memory part MT40A1G16RC-062E-B 16Gb

BUG=b:184024142
TEST=none

Change-Id: I438310fb74d96953bc83374df3109e4c56192a5f
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-04-06 06:46:18 +00:00
Frank Wu e440c6b238 mb/google/zork/var/vilboz: Update WiFi SAR for Vilboz/Vilboz360 LTE
Loading wifi_sar-vilboz-2.hex for vilboz LTE sku.
Loading wifi_sar-vilboz-3.hex for vilboz360 LTE sku.

BUG=b:183902165, b:176211194, b:183913210
BRANCH=firmware-zork-13434.B
TEST=Build coreboot and load the wifi sar table by fw_config

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I37a40456970e3f1dc8b2eed26aa23e3d75748222
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-04-06 03:24:13 +00:00
Julius Werner 8205ce6b34 fsp2_0: Replace fspld->get_destination() callback with CBFS allocator
The Intel FSP 2.0 driver contains a custom construct that basically
serves the same purpose as the new CBFS allocator concept: a callback
function to customize placement of a loaded CBFS file whose size is
initially unknown. This patch removes the existing implementation and
replaces it with a CBFS allocator.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I0b7b446a0d2af87ec337fb80ad54f2d404e69668
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05 22:59:09 +00:00
Julius Werner 4676ec52c2 cbfs: Make `mdata` argument to cbfs_allocator_t const
Right before CB:49334 was submitted, I changed the signature of
cbfs_allocator_t function pointers to include another argument passing
in the already loaded CBFS metadata (to allow for the rare edge case of
allocators needing to read CBFS attributes). This interface is not meant
to be able to modify the passed-in metadata, so to clarify that and
prevent potential errors, we should declare the argument const.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I7e3756490b9ad7ded91268c61797cef36c4118ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05 22:59:02 +00:00
Felix Held d9c02cdc98 vc/amd/fsp/picasso/platform_descriptors: fix typos in enum element names
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5cad6a6a585320b33bfab7b3950888241f7c179c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-05 19:49:02 +00:00
Karthikeyan Ramasubramanian 72c1deaa74 mb/google/guybrush/var/guybrush: Add Codec and Speaker configration
Enable I2C2 in devicetree and fill ACPI information for Codec and
Speaker amplifiers. Pass correct IRQ GPIO for headset jack.

BUG=None
BRANCH=None
TEST=Ensure that the Codec and Speaker Amplifiers are detected in
i2cdetect.

Change-Id: I1ae52a8bbaa0181c906cd14a94de22e0250ed4c1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52046
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 19:47:24 +00:00
Karthikeyan Ramasubramanian d84ce40f7d mb/google/guybrush: Add Bluetooth configuration
Configure the BT disable GPIO to logic low in order to enable Bluetooth.
Add USB ACPI configuration for BT device.

BUG=b:182201890
TEST=Build and boot to OS.

Change-Id: I647c301e2db6d4a7c5c8cb31cbc47a44cba5e734
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05 19:47:15 +00:00
Raul E Rangel 92e66cc4e3 soc/amd/cezanne: Add soc/msr.h
This is a copy of picasso.

BUG=b:184151560
TEST=Compared with the cezanne PPR.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia4bc40daa971c126c2596837155312d411b91a06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-05 19:25:26 +00:00
Ivy Jian 7a347afa95 mb/google/guybrush: Enable camera power GPIO
Configure camera power GPIO to high

BUG=b:182207799
TEST=Build and boot to OS then checked camera device existence with lsusb

Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: Ie894167e3c4f8efdb3710599c6ff3a9fc975adb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-05 18:30:46 +00:00
Martin Roth 632419852a mb/google/guybrush: Update GPIO configuration
Initialize all eSPI signals including PCIE_RST0_L early for EC
communication.
- Set PCIE_RST0_L to a GPIO and set it high to release the bus.  This is
a temporary workaround until PCIE_RST_L comes up on its own.
- Make sure all GPIO muxes initialized early are re-initialized.

BUG=b:183340503
TEST=Boot Guybrush

Change-Id: I512cb8b435dc8412cd46189e741ad94e5a24699e
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51675
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 18:24:44 +00:00
Martin Roth d07f724f9c soc/amd/common: Add some ESPI register definitions
Use definitions instead of magic numbers
clean up some whitespace while I'm here.

BUG=b:183207262
TEST=Build

Change-Id: Ieae53b12e5303641fb3f180c47468aaa6906e9af
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-05 17:34:18 +00:00
Martin Roth fa9eb951d4 util/bincfg: Clean up Makefile
- Enable warnings
- Enable warnings as errors
- Remove debug flag -g
- Add targets for all, distclean, and help
- Add dependency of the bincfg file for output targets
- Add all phony targets to .PHONY

BUG=None
TEST=Build all targets

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ic0302f663cbc931325334d0cce93d3b0bf937cc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50654
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 17:21:04 +00:00
Eric Lai 7bbcdc2f20 mb/google/mancomb: Add ACPI support for Chrome EC
BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ibce15d2e4340515353a33c593d065df50a15286a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-05 16:41:14 +00:00
Eric Lai e93e693173 mb/google/mancomb: Enable eSPI VW SCI events
Mancomb does not have a dedicated SCI pin so it uses VW.

BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Id315ab448209d9c93494f7689361e45f8a6ed001
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-05 16:41:02 +00:00
Eric Lai 6b928356ca mb/google/mancomb: Enable Chrome EC SKUID and BOARDID
BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I70283c8d93b5cbabdaf5a8ab947d5f8444940dff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-05 16:40:48 +00:00
Eric Lai 1954c1f92e mb/google/mancomb: Add smihandler
BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I52411917d9e7e8f8d9ac5d1c9b426a58ba09f5ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-05 16:40:37 +00:00
Eric Lai 87e27e1d0e mb/google/mancomb: Enable Chrome EC
BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Id1617be67bfc5d2f142358ae8a70c3e575a94c6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-04-05 16:40:08 +00:00
Raul E Rangel b95f848766 soc/amd: Make espi_clear_decodes private
espi_setup already clears most of the controller registers. So this
change consolidates the clear logic into one spot.

This shouldn't result in a behavior change on Picasso. Picasso already
has the eSPI decodes clear on boot, so this change is a nop.

BUG=b:183524609
TEST=Boot guybrush to the OS

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic57689e50febd29796d8ac8d99c81e41fee5b41c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05 16:39:11 +00:00
Raul E Rangel 61ac1bc530 soc/amd: Make espi_configure_decodes private
This is only ever called after espi_setup.

55861 - AMD System Peripheral Bus Overview also says that io ranges
should be configured before enabling the BUS_MASTER bit.

BUG=b:183524609
TEST=Boot guybrush to OS

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I074e487d8768a578ee889a125b9948e3aa6c7269
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05 16:38:23 +00:00
Seunghwan Kim c988d0516c mb/google/dedede/var/sasuke: Update DPTF parameters
Remove TSR2, use DPTF parameters from internal thermal team.

BUG=b:183749595
BRANCH=dedede
TEST=emerge-dedede coreboot

Change-Id: I3182b96bf36c8d07299fe435a29e6b8c0b8a6927
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-04-05 15:37:42 +00:00
Seunghwan Kim 6ffaf5a691 mb/google/dedede/var/sasuke: Configure I2C times for touchpad/audio
Configure I2C rise/fall time in device tree to ensure I2C CLK runs
accurately at I2C_SPEED_FAST (< 400 kHz).

Measured I2C frequency just as below after tuning:
I2C0(touchpad): 385 kHz
I2C4(audio): 380 kHz

BUG=b:180335053
BRANCH=dedede
TEST=Build and check after tuning I2C clock is under 400kHz

Change-Id: Ic92ee0379456e80260a8026bc38ee41325dad6d2
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-05 15:32:09 +00:00
Raul E Rangel 66c52ffb2b soc/amd/common/espi: Clear DNCMD_COMPLETE on completion
Tidy up the interrupt status. This will leave SLAVE0_INT_STS = 0.

BUG=b:183524609
TEST=Boot guybrush to OS

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I950cfb81521e35758c120a482670cfdb924201d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52056
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 15:02:10 +00:00
Raul E Rangel b92383a8a5 soc/amd/common/espi: Reset eSPI registers to known state
This sets the eSPI registers to the reset values specified in the PPR.

On Cezanne, the PSP modifies these registers such that the eSPI
peripheral cannot send DEFER packets. This causes random bus errors.

These reset values are identical to what is currently used on Zork.

I didn't clear out ESPI_DECODE because it's currently being done by
cb:51749.

BUG=b:183524609
TEST=Boot guybrush to the OS

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic3a9860747aac78121358b4499d8a38052236c0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05 15:02:00 +00:00
Raul E Rangel 1d0e4930ba soc/amd/common/espi: Add missing eSPI register definitions
These are defined in the public Picasso PPR - 55570-B1 Rev 3.15.

BUG=b:183524609
TEST=Build guybrush

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7e601f767327e0a24a086146623af039388b2e7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52057
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 15:01:50 +00:00
Aaron Durbin a435c3e2ea mb/google/dedede: add lalala variant
The Lalala variant is a design that differs only
in replacing Cr50 with a discrete TPM part.

BUG=b:184151664

Change-Id: I2f7abb9637cd5a13ac896396781b19feb156c948
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
2021-04-05 14:31:15 +00:00
Aaron Durbin 7164ad74bf mb/google/dedede: add discrete TPM 2.0 configuration
There are forthcoming designs that will be utilizing
a discrete TPM 2.0 solution. Split the existing dedede
configuration options so future mainboard variants can
easily select the appropriate Kconfig option using the
newly introduced options:
- BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50
- BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2
The existing variants all select the former option,
BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 since all those
designs currently utilize Cr50.

BUG=b:184151664

Change-Id: I2bdb1ca4fd78cc0628256d49678ea042c55f6fba
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52030
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 14:31:08 +00:00
Furquan Shaikh f7f715dff3 mb/google/brya: Enable south XHCI ports 1 and 2
FSP v2081 has a bug where it uses the information about south XHCI
ports to enable TCSS XHCI ports. This change works around this bug by
enabling south XHCI ports 1 and 2 in brya baseboard devicetree. brya0
already enables south XHCI port 1 in overridetree.cb, however, it is
still enabled in baseboard/devicetree in case more variants are added
to brya before FSP is fixed.

BUG=b:184324979
TEST=Verified that TCSS XHCI ports 1 and 2 are now enabled.

Change-Id: I4b86a98b18234ba309ddf2f30b80d78472951637
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-05 14:15:31 +00:00
Angel Pons 5304ce108e nb/intel/sandybridge: Drop `pci_mmio_size`
There's no good reason to use values smaller than 2 GiB here. Well, it
increases available DRAM in 32-bit space. However, as this is a 64-bit
platform, it's highly unlikely that 32-bit limitations would cause any
issues anymore. It's more likely to have the allocator give up because
memory-mapped resources in 32-bit space don't fit within the specified
MMIO size, which can easily occur when using a discrete graphics card.

Change-Id: If585b6044f58b1e5397457f3bfa906aafc7f9297
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52072
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 13:16:43 +00:00
Angel Pons f2e8660fa2 sandybridge boards: Drop default `pci_mmio_size`
2 GiB is the default already.

Change-Id: I294460949659c97d4e19ad4e9d14f8c3566cca3f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52071
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 13:16:36 +00:00
Angel Pons e24f97c081 nb/intel/ironlake: Drop `pci_mmio_size`
There's no good reason to use values smaller than 2 GiB here. Well, it
increases available DRAM in 32-bit space. However, as this is a 64-bit
platform, it's highly unlikely that 32-bit limitations would cause any
issues anymore. It's more likely to have the allocator give up because
memory-mapped resources in 32-bit space don't fit within the specified
MMIO size, which can easily occur when using a discrete graphics card.

Change-Id: I6cdce5f56bc94cca7065ee3e38af60d1de66e45c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52070
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 13:16:22 +00:00
Angel Pons 83e319d6f5 device/dram/ddr3: Drop unused MRS helpers
These aren't used anywhere anymore.

Change-Id: I4cf2fc0d07a772886e90fba4f66591a7b0a40e6c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-05 13:03:58 +00:00
Angel Pons ae5e636b96 nb/intel/sandybridge: Rename `pdwm_mode` enum
The `pdwm` part was supposed to be an abbreviation of `power down`, but
it is neither self-explanatory nor properly-spelled. Rename the enum.

Change-Id: I7b83c71d4534b62e18ced04eebe6a65089e1d874
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-05 13:03:24 +00:00
Angel Pons 623d75e828 spd.h: Remove unused definitions
These definitions are unused and not particularly useful. Drop them.

Change-Id: I40a824888701870b6713c1a16ab671c19b3770ae
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51900
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 13:02:59 +00:00