Commit Graph

12440 Commits

Author SHA1 Message Date
Furquan Shaikh ba87e6cc94 libpayload: Add support for memory barriers
Add support for memory barriers in arch {arm,arm64,x86}. This is required to
force strict CPU ordering. Definitions are based on FREEBSD atomic.h
definitions.

BUG=chrome-os-partner:31533
BRANCH=None
TEST=Memory barriers tested with ehci driver on arm64

Change-Id: I50060b0f33a6bd6cb95e829df079df379b2ff2a5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 937d66cdab92a8521ede8307f5af8f5c20d3e552
Original-Change-Id: Ie51e3452f7a254b24111000da5dbe8714ac22223
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/213916
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8731
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-19 23:24:16 +01:00
Aaron Durbin c88cca1c38 libpayload: add xmemalign()
Similarly to xzalloc() and xmalloc() provide an xmemalign() function
to do the approriate assertions on allocation failure.

BUG=None
BRANCH=None
TEST=Built and booted using xmemalign().

Change-Id: I59579d9ee973af3bb34037b7df5b1024b60e348d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3001822656024dbfc34d6b849a0245274b8c0f46
Original-Change-Id: Ie307d4c9c1882bba25745afe38455f2682303e37
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/242455
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/8728
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-19 23:23:41 +01:00
Patrick Georgi e5be1dc336 libpayload: Add OpenBSD queue implementation
Add OpenBSD's header-only implementation of some
basic data structures, imported from
src/sys/sys/queue.h, revision 1.38
(all whitespace errors kept verbatim)

Unlike home-grown solutions they likely handle
all corner cases correctly from the start and
unlike Linux's solution it's properly documented
(see OpenBSD's LIST_INIT(3)) and also BSD-l.

BRANCH=none
BUG=none
TEST=none

Change-Id: I89ae4df0c73662c355537283e7559af03a8b99a0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6f89e0316e6d68158c689bed4b1bdfe168c1449a
Original-Change-Id: Ie08a567851a2f07cbd2ac80ba31d8bca9844937d
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/240190
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/8727
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-19 23:23:36 +01:00
Nico Huber b0f8326ac2 uio_usbdebug: User-space-i/o framework for usbdebug
uio_usbdebug enables you to debug coreboot's usbdebug driver inside a
running operating system (only Linux at this time). This comes very
handy if you're hacking the usbdebug driver and don't have any other
debug output from coreboot itself.

Currently, only Intel chipsets are supported.

Change-Id: Iaf0bcd4b4c01ae0b099d1206d553344054a62f31
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/4695
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-19 19:19:42 +01:00
Timothy Pearson 86f4ca5b4b cpu/amd/model_10xxx: Add support for early cbmem
mainboards/amd/fam10: Initialize cbmem area after raminit

When GFXUMA is enabled, CBMEM is placed at TOM - UMASIZE
When GFXUMA is disabled, CBMEM is placed at TOM
This matches the behaviour present before conversion to early
CBMEM.

The CBMEM location code implicitly assumes TOM does not change
between romstage and ramstage.  TOM is set by romstage raminit,
and is never changed by romstage or ramstage afterward.  As
the CBMEM location is positioned at a specific offset from TOM
that is known to both romstage and ramstage early CBMEM is safe
on Fam10h systems.

TEST: Booted ASUS KFSN4-DRE and verified both cbmem timestamp
tables from romstage and cbmem log tables from ramstage.

Change-Id: Idf9e0245fe91185696ff664b06182c26b376c196
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8489
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-03-19 08:28:43 +01:00
Timothy Pearson e24f7d37ce cpu/amd/model_10xxx: Fix UMA memory sizes
Fix up commit 4916880 (cpu/amd/model_10xxx: Move GFXUMA size
calculation to separate function) unintentionally changing
behavior when converting the switch statement to an if-else
statement.

Change-Id: I8d126aaec1b324face6407a2b451e603e61db0e5
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8748
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-19 08:27:09 +01:00
Kyösti Mälkki 4da487eae8 CBMEM: Add LATE_CBMEM_INIT guards
Our target is to get rid of backup_top_of_ram() and get_top_of_ram()
entirely so only declare these with LATE_CBMEM_INIT=y.

Change-Id: I54f549fe774996f4d803f9ec527e0fac46f6576f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8749
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-03-19 06:17:07 +01:00
Timothy Pearson e9424c593a northbridge/amd/amdfam10: Unify CBMEM location across UMA and non-UMA
The CBMEM memory segment is always placed at TOM - UMASIZE when GFXUMA
is enabled, however when GFXUMA is disabled an attempt was made to locate
the CBMEM memory segment above the I/O hole in certain rare cases.

Removing this special case does not impact functionality, and paves
the way for early CBMEM support.

Change-Id: I98d29ab9d601a4e20f58e2cd0a66abb13b494e74
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8664
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: Aaron Durbin <adurbin@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-03-19 05:00:25 +01:00
Kyösti Mälkki 1e60839be0 southbridge/amd/rs780: Remove requirement for CF8/CFC config access
The AMD RS780 early initialization code originally used the
CF8/CFC I/O method for PCI configuration space access. After
the default configuration access method was changed to MMIO
(http://review.coreboot.org/#q,aad07472), booting would hang
at "PCI: pci_scan_bus for bus 01". Fix the problem by changing
function rs780_nb_gfx_dev_table() so that it no longer borrows
the BAR3 address needed for PCIe MMIO config usage.

Change-Id: I8816b94c848e1b50f8c880e5867a96ca2a33a8a7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8394
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-19 04:00:08 +01:00
Patrick Georgi 8135dba368 crossgcc: jump to crossgcc path before building the toolchain
We use paths relative to that in the buildgcc script.

Change-Id: I2b79c3d2c75088af7e8e362d18a38274352eb965
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/8713
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-18 21:50:33 +01:00
Aaron Durbin 9ef9d85976 bootstate: use structure pointers for scheduling callbacks
The GCC 4.9.2 update showed that the boot_state_init_entry
structures were being padded and assumed to be aligned in to an
increased size. The bootstate scheduler for static entries,
boot_state_schedule_static_entries(), was then calculating the
wrong values within the array. To fix this just use a pointer to
the boot_state_init_entry structure that needs to be scheduled.

In addition to the previous issue noted above, the .bs_init
section was sitting in the read only portion of the image while
the fields within it need to be writable. Also, the
boot_state_schedule_static_entries() was using symbol comparison
to terminate a loop which in C can lead the compiler to always
evaluate the loop at least once since the language spec indicates
no 2 symbols can be the same value.

Change-Id: I6dc5331c2979d508dde3cd5c3332903d40d8048b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8699
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-18 16:41:43 +01:00
Marc Jones b335c3de42 chromeec: Move SERIQ mode to LPC option
SERIRQ_CONTINUOUS_MODE is specific feature of LPC busses.
This fixes a KCONFIG unmet dependency warning on ARM mainboards with
chromeec.

Change-Id: Iae61986219585dcb1124cf3b24fa32a8596d56c8
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8665
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-18 07:08:59 +01:00
Stefan Reinauer 425b61e102 arch/x86/Kconfig: Add license header
Add license header with copyright of the original authors.

Change-Id: I8c55bb38a2a2a387ad2461e11d402c7392fa2497
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8691
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-17 18:11:38 +01:00
Dave Frodin f364fc7682 southbridge/amd/pi: Enable early I/O decode to LPC
The decode of UART addresses down to the LPC bus needs
to occur early to allow romstage console messages to
be seen. This enables the decode of most of the I/O
ports typically seen in a system.

Change-Id: I6636946af4ad5320a5a46c2920b4f06345b5f806
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8661
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-17 17:49:58 +01:00
David Hendricks 68ec2fce2b ipq806x: Break apart large transfers in spi_xfer()
The current spi_xfer() function sets the count in hardware and then
loops while waiting for the requested number of bytes to be sent or
received. However, the number of bytes to be transferred may exceed
the maximum count that can be programmed into the controller.

This patch re-factors spi_xfer() to split the low-level FIFO handling
portions for transmit/receive into their own functions to be called
by loops in spi_xfer() which will break large transfers into smaller
ones.

BUG=chrome-os-partner:30904
BRANCH=storm
TEST=built and booted with a >64KB payload on Storm

Original-Change-Id: I70743487996cf08cfc602449f2181a7fcd99bfa4
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/209838
Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
Original-Tested-by: Trevor Bourget <tbourget@codeaurora.org>
(cherry picked from commit 5ec28de11f12c2438356f45ce978a17fbb603bf7)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I0033e0dd96006cfd30a7a4f5e5a052f677e05108
Reviewed-on: http://review.coreboot.org/8676
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17 16:54:26 +01:00
Furquan Shaikh c4f08f7f9c cbfstool: Add relocation codes for arm mode
Add relocation codes required for arm mode. These are required by armv4.

BUG=chrome-os-partner:30784
BRANCH=None
TEST=Compiles successfully for rush

Original-Change-Id: Ie7c5b3e07689c85091036a619a65f9fea1918b6b
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209973
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit dc5f411f95e02a02b4a4ef4652303ce62aa220c2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ie62ed730080299e474c256371ab88f605b54c10f
Reviewed-on: http://review.coreboot.org/8675
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17 16:53:50 +01:00
Furquan Shaikh c800129009 t132: Add TTB_BUFFER to resource reserved
TTB_BUFFER holds the MMU tables. Thus, this memory needs to be preserved while
performing a wipe in depthcharge. Hence, marking it as reserved

BUG=None
BRANCH=None
TEST=Compiles successfully and boots upto depthcharge. Error wiping memory
tables is fixed.

Original-Change-Id: Idd5cd0235d50f7b9617df2cead3bf71012e3b630
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/210000
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 670e21ed11f985ca6cfef4f051c71b3c06f9c6ff)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ifcbdd4fdaad0bd4bfe384698b13cc5013317345e
Reviewed-on: http://review.coreboot.org/8681
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17 16:41:00 +01:00
Furquan Shaikh f4731afb9d rush: Update rush Kconfig file
Update rush Kconfig file to include TPM and RAMSTAGE_INDEX options

BUG=None
BRANCH=None
TEST=Compiles successfully. TPM works. Ramstage boots successfully.

Original-Change-Id: Ie55260c710ffcb6a2e04c8658ca6dd3cdec6b6db
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209978
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 0088f5aade8533c6ed235de25934d47cd0743a67)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I5c4a54b74546de73eee7e7bae072cc712ce1838f
Reviewed-on: http://review.coreboot.org/8680
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17 16:40:49 +01:00
Furquan Shaikh e6ede46c33 rush: Add ec_dummy file to enable vboot compilation
BUG=chrome-os-partner:30784
BRANCH=None
TEST=Compiles successfully for rush

Original-Change-Id: Ic11bef85e5c7635000582f87727cd9a33b0b36e3
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209975
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 3d3f0494d8758ef5040384f63d023c042686bd2c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ie15781d10a366b68f0db97378ccb348a4f074995
Reviewed-on: http://review.coreboot.org/8679
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17 16:40:34 +01:00
Furquan Shaikh 64352a7c1b rush: Pull in chromeos.c from nyan into rush
Hardcoded values are set for developer,recovery mode. Change as per requirements

BUG=chrome-os-partner:30784
BRANCH=None
TEST=Compiles succesfully for rush

Original-Change-Id: Ied506a9d1c4e0ba8ee06d57c6ca8c726220998b5
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209974
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 2e6934d47c5b4bb98e60486202b230bae79d927b)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I36e384b0d331fdd9e3f47954decfddaf4f31aed3
Reviewed-on: http://review.coreboot.org/8678
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17 16:40:21 +01:00
Jimmy Zhang aa228d08e9 Tegra132: Configure CPU clock
Since CCLK_BURST_POLICY and SUPER_CCLK_DIVIDER are not accesible
from AVP, the first place that can change CPU clock is after CPU
has been brought up, ie, ramstage in this case.

CPU initial clock source is set to PLLP by MTS.

BUG=None
TEST=Norrin64 and A44

Original-Change-Id: I525bb2fa2be0afba52837bc0178950541535fd22
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209698
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit ba77e26508bb4a50a08d07ad15632ff1ba501bfa)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Icf2458c491b4b3a553d3e01f88c6f25b25639e89
Reviewed-on: http://review.coreboot.org/8677
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17 16:39:22 +01:00
Furquan Shaikh 6ad6e3d84a t132: Add monotonic_timer.c to rmodules_arm
Update VBOOT_STUB_DEPS to include monotonic_timer.c

BUG=chrome-os-partner:30784
BRANCH=None
TEST=Compiles successfully for rush

Original-Change-Id: I3cc559fa21c444da1a7976e4952ea4941c2a1428
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209972
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 8096ae56c4df4013cfc798944b98dd1078c8b451)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I68c13617b96fd872d1eaa9278de6647eccb795c3
Reviewed-on: http://review.coreboot.org/8674
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17 16:38:38 +01:00
Furquan Shaikh a742ef1a48 rmodules: Make rmodules inclusion for vboot dependent on romstage_arch
Currently, the rmodules inclusion for vboot is dependent on ramstage_arch.
This change adds dependency on romstage_arch, since vboot is associated with
romstage. Inclusion based on ramstage_arch is left as is in case someone needs
it in ramstage.

BUG=chrome-os-partner:30784
BRANCH=None
TEST=Compiles successfully for link, rush and nyan

Original-Change-Id: Ib62415671c26a4a18c7133d98e8c683414def32b
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209568
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 00da67cc02c81d7a6160f7336b33bf53b00e1875)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I9df02134af4e396c7257a2db2e2c371cfd1a02bc
Reviewed-on: http://review.coreboot.org/8673
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17 16:38:23 +01:00
Furquan Shaikh fbff908a74 coreboot classes: Add dynamic classes to coreboot
Provide functionality to create dynamic classes based on program name and the
architecture for which the program needs to be compiled/linked. define_class
takes program_name and arch as its arguments and adds the program_name to
classes-y to create dynamic class and compiler toolset is created for the
specified arch. All the files for this program can then be added to
program_name-y += .. Ensure that define_class is called before any files are
added to the class. Check subdirs-y for order of directory inclusion.

One such example of dynamic class is rmodules. Multiple rmodules can be used
which need to be compiled for different architectures. With dynamic classes,
this is possible.

BUG=chrome-os-partner:30784
BRANCH=None
TEST=Compiles successfully for nyan, rush and link.

Original-Change-Id: I3e3aadbe723d432b9b3500c44bcff578c98f5643
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209379
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 242bb90d7476c2ee47d60c50ee18785edeb1a295)

Some of this cherry-pick had already been committed here:
commit 133096b6dc
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I9f5868d704c4b3251ca6f54afa634588108a788c
Reviewed-on: http://review.coreboot.org/8672
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17 16:38:10 +01:00
Deepa Dinamani 74aa7770f6 soc/ipq806x: Replace GPT with fine grained DGT timer.
Support 1MHz libpayload restriction on timer implementation
by using DGT (debug) timer instead of GPT (general purpose) timer.

BUG=chrome-os-partner:28880
TEST=manual
  verified DGT timer functions in coreboot and depthcharge.

Original-Change-Id: Iab322d7e863e3959c027e9ce876223a64eb7e257
Original-Signed-off-by: Deepa Dinamani <deepad@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/201574
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
(cherry picked from commit ddf11eee5ec2d86a62095e932dbec9313b8fb9e1)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Id73e805801fd8d135b607df9f4f8caf567ec5b83
Reviewed-on: http://review.coreboot.org/8596
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17 16:30:58 +01:00
Aaron Durbin f69a99dbf8 coreboot: x86: enable gc-sections
Garbage collected sections allow for trimming the size of the
binaries as well as allowing for not needing to config off
unused functions. To that end, on a rambi build the following
differences are observed:

$ diff -up \
	<(readelf -l coreboot-builds/google_rambi/cbfs/fallback/ramstage.elf) \
	<(readelf -l coreboot-builds/google_rambi_gc_sections/cbfs/fallback/ramstage.elf)
--- /dev/fd/63  2015-03-10 12:07:27.927985430 -0500
+++ /dev/fd/62  2015-03-10 12:07:27.927985430 -0500
@@ -6,9 +6,9 @@ There are 4 program headers, starting at
 Program Headers:
   Type           Offset   VirtAddr   PhysAddr   FileSiz MemSiz  Flg
Align
   LOAD           0x001000 0x00000000 0x00000000 0x00040 0x00040 RWE 0
-  LOAD           0x001040 0x00000040 0x00000040 0x34560 0x34560 RWE 0
-  LOAD           0x0355a0 0x000345a0 0x000345a0 0x02578 0x02578 RWE 0
-  LOAD           0x037b18 0x00036b18 0x00036b18 0x00000 0x0b560     0
+  LOAD           0x001040 0x00000040 0x00000040 0x2cbf8 0x2cbf8 RWE 0
+  LOAD           0x02dc38 0x0002cc38 0x0002cc38 0x02208 0x02208 RWE 0
+  LOAD           0x02fe40 0x0002ee40 0x0002ee40 0x00000 0x0a888     0

  Section to Segment mapping:
   Segment Sections...

$ diff -up \
	<(readelf -l coreboot-builds/google_rambi/cbfs/fallback/romstage.elf) \
	<(readelf -l coreboot-builds/google_rambi_gc_sections/cbfs/fallback/romstage.elf)
--- /dev/fd/63  2015-03-10 12:08:16.855985880 -0500
+++ /dev/fd/62  2015-03-10 12:08:16.851985880 -0500
@@ -5,8 +5,8 @@ There are 1 program headers, starting at

 Program Headers:
   Type           Offset   VirtAddr   PhysAddr   FileSiz MemSiz  Flg
Align
-  LOAD           0x000060 0xfff20000 0xfff20000 0x08b81 0x08b81 R E
   0x10
+  LOAD           0x000060 0xfff20000 0xfff20000 0x06300 0x06300 R E
0x10

  Section to Segment mapping:
   Segment Sections...
-   00     .rom .text
+   00     .rom

The following warnings needed to be applied to CFLAGS_common because for
some reason gcc was miraculously emitting the warnings with the
unrelated *-sections options:
  -Wno-unused-but-set-variable

Change-Id: I210784fdfc273ce4cb9927352cbd5a51be3c6929
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8635
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-17 14:35:31 +01:00
Kyösti Mälkki 5179419989 rockchip/rk3288: Fix whitespace
Change-Id: I6c3c1e871de33b4d0e968b254bbcf125cee9fddb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8704
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-17 06:59:25 +01:00
Stefan Reinauer 3d78ece7d0 haswell: Fix monotonic timer integration
In some previous attempt to enable monotonic timers on all platforms,
the LAPIC monotonic timer was selected for Haswell devices, despite
the fact that LAPIC timers are not used in coreboot on Haswell
(See haswell Kconfig) and there already was a monotonic timer
implementation enabled that just needed to be added for SMM as well.

Change-Id: I6beb2977864e507956636860ed463e1991cea1ed
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/8702
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-17 04:56:14 +01:00
Stefan Reinauer c3d15a7210 Intel common SPI: Fix compilation breakage from refactoring
When the Intel SPI drivers were refactored, compilation for Chrome OS
devices broke, because ELOG uses the SPI driver in SMM.

Change-Id: If2b2da5d526196ed742e17409b01a381417d0ce8
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/8701
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-17 04:55:52 +01:00
Stefan Reinauer 45a225b05d elog: Fix compilation with CONFIG_CHROMEOS enabled
On ChromeOS devices the ELOG section size and offset are
provided by the FMAP, rather than KConfig. Some upstream
refactoring broke compilation in that case.

Change-Id: I8b08daa327726218815855c7c2be45f44fcffeed
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/8700
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-17 04:54:46 +01:00
Timothy Pearson 4916880511 cpu/amd/model_10xxx: Move GFXUMA size calculation to separate function
This is required for early CBMEM support.

Change-Id: I31d9b6a04ef963a7d3e045d9c5201ae64604218a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8663
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-03-17 04:33:06 +01:00
Timothy Pearson 447240808c lib: Add Kconfig option to enable/disable auto fallback control
Under certain conditions, e.g. automated testing, it is useful
to have the payload (e.g. Linux) reset the reboot_bits CMOS
value.  This allows automated recovery in the case of coreboot
starting properly but the payload failing to start due to bad
configuration data provided by the coreboot image under test.

Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Change-Id: Ifc8f565f8292941d90b2e520cc9c5993b41e9cdd
Reviewed-on: http://review.coreboot.org/8698
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2015-03-17 04:22:23 +01:00
Stefan Reinauer 87200e2aa3 Makefile.inc: Use -Og when compiling with GDB support
From GCC's documentation:

Optimize debugging experience. -Og enables optimizations that do not interfere
with debugging. It should be the optimization level of choice for the standard
edit-compile-debug cycle, offering a reasonable level of optimization while
maintaining fast compilation and a good debugging experience.

Change-Id: I9a3dadbf8e894cb28e29d7b2f4e9add252e7bbb3
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/8689
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-17 01:08:20 +01:00
Stefan Reinauer 24f9cb91d0 crossgcc: Add x86_64 to list of supported architectures
You can build your new toolchain with:
  $ cd util/crossgcc/
  $ ./buildgcc -d /opt/cross -p x86_64-elf -j 16
or
  $ make crossgcc-x64

Change-Id: I8eb584166294578d2b33c63e94ed3aca9b5de4f4
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8668
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-17 01:07:27 +01:00
Dave Frodin 84c72dedab northbridge/amd/pi: Create common agesawrapper.c
This removes the mainboard agesawrapper.c file from binarypi
based boards and creates a common one.

Change-Id: I900dba914f1c401e4ac732eb93d94b98216e629a
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8671
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-16 21:46:17 +01:00
Dave Frodin 4b45dd3253 cpu/amd/pi: Add amd_initcpuio() and amd_initmmio()
This makes the change to the cpu/amd/pi/00730F01 that was
made for the cpu/amd/agesa based boards in:
    commit 48518f0d
    AGESA: Add amd_initcpuio() and amd_initmmio()
    These are not wrappers for AGESA as they do not enter vendorcode at all.
    We expect most of the added fixme.c file to be written without use of AMDLIB.h
    and parts relocated as northbridge enable_resources().

The equivalent change has already been made for cpu/amd/pi/00630F01.

Change-Id: I591b50ee807436f5a1dee14d2c88a77462024744
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8670
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-16 21:45:49 +01:00
Timothy Pearson 8e3da749ed mainboards/amd: Fix incorrect reboot_bits location
Change-Id: Iead07df714f4f1bbaae6b564431fb4edf7b18ac2
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8684
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-16 07:07:18 +01:00
Francis Rowe 71512b2cf6 northbridge/i945/gma: fix build error with native graphics init
Tested on an X60, Native graphics init still works perfectly.

Change-Id: I91be3baa658e0332028c512c5a4cb0aee07d540a
Signed-off-by: Francis Rowe <info@gluglug.org.uk>
Reviewed-on: http://review.coreboot.org/8696
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-03-16 06:46:48 +01:00
jinkun.hong ac490b8a6b coreboot: rk3288: Add a stub implementation of the rk3288 SOC
Most things still needs to be filled in, but this will allow us to build boards which use this SOC.

BUG=chrome-os-partner:29778
TEST=emerge-veyron coreboot

Original-Change-Id: If643d620c5fb8951faaf1ccde400a8e9ed7db3bc
Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205069
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 2f72473a8c2b3fe21d77b351338e6209035878fb)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I53fd0ced42f6ef191d7bf80d8b823bb880344239
Reviewed-on: http://review.coreboot.org/8653
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-16 04:52:46 +01:00
Alexander Couzens a74d569731 genbuild_h.sh: use the last git commit as timesource if available
Change-Id: I1472265adac9406a86da22839199ec6bbdaa0c69
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/8619
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-16 04:02:08 +01:00
Alexandru Gagniuc 83b05eb0a8 google/butterfly: Drop MRC.bin in favor of native raminit
I thought this wasn't going to work, and observing the timC detection
failure of early tests, I was getting somewhat discouraged; however,
this works. I've tried it with all possible permutations of the
following memory modules:
* 2 GiB single-rank DDR3-1600
* 4 GiB single-rank DDR3-1600
* 4 GiB dual-rank DDR3-1600

I did notice a limited number of memtest errors during one of the
runs, but they were in an address range that is otherwise marked as
reserved. I wrote that off as "maybe something was doing MMIO there
just when memtest was poking the address range". I was not able to
reproduce that error.

Change-Id: Ibd52e1d52fc8d900591d6a488f9a5b4d1e5e4fd3
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8477
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2015-03-15 05:28:29 +01:00
Timothy Pearson 21d898bad0 mainboard/asus/kfsn4-dre: Use Fallback boot image by default
Change-Id: Ib58550acda63132e35a526c72ac7d987b457cea5
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8686
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-15 02:57:53 +01:00
Timothy Pearson d7210c579e mainboard/asus/kfsn4-dre: Change default debug level to Spew
This brings the KFSN4-DRE in line with other boards in the tree.

Change-Id: I9216130f51ed0576871fd27ca6ae4610c5f5810e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8683
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-15 02:57:32 +01:00
Timothy Pearson b812d5d92f northbridge/amd/amdht/h3finit.c: Fix boot failure
GIT hash 586d6e introduced a regression that causes boot failure
with an f0011449 AMD stop code.

Change-Id: Ieced9088b79bc89d55117b7240b82a086eff9d21
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8685
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-15 02:45:50 +01:00
Kyösti Mälkki 8517f94bfd OxPCIe952: Fix read8/write8 argument
This was missed in commit bde6d309 as the driver is not enabled
in any configuration by default.

Change-Id: I3d886531f5bcf013fc22ee0a1e8fa250d7c4c1a4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8660
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-14 00:10:52 +01:00
Vadim Bendebury f9fb0d9bf3 Use a common boardid.h instead of per board copies
There is no point in duplicating boardid.h per board - they are all
the same. Let's keep a single instance in the common include directory
and let the linker report a problem if one tries using this function
on a board where it is not supported.

BUG=chrome-os-partner:30489
TEST=verified that coreboot builds fine for nyan_big and nyan_blaze.

Original-Change-Id: Ifbe9c2287a1d828d4db74c637d1d02047ac4da25
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/209699
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 589e6415faf18ca6aaf44da343dd33eadc8a53d3)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I8eef89cb822611a0050e5a50fc4b970eebd8d962
Reviewed-on: http://review.coreboot.org/8666
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-13 23:01:54 +01:00
Yogesh Lal 419fa61f37 libpayload: ipq808x: stale interrupt shall not be cleared unconditionally
The serial driver hangs in cases when FIFO has more than single word to be
processed. Easiest way to reproduce is to paste a string of greater than 4
characters in cli.

Clearing the RXSTALE interrupt without draining all the characters from FIFO
leads to the issue as the driver is dependent on msm_boot_uart_dm_read
function to reinitialize for next transfer.

Logically the driver is organized in such a manner that next transfer never
gets initiated till rx_data_read < total_rx_data. Clearing the RXSTALE without
consideration of total number of characters (or words) unprocessed makes the
msm_boot_uart_dm_read to return on the first if conditional. Thus the driver is
stuck forever.

A quick fix is to avoid clearing the stale interrupt. Reset is handled whenever
a new transfer is initialized in msm_boot_uart_dm_init_rx_transfer.

BUG=chrome-os-partner:29542
TEST=manual
	-Paste a string greater than 4 characters in cli.

Original-Change-Id: I016afb01a77cd14764f0176f6bf144fb29796c2f
Original-Signed-off-by: Yogesh Lal <ylal@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/209512
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
(cherry picked from commit 61528884ad2c0a8e146054bbfeb01a3bc73b9692)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I936af5daa52a25f62133bdf9fb44f0b68cf34e88
Reviewed-on: http://review.coreboot.org/8667
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-13 23:01:39 +01:00
Timothy Pearson 586d6e2a88 northbridge/amd/amdht: Allow mainboards to set HT frequency limit
This is useful when the PCB layout of a mainboard does not allow
stable operation at the increased HyperTransport speeds of newer
processors.

Change-Id: Idc93a1294608178ddf38ca72d40e6bad7deb9004
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8464
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-13 21:17:58 +01:00
Kyösti Mälkki 668828d3b3 siemens/mc_tcu3: Fix build and ACPI IRQ bridge entry
Propagate commit d08057a change to this new FSP platform.

Change-Id: Ie83c7f3573c189f4e4576c971dbc12099bb7b123
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8662
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2015-03-13 19:21:25 +01:00
Julius Werner c5cd57c330 nyan: Remove broken setup_display() from romstage
This patch removes a chunk of romstage code from Tegra and all Nyan
boards that was supposed to enable some LCD power rails early, but never
really worked. The dev_find_slot() function can only find PCI devices,
which the CPU cluster is not. Since we're done with Nyan-RO and the
ramstage display code is fine as it is, there is no point in trying to
fix this... but we should remove it from ToT lest someone uses it as a
blueprint to add more dead code to future boards.

BRANCH=None
BUG=None
TEST=None

Original-Change-Id: I6eee256873299429d4e3934fe7d454120390f34d
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207720
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit a3df62a3bcefcc20ae59648f5d1f0a01db3c02c6)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I8deedea5e9787848aae3064509c611bc349313cc
Reviewed-on: http://review.coreboot.org/8638
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-03-13 18:43:19 +01:00