Commit Graph

42418 Commits

Author SHA1 Message Date
Angel Pons 685dc56b9f sb/intel/ibexpeak: Drop P_LVLx support in FADT
IO MWAIT redirection is not enabled. The code is missing, but C-states
should instead be reported using the _CST ACPI object.

Change-Id: I21fd2fa6ee4aa1ed57694549d5cb48159f37af26
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-07 11:37:01 +00:00
Angel Pons 772c09739e cpu/intel/model_206ax/acpi.c: Do not report P_BLK
IO MWAIT redirection is disabled, which means reads to the P_LVL2 and
P_LVL3 "registers" will never produce any C-state transition requests.

Change-Id: Ibbf7b915a9909d6bc8e784a439df751e11ec5bee
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-06-07 11:36:53 +00:00
Christopher Meis 1128817ed6 3rdparty/intel-sec-tools: Update to support Boot Guard
Update intel-sec-tools to commit of BootGuard support.
Remove --coreboot argument in src/security/intel/cbnt/Makefile.inc:
was removed as argument for cbnt

Change-Id: Iaf34bdb65a5f067d1d632e35d340b8fc49aaf318
Signed-off-by: Christopher Meis <christopher.meis@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55013
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-07 11:36:22 +00:00
Tony Huang 66713d0cc9 mb/google/dedede/var/kracko: Add P-sensor support
Configure GPIO D22/D23/E11.
Add P-sensor to device tree, these registers are draft version.

BUG=b:178092096
BRANCH=dedede
TEST=built firmware and dmesg shows STH9324 initial success.

Change-Id: I2c8feedd6efc1a471304322a17480c836e22349e
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-07 11:36:10 +00:00
Raul E Rangel 6b4b4a8349 drivers/pcie/rtd3/device: Add PCIe RTD3 driver
This driver was inspired from soc/intel/common/block/pci/rtd3. I decided
to copy and modify it because the Intel driver has a lot of Intel
specific code.

This driver has been stripped down to only provide a power resource and
set the StorageD3Enable property. This driver is SoC agnostic and does
not handle suspending the actual PCIe root port. That should be
implemented by an SoC specific driver.

This is required for Guybrush to suspend/resume properly because the
NVMe power is tied to the S0 power rails, so the kernel needs to place
the device into D3.

BUG=b:184617186
TEST=Guybrush is able to suspend/resume properly. Also see power
resource get enabled / disabled.
[   56.075559]     power-0416 __acpi_power_off      : Power resource [RTD3] turned off
[   56.075562] device_pm-0279 device_set_power      : Device [PXSX] transitioned to D3cold
[   56.075567] pci_pm_suspend_noirq: nvme 0000:02:00.0: PCI PM: Suspend power state: D3cold
[   56.075569] nvme 0000:02:00.0: pci_pm_suspend_noirq+0x0/0x413 returned 0 after 15978 usecs

[  123.464874] nvme 0000:02:00.0: calling pci_pm_resume_noirq+0x0/0x11d @ 7, parent: 0000:00:02.4
[  123.464891] acpi_device_set_power: ACPI: \_SB_.PCI0.GP14.PXSX: Power state change: D3cold -> D0
[  123.464982]     power-0360 __acpi_power_on       : Power resource [RTD3] turned on
[  123.464984] device_pm-0279 device_set_power      : Device [PXSX] transitioned to D0
[  123.465039] nvme 0000:02:00.0: pci_pm_resume_noirq+0x0/0x11d returned 0 after 158 usecs

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I2adfc925183ff7a19ab97e89212bc87c40d552d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-07 11:35:47 +00:00
Furquan Shaikh b9b6f4d013 soc/intel: Drop unused lpss functions
This change drops the following unused lpss functions and related
code:
* soc_lpss_controllers_list
* is_dev_lpss

These functions were added to determine if a controller is LPSS for
performing IRQ configuration. But, these never got used and hence are
being dropped.

Change-Id: I27bdfbca7c199e823a0e4fdb277e3f22fb6bae7a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-07 11:35:08 +00:00
Matt DeVillier c6a3f34096 payloads/tianocore: Fix orphaned reference to 'bootloader' variable
commit d3b49b4
[payloads/Tianocore: Update default build target, simplify build options]
simplified the build string and removed the bootloader Makefile variable,
but one reference was missed. Luckily the variable being empty didn't
break things, but correct it regardless.

Change-Id: If37b291dda59c20bfe4c6e5b9100fac52d11a2f4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55239
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-07 11:34:50 +00:00
James Ye b92a4d682f sb/intel/bd82x6x: Add missing ID for PCI bridge
The PCI device ID 0x244e for the "Intel Corporation 82801 PCI Bridge"
for desktop platforms was missing.

Change-Id: I22cdbcf518d86af7b93de7731d175088a81bbc1f
Signed-off-by: James Ye <jye836@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-06-07 11:34:27 +00:00
Angel Pons 023968453e sb/intel/bd82x6x: Use array for PCIe ASPM overrides
Using an array reduces the amount of boilerplate code.

Change-Id: Ic6a48a01d3b96e69273dc28bdb6699ce7c0931b2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55246
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-07 11:34:11 +00:00
Sridhar Siricilla d047927168 soc/intel/alderlake: Set Base Addresses for TBT DMA remapping engines
The patch configures 4KB memory region window for each of the TBT DMA
remapping engine. So, the remap engines map their register set to
the respective 4KB window.

TEST=Verified boot on Brya

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I669255065d60d73c4bea0eeb732c4114bcc447c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55015
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-07 06:40:17 +00:00
Lean Sheng Tan b67c5edf82 3rdparty/fsp: Update submodule pointer to newest master
Newest master includes these changes:
1. Introduce the FSP package for Elkhart Lake SKUs
2. Introduce the FSP package for Tiger Lake IoT SKUs
3. Update the FSP package to latest version for Apollo Lake,
   Comet Lake and Tiger Lake (client SKUs)

You can get further 3rdparty/FSP commit history here:
https://github.com/intel/FSP/commits/master

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I96d147fec82d0fcd5c7748c277deb0672a975ceb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55228
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-07 05:27:21 +00:00
Raul E Rangel 6d2bc001ea acpi/device: Add ability to generate proper _STA for PowerResource
acpi_device_add_power_res currently generates a `_STA` method hardcoded
to ON. This change enables the ability to generate a `_STA` method that
queries the status of the GPIOs to determine if the power resource is ON
or OFF.

BUG=b:184617186
TEST=Dump SSDT table for guybrush

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I91410556db002c620fd9aaa99981457808da93a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-07 05:21:30 +00:00
Karthikeyan Ramasubramanian fec4db954e soc/amd/cezanne: Configure I2C Pad RX Select through devicetree
Some of the I2C buses are required to operate at different voltage level
compared to other I2C buses eg. I2C bus to Google Security Chip (GSC)
should be at 1.8V level. By default, all the I2C buses are initialized
to operate at 3.3 V. Add support to configure I2C pad RX select through
devicetree and update the concerned devicetree.

BUG=b:188538373
TEST=Build and boot to OS in Guybrush. Ensure that the communication
with GSC is fine. Build Majolica mainboard.

Change-Id: I595a64736fdac0274abffb68c5e521302275b845
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-07 05:18:49 +00:00
Karthikeyan Ramasubramanian fcb9716db5 mb/google/guybrush/var/guybrush: Update GPIO configuration
Some of the GPIOs are either re-purposed for different use-cases or are
unused in upcoming board phase (board version 2). Update the GPIO
configuration accordingly. Here are the GPIOs that are updated:
GPIO	Board Id 1		Board Id 2
=============================================
GPIO31	TP183			EN_SPKR
GPIO69	EN_SPKR			SD_AUX_REST_L
GPIO70	SD_AUX_RESET_L		Unused TP27
GPIO74	RAM_ID_CHAN_SEL		Unused TP49

BUG=b:189327557, b:188542649, b:188542497
TEST=Build Guybrush mainboard. Verify Audio is audible and SD card is
detected fine in Board ID 1.

Change-Id: I31523b3e03d2b59577f33eae548747834cfc98aa
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-07 05:18:41 +00:00
Kangheui Won 260f0f93ef cezanne/psp_verstage: add reset/timer svc
The new cezanne PSP release added support for these svcs. So add those
functionality back to cezanne psp_verstage.

BUG=b:187906425

Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Id542f5ed0762f582ea966466d67ed938ecb9c1f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-07 05:16:20 +00:00
Kangheui Won 32f43e0e13 psp_verstage: initialize i2c in soc_init
GSC is connected with AP via i2c bus so we need to enable i2c in
psp_verstage.

Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I5f7b73be67a692ea7de31ae53bd111d0e4b6998c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55136
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-07 05:16:06 +00:00
Matt DeVillier 7ca3ecb73a drivers/smmstore: Enable SMMSTORE V2 by default for Tianocore UEFIPAYLOAD
Tianocore UEFIPAYLOAD now supports SMMSTORE V2, so enable it by default

Change-Id: I33582427fe9d3fc7c15014d3a04fcdc533cb1ac8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-07 05:06:23 +00:00
Matt DeVillier 3469378a17 payloads/tianocore: Restrict bootsplash option to UEFIPAYLOAD
The custom bootsplash option only functions when using the UEFIPAYLOAD
payload option, so restrict visibility to when that option is selected.

Change-Id: If5fe46b629e5275da54a5e86465a68271110397b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-07 05:06:01 +00:00
Matt DeVillier ba7f116728 payloads/tianocore: Add Kconfig option to enable cbmem logging
Logging to coreboot cbmem, instead of a serial console, was
added to MrChromebox's uefipayloadpkg branch. Add a Kconfig
option to enable this, and restrict it to the UEFIPAYLOAD
payload option, since this feature does not exist in upstream
edk2.

Change-Id: Idef125235dc7ba885eb22ac69c6f752588a9e295
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
2021-06-07 05:05:24 +00:00
Angel Pons 6e7f9d6824 cpu/intel/model_206ax/acpi.c: Do not report P_BLK
IO MWAIT redirection is disabled, which means reads to the P_LVL2 and
P_LVL3 "registers" will never produce any C-state transition requests.
Moreover, the register resource descriptors for all reported C-states
use the FFixedHW address space, not I/O.

Change-Id: I026835dd24d7ac1e1bae2d851e011e1670abaad4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-07 04:58:34 +00:00
Angel Pons 151d561ddd cpu/intel/haswell/acpi.c: Do not report P_BLK
Even if IO MWAIT redirection were enabled, the base address is wrong.
Moreover, the register resource descriptors for all reported C-states
use the FFixedHW address space, not I/O.

Change-Id: Ic2faaafbe4928994aeeab8098d8e0fb6703d203d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-07 04:57:46 +00:00
Angel Pons 00c95b13ab cpu/intel/model_206ax: Do not set PMG_IO_CAPTURE_ADDR MSR
The MSR only needs to be set when IO MWAIT redirection is to be enabled.

Change-Id: Ie856086babe4dadc690f701bd90a7bbac88cb4ad
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-07 04:56:21 +00:00
Tao Xia 42b6309595 mb/google/dedede/var/sasukette: Update DPTF parameters
Update DPTF parameters from internal thermal team.

BUG=b:180875580
BRANCH=dedede
TEST=emerge-dedede coreboot

Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: Id18a38cddbcacbafbe2c54d94dbda5e00de02b3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
2021-06-07 04:55:31 +00:00
Angel Pons 0caf80d8aa bd82x6x boards: Drop redundant `c2_latency`
If unspecified, chipset code already uses 101, and 0x65 == 101.

Change-Id: I524ca492fa577003df23017756f74a455582132f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-07 04:53:39 +00:00
Angel Pons d4e68eb414 mb/lenovo/t410: Enable WLAN and WUSB PCIe ports
These PCH PCIe ports are used and should be enabled.

Resolves: https://ticket.coreboot.org/issues/311
Change-Id: I26ace6e043c7c66f8944f0986923014703423b8c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Swift Geek (Sebastian Grzywna) <swiftgeek@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-06-06 13:57:08 +00:00
Angel Pons 3269ad328a mb/lenovo/t410: Update PCH PCIe RP comments
Looks like the comments were derived from a preproduction board's
schematics. Production boards use a different port mapping.

Change-Id: I40c267ff048959b131c22c07695212e8bd90c3f4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Swift Geek (Sebastian Grzywna) <swiftgeek@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-06-06 13:56:50 +00:00
Patrick Georgi 54f86a5a07 util/crossgcc: Avoid complex filename sets
bin/{foo,bar,baz} can fail if one of the files doesn't exist (depending
on the shell in use). Instead, cd into the directory and list the
files individually.

Change-Id: I042b2e45fded1b63551d8e65ead2a7bbbf96b1e7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-06 13:08:37 +00:00
Patrick Georgi 5a76a53034 util/crossgcc: Update to clang 12
Change-Id: I38fc64fa872e2ecb0a10fb5378b3ce0d6a02443c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-06 13:08:29 +00:00
Subrata Banik 66a5d40a5d mb/intel/sm: Use device aliases
Use the device aliases provided by alderlake chipset.cb instead of
the raw pci device+function.  Take advantage of the default states
in chipset.cb and only list the devices that are enabled for all
shadowmountain board variants.

TEST=Dump devicetree device enable list without and with this CL, no
difference observed.

Change-Id: I2b769d653ad8ad8ff069a0787d00ff33ead5c912
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-05 19:54:53 +00:00
Subrata Banik 2cfb83fcf3 mb/intel/adlrvp: Use device aliases
Use the device aliases provided by alderlake chipset.cb instead of
the raw pci device+function.  Take advantage of the default states
in chipset.cb and only list the devices that are enabled for all
different adlrvp boards.

TEST=Dump devicetree device enable list without and with this CL, no
difference observed.

Change-Id: Ib9e82d953416c076588974f3167d00ae96f01bb5
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55205
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-05 19:54:43 +00:00
Subrata Banik c000057aa6 mb/intel/{adlrvp, sm}: Remove ADL-S devices from ADL-P/M devicetree.cb
Change-Id: I095394d9a79506346b8464c850d03cbd8ce2b812
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55221
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-05 16:49:38 +00:00
Subrata Banik 8a0aea8d58 soc/intel/alderlake: Add IDE-R and KT device into chipset.cb
Add IDE-R and KT device to chipset.cb and leave it off by default.

Change-Id: Iaa51e3dc107eb3f06ad7b2aad72a6bc112999d98
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-05 16:49:26 +00:00
Zhiqiang Ma 1c70f8f48a soc/mediatek/mt8195: fix GPIO register offsets
Correct the offsets by MT8195 Register Map V0.2-1
chapter: 3.2 GPIO Controller (page 3272)

Control register names:
	PUPD_CFG0
	PU_CFG0

Signed-off-by: Zhiqiang Ma <zhiqiang.ma@mediatek.com>
Change-Id: I9b0f8a24756092a97933cc9d4ba13a9e79c73e91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55163
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-05 13:05:15 +00:00
Rex-BC Chen ef53634d9a mb/google/cherry: Get RAM code from ADC
On Chromebooks the RAM code is implemented by the resistor straps
that we can read and decode from ADC. For Cherry the RAM code can be
read from ADC channel 2 and 3.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I4f28bc1c567cb886bd90d930219981a6206b9bb9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-05 13:05:03 +00:00
Zhiqiang Ma d2644dbf5f soc/mediatek/mt8195: Enable mt8195 auxadc
Enable auxadc on MediaTek mt8195 platform.

Signed-off-by: Zhiqiang Ma <zhiqiang.ma@mediatek.com>
Change-Id: Ie79420e20c9ed6155791b490e1b5e4b44a579a49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-06-05 13:04:54 +00:00
Rex-BC Chen 9e3e0f560b mb/google/cherry: Initialize SPM
This patch adds support for SPM. This adds 43ms to the boot time.

TEST=program counter of SPM is correct value after booting up.

Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I5f17f6d51fc9ad2d23c71c3c5cd29fdc777dc071
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55154
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-05 13:04:43 +00:00
Tim Wawrzynczak fb1858539f Revert "src/mainboard: Add Star Labs labtop series"
This reverts commit 2e665eb8da.

Reason for revert: Was submitted too early and out-of-order.

Change-Id: I119b7a81b849bbe3424d73d5fdf9b55481444686
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54971
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04 18:52:32 +00:00
Daisuke Nojiri fc7900b6b9 vboot: Add VB2_CONTEXT_EC_TRUSTED
This patch makes coreboot set VB2_CONTEXT_EC_TRUSTED based on the EC"s
boot mode. Vboot will check VB2_CONTEXT_EC_TRUSTED to determine
whether it can enter recovery mode or not.

BUG=b:180927027, b:187871195
BRANCH=none
TEST=build

Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I9fa09dd7ae5baa1efb4e1ed4f0fe9a6803167c93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-04 18:51:20 +00:00
Subrata Banik c11d4fb0b0 mb/google/brya: Remove I2C4 usage in devicetree.cb
I2C4 is not used pn Brya hence make below changes:
1. Disable it in SerialIoI2cMode.
2. Remove I2C4 config in common_soc_config.

TEST=Make sure FSP is not programming I2C4.

Change-Id: I94c72b7fac9d8a001913b5faa2c0c8a3e8b701e9
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-04 18:25:16 +00:00
Sean Rhodes 2e665eb8da src/mainboard: Add Star Labs labtop series
Add support for LabTop Mk III (kblr) and LabTop Mk IV (cml)

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Iffa6061b0e600880b0c93746f35b1731e4841e31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-04 17:21:21 +00:00
Sean Rhodes 2d89789337 ec: Add Star Labs ITE 8987E support
Support for Star Labs labtop series EC

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1967f7c4a7e3cab714f22844bf36749e0c9652b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-04 17:20:56 +00:00
Tim Wawrzynczak cbd2abf9b4 soc/intel/alderlake: Add PMC ACPI interface
This ACPI interface is required by e.g., the intel/common/pcie/rtd3
driver, which is used by some alderlake boards.

BUG=b:190080798
TEST=disassemble SSDT and find \_SB.PCI0.PMC.IPCS

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I59eae47e623587d35e394c9bff21481fcad2d6b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55172
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04 16:33:53 +00:00
Taniya Das 017c59096a soc: common: gpio: Add support for common GPIO driver
Add common gpio functionalities across qualcomm soc targets.

This common gpio driver would allow the consumers to be able to
configure gpio function, set/get gpio direction as input/output,
configure the gpio as pull-up/pull-down, configure the gpio as an
IRQ and also query the gpio irq status.

The GPIO pin definition would be SoC specific.

BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Change-Id: Ia672130c6ca938d9284cae5071307637709480d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55076
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04 12:40:41 +00:00
Ravi Kumar Bokka 414b4269be sc7280: Reserve wlan & wpss dram regions index order corrected
BUG=b:182963902
TEST=Validated on qualcomm sc7280 developement board

Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: I8501e9ce52bb296bb42797d8b43fd38174b80550
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2021-06-04 12:40:30 +00:00
Werner Zeh b2bb959ecf mb/siemens/mc_apl2: Disable unused I2C controllers
Only I2C controller 3 is used on this mainboard. Disable all other
controllers.

Change-Id: Id06d98787a0574a5b3a8dc2e86858dfcc7154606
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-06-04 12:40:06 +00:00
Werner Zeh a67bda339e mb/siemens/mc_apl{1,2,3,5,6}: Provide I2C timings for 400 kHz
The I2C bus at which the external RTC is attached to is operated at
standard speed (100 kHz) at coreboot runtime. The OS can choose to run it
at fast speed since it uses its own driver and controller setup.

Report additional bus timings for fast mode so that OS can do it right.

Change-Id: I82e11e5dde8ad1047713f105c5a6d020eebf1ffd
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55089
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04 12:39:57 +00:00
Werner Zeh 1e02ad3f5a drivers/i2c/designware: Report I2C timings for additional bus speeds
Since the OS provides its own driver for the I2C controller it can
choose to use a bus speed other than the one used at coreboot runtime.
In this case it would be good to provide a way how the needed bus
timings are communicated to the OS, since these are very board-specific
and there is no way that the OS can know them other than read the
appropriate ACPI reported timings.
This patch adds some code to report additional bus speed timings if
there are some defined in the devicetree.

Change-Id: If921e0613864660dc1bb8d7c1b30fb9db8ac655d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-06-04 12:39:06 +00:00
Dtrain Hsu fb9aecdf8b mb/google/dedede/var/cret: Add new Goodix touchscreen
Add Goodix GT7996F touchscreen into devicetree for cret.

BUG=b:180547935, b:188501391
BRANCH=dedede
TEST=Built cret firmware and verified touchscreen function.

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I2a6f7c1e9900492937202c0bc6595674f1e79e5b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-06-04 12:38:46 +00:00
Rocky Phagura d4db36e672 src/intel/xeon_sp: add hardware error support (HEST)
This patch adds the ACPI hardware error source table (HEST) support.
This involves a few different parts: (1) The ACPI HEST table which is filled
with the appropriate fields (2) Reserved memory which is used by runtime
SW to provide error information. OS will not accept a HEST table with
this memory set to 0.

The ASL code to enable APEI bit will be submitted in a separate patch.

Tested on DeltaLake mainboard with following options enabled
SOC_INTEL_XEON_RAS

After boot to Linux, the following will show in dmesg:
HEST: Table parsing has been initialized

Change-Id: If76b2af153616182cc053ca878f30fe056e9c8bd
Signed-off-by: Rocky Phagura <rphagura@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-04 12:38:32 +00:00
Sugnan Prabhu S 3bfa1bde60 mb/google/brya: Add firmware configuration probing for audio
For all of the audio devices in overridetree.cb add the probe matches
that will determine if the device should be enabled or not based on the
selected audio daughter board type.

AUDIO=MAX98357_ALC5682I_I2S: enable max98357, dmic1 and alc5682i
AUDIO=MAX98373_ALC5682_SNDW: enable max98373, dmic2 and alc5682

BUG=b:188696010
TEST=test different audio devices based on fw_config value:
> AUDIO=UNKNOWN
ectool cbi set 6 0x00000000 4 2
> AUDIO=MAX98357_ALC5682I_I2S
ectool cbi set 6 0x00000100 4 2
> AUDIO=MAX98373_ALC5682_SNDW
ectool cbi set 6 0x00000200 4 2

Change-Id: I6f159442516830f9d304d78c83f070e4fcff4a37
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-04 12:38:15 +00:00