The SATA device moved from 0:1f.2 to 0:17.0, 0:1f.2 became PMC. We
detect that by checking the PCI device class.
The ABAR MMIO space has grown to 2KiB and up to 8 ports are supported
now. For backwards compatibility, only dump port registers of ports
that are enabled in the Ports Implemented (PI) register.
Change-Id: I8e0f07d7359d92f689882b5afefa5ffb3766ee8b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
We have to call pci_free_dev() for each device we allocated with
pci_get_dev(). Since that's not the case for `sb`, we can close
this TODO.
Change-Id: I1ef80c837263a205467f835156dcb8fa667d3a8f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This is supposed to fill the `size[]` array with the actual sizes of
a device' MMIO ranges, but apparently isn't implemented for every
access method in libpci (we let the library choose one). It tells us
by clearing `PCI_FILL_SIZES` in the return value of `pci_fill_info()`
(which we don't check). Since we don't ever use `size`, we can just
make it clear and don't ask for it.
Change-Id: I3fb9334472f1c7563a9e17910190f73affbe067a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The Wildcat Point-LP Premium is handled the same as the Wildcat Point-LP,
but it wasn't supported by inteltool.
Change-Id: I694514e1963f074582a3f5f81d63c20e7fa49189
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/19445
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Lint prevents my next commit which adds a new line to the table
so it's better to break all the > 80 character lines so it will be
consistent with the new line I'm about to add.
Change-Id: Ic7ad0cb90e861cd830db1186225d4f839250792a
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/19444
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Without this change inteltool cannot read BIOS_CNTL values nor can it
read the SPIBAR values.
Change-Id: I9ff16e060aca66e3cb11c8315a6843ccecd1d3c2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17979
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The ICH7 SPIBAR offset and registers are different from later
generation.
ICH8 has a different offset from later generation.
ICH6 has no SPI controller.
Change-Id: I7691bce619089b15805114047bcb1fd121a5722b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17978
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Use a unique bus/device/function if a bay trail LPC bridge was found.
TEST=Run on MinnowBoard MAX Turbot and customer's LynxPoint-LP.
Change-Id: Ib4b50aaf9817ac94f46c28925081540676226d84
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17464
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
According to datasheets for Intel ICH/PCH, it works for chipsets from
ICH7 to 9-series PCH, with PCI device address D31:F2.
Change-Id: If1ddd7208108bda949b5a94894a7bf9e8bfe1e5f
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/15106
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
A struct pci_dev was allocated but not freed.
Change-Id: I6a8bbef6a118fc1f0aa7037e72c4d0dda9208f4b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1353037
Reviewed-on: https://review.coreboot.org/15971
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The current implementation from Vladimir simply dumps 1 MB of memory
contents starting at the base address of the second PCI device (which
most likely is the VGA controller on Intel systems). This locks up a
number of different systems, e.g. my Ibex Peak-based T410s.
This patch documents the issue and stops dumping the graphics registers
for the -a/--all parameter.
Change-Id: I581bdc63db60afaf4792bc11fbeed73aab57f63a
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/14627
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
- manpage
- usage message
- new warning message if -S is used on an unsupported chipset
Change-Id: I1acaa5f4232b65244ec00fd22ec7460d9cc387f1
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/14624
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The license text that we decided to remove was removed from the headers
of these files, but was still left in the help text. Remove it from
those locations as well.
Change-Id: I0e1b3b79f1afa35e632c4a4dd09a8bf2b02eaa6d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12913
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.
This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.
Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
- Have clean remove junit.xml files.
- Remove junit.xml target from cbmem makefile - this is in the top
level Makefile.inc now.
- add distclean targets to makefiles.
- Make sure all makefiles have .PHONY set up.
- rm commands need -f or they will fail if the file they're trying
to remove doesn't exist, causing the build to fail.
Change-Id: I2f0635f2c0a9417e3377a90c8d67103323c4a72f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12120
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
E.g. on my MacbookAir to generate spd.bin to be used
with coreboot I do:
./inteltool -S spd.bin
Change-Id: If165475ed3e1f3262a8926ef619128d25b1e2896
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11847
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Previously, X4X was incorrectly named because it provides
support for SKUs within XX4X range. This is renamed.
This patch provides support for all X4X SKUs according to
datasheet Intel 4 Series Chipset Family Specification Update,
namely: Q45, Q43, P45, P43, G45, G43, G41 and B43 (both versions).
Tested on Gigabyte GA-G41M-ES2L
Change-Id: I032265e80d9ca51e2fef29201280832ea3210a0b
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/11245
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Used command line to remove empty lines at end of file:
find . -type f -exec sed -i -e :a -e '/^\n*$/{$d;N;};/\n$/ba' {} \;
Change-Id: I816ac9666b6dbb7c7e47843672f0d5cc499766a3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: http://review.coreboot.org/10446
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Follow up for commit b890a12, some contributions brought
back a number of FSF addresses, so get rid of them again.
Change-Id: I0ac0c957738ce512deb0ed82b2219ef90d96d46b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10322
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Useful for autoport and other gfx-related developpement.
Change-Id: I1fc0952bc30ab15cd39a4f0c00649714dcf318f3
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10276
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
As per discussion with lawyers[tm], it's not a good idea to
shorten the license header too much - not for legal reasons
but because there are tools that look for them, and giving
them a standard pattern simplifies things.
However, we got confirmation that we don't have to update
every file ever added to coreboot whenever the FSF gets a
new lease, but can drop the address instead.
util/kconfig is excluded because that's imported code that
we may want to synchronize every now and then.
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} +
$ find * -type f
-a \! -name \*.patch \
-a \! -name \*_shipped \
-a \! -name LICENSE_GPL \
-a \! -name LGPL.txt \
-a \! -name COPYING \
-a \! -name DISCLAIMER \
-exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} +
Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9233
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
add handling of PCI IDs for Broadwell-U/Wildcat Point LP,
using same functions as Haswell-U/Lynx Point LP
Change-Id: I1094cbdace3c73f0f85c2e27c676b877b1a04bfe
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: http://review.coreboot.org/10209
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ia90f967a4988214c719f374a49233bb6fade11b0
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8481
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I3bb5dc23885af8c992456ee5e4bd374cd4b813bf
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/8049
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
abuild, inteltool, and superiotool's manpages still referenced reporting
bugs to tracker.coreboot.org. Remove that url and change the message
to point to the coreboot mailing list instead.
Change-Id: I7a85bc2b36ccdb7f3798a39a08345c1a02a67e65
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7712
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Add IDs of some SNB and Haswell chips; use more descriptive names.
Add PCIEXBAR and PXPEPBAR read support for SNB/IVB/Haswell.
Change-Id: I16753bf90061fc2065b813b1c2169e7b7bcc89e8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/7360
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Mathias Krause <minipli@googlemail.com>
If we find multiple LPC controllers, we want to tell the user that we'll
ignore all but the first. However, we use 'dev' in the message (the
current device found) instead of 'sb' (the one we want to use).
Fix the message by using 'sb' and break the loop right away in this
case. It's sufficient to tell the user once which LPC controller we'll
use.
Change-Id: Ibd27e40525fabe8c63b112691ad49fd994c70a48
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: http://review.coreboot.org/7342
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Change-Id: I408614e743ab6f0f447b327c01d8f4dacf787124
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6692
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
It never worked.
Change-Id: Ic68614bb8ed481babf54b4f9d8db00635755f4d1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7324
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Nicolas Reinecke was noticing that in my Lenovo T410s logs the GPIO*3
settings were missing. This led to some investigation and this patch, thanks!
Change-Id: I7ba28aa00d10f988a7fe81e61d2e216b54a11006
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/7239
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
The GPIO offset of '0x44 - GP_IO_SEL3' as specified in the pch.h header
is incorrectly reported as 'GPIO_SEL3'.
Change-Id: I56dcdda109d5f57ed45938d60b995807bdfb46b1
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6459
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This patch supports northbridges: 0x0150 0x0154 0x0158 0x015c as 3rd gen core.
Tested on 0x0150 (0x0154 previously only model).
Change-Id: I53a33d864494dd4ac1cb9e8330450f56001ed92c
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/5873
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The raw CPUID is useful for matching the directories under 'src/cpu/intel'
and is not easy to find out otherwise because it is most often decoded
already. The decoded values are not obviously hexadecimal so prepend
them with 0x to make sure they are unambiguous.
The output differences look like this:
- CPU: Processor Type: 0, Family 6, Model 25, Stepping 2
+ CPU: ID 0x20652, Processor Type 0x0, Family 0x6, Model 0x25, Stepping 0x2
Change-Id: Id47f0b00f8db931f0000451c8f63ac1e966442c4
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3788
Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at>
Tested-by: build bot (Jenkins)
Also, add pretty printing of Westmere's DMI registers (tested on my t410s
by staring at non-zero output values :)
Apparently Nehalem does not have a MEMBAR? But there are some
documented memory controller control registers in PCI configuration
space... left out for now.
The PCIEXBAR is not documented publicly AFAICT, but there is
a similar register on a device on bus 0xFF. phcoder might know more...
Change-Id: I5faadb6e4f701728f5290276c02809b4993bd86d
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/3505
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
e4e8e090fa does add support for QM57,
but there are many more that should work with that code(?).
Does not explode on...
CPU: Processor Type: 0, Family 6, Model 25, Stepping 2
Northbridge: 8086:0044 (1st generation (Westmere family) Core Processor)
Southbridge: 8086:3b0f (QS57)
Change-Id: I85e15ba45678a5bd635415a7a8d69c05bff8f7ef
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/3321
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Nico Huber