Replace _delay with an arch_ndelay(). This way each arch can setup their
own delay mechanism.
BUG=b:109749762
TEST=Verified delay's still work on grunt.
Change-Id: I552eb30984f9c21e92dffc9d7b36873e9e2e4ac5
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28243
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The apic_delay method will halt the CPU and wait for a timer interrupt
to fire. I went with usec because nsec is too granular to guarantee.
This method will be called from an arch_ndelay() method when the delay
is large enough to justify a sleep.
BUG=b:109749762
TEST=Tested it on grunt by changing the _delay method to call
apic_delay().
Change-Id: I80363f06bdb22d0907f895885e607fde1c4c468d
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This is just the bare minimum required to initialize the APIC. I only
support xAPIC and chose not to support x2APIC. We can add that
functionality later when it's required.
I also made the exception dispatcher call apic_eoi so that the callbacks
won't forget to call it.
BUG=b:109749762
TEST=Booted grunt and verified that depthcharge continued to function
and that linux booted correctly. Also verified GDB still works.
Change-Id: I420a4eadae84df088525e727b481089ef615183f
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
BUG=b:109749762
TEST=Verified GDB still functions by hitting Ctrl+G on the developer
screen and stepping through some code.
Change-Id: I723a8a95f681c500d9d8e35e49fd1d893cb1f133
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
I need to setup the APIC timer to fire interrupts. I would like to reuse
the existing interrupt table. So I extended it to support user defined
interrupts. I just added all 255 vectors so there wouldn't need to be
any additional build time configuration.
I'm going to deprecate exception_install_hook and remove it in a follow
up. It will be replaced with set_interrupt_handler. This way the
exception lookup does not have to manage a list of callbacks, or have to
worry about the order they are processed.
BUG=b:109749762
TEST=Wrote an interrupt handler and fired an APIC timer interrupt and
verified that vector 32 was returned.
Change-Id: Id9c2583c7c3d9be4a06a25e546e64399f2b0620c
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Will be used by the APIC.
BUG=b:109749762
TEST=Verified by the other cls in the stack.
Change-Id: Id86f2719d98a90318ac625e09601e5dbb06e3765
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Since libpayload doesn't link against libgcc we need to define our own
cpuid macro. I didn't add any error checking since anything in the last
decade should support cpuid.
BUG=b:109749762
TEST=called it and made sure the correct flags were returned.
Change-Id: Id09878ac80c74416d0abca83e217516a9c1afeff
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Because the Kconfig configuration files for primary payloads are
already sourced via a wildcard pattern this change requires to
use another file name pattern.
Change-Id: I83b89f5e14618e8a487ebb044fcdd3c175662591
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/28217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Since we can derive chromeos_acpi's location from that of
ACPI GNVS, remove chromeos_acpi entry from cbtable and
instead use acpi_gnvs + GVNS_CHROMEOS_ACPI_OFFSET.
BUG=b:112288216
TEST=None
CQ-DEPEND=CL:1179725
Change-Id: I74d8a9965a0ed7874ff03884e7a921fd725eace9
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/28190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There is a confusingly named section in cbmem called vdat.
This section holds a data structure called chromeos_acpi_t,
which exposes some system information to the Chrome OS
userland utility crossystem.
Within the chromeos_acpi_t structure, there is a member
called vdat. This (currently) holds a VbSharedDataHeader.
Rename the outer vdat to chromeos_acpi to make its purpose
clear, and prevent the bizarreness of being able to access
vdat->vdat.
Additionally, disallow external references to the
chromeos_acpi data structure in gnvs.c.
BUG=b:112288216
TEST=emerge-eve coreboot, run on eve
CQ-DEPEND=CL:1164722
Change-Id: Ia74e58cde21678f24b0bb6c1ca15048677116b2e
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/27888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Curley brace expansion is a bash-ism, so we can't use it for the
u-root command list.
This unfortunately also breaks the current Kconfig option since the
list needs to be separated by space instead of commas.
Change-Id: I429a52c1673e29b7180ee6f53deaa7a551a1a9b3
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/27967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
BUG=none
TEST=compiled on grunt and made sure USB still works in depthcharge
Change-Id: I972f4604bb5ff3838cb15f323c5a579ad890ecf5
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Fixes build with gcc8.1
Change-Id: I042f79ddfb4c249e00b5b259280289b8534f6854
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/27546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add support for ARCH=ARM64 and introduce CROSS_COMPILE for all architectures.
* Always compress kernel Image using xz
* Create FIT uImage containing the kernel, initramfs and DTB
* Add ARM64 defconfig for all SoCs
Change-Id: I9a0cc248283432fb2384956ca55e687d4127398c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
If a port disconnects after a reset we should abort any initialization
on the port. This might mean the device has re-enumerated as a 3.0 device
so the hub should be scanned again.
BUG=b:76831439
TEST=Verified USB-C devices that get detected correctly in depthcharge.
Change-Id: Iad899544684312df1bef08d69b5c7f41eac3a21c
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Make it obvious that the command has failed.
BUG=b:76831439
TEST=Verified on grunt
Change-Id: Ifa0b2fb087f5f0a36ba017a774fc98b33ab035a4
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
xhci_rh_port_speed return -1 if the port is disabled. The usb_speed enum
is unsigned so this results in a positive value which implies success.
Adding a -1 to the enum will make it signed so the >= 0 check will work
correctly.
BUG=b:76831439
TEST=verified on grunt that -1 is returned when port is disabled.
Change-Id: I98a373717d52dfb6ca4dcc53a00dc1b4c240a919
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This makes it easier to know what offset each register references.
BUG=b:76831439
TEST=none
Change-Id: I92dcbd463ceb4dd8edbbd97b51a4e9aa32a983a6
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
As *None* is special and not a payload, it makes sense to put it at the
top. Also, it was at before the latest addition of the FIT payload
choice.
Fixes: a892cde6 (lib: Add FIT payload support)
Change-Id: I52163ea9472308ecbc396012d9912b9617e0c318
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/27414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
SeaBIOS 1.11.2 was tagged with the following changes:
```
f9626cc cbvga_set_mode: refine clear display logic
f88297a qemu: add qemu ramfb support
a2e4001 vgasrc: add allocate_pmm()
17b01f4 pmm: use tmp zone on oom
44b17d0 bochs_display_setup: return error on failure
4ba61fa cbvga_set_mode: disable clearmem in windows x86 emulator.
dd69189 cbvga_list_modes: don't list current mode twice
5f0e7c9 cbvga_setup_modes: use real mode number instead of 0x140
961f67c qemu: add bochs-display support
767365e cbvga: factor out cbvga_setup_modes()
7906460 optionrom: enable non-vga display devices
```
Tested by running it on a Thinkpad X230.
Change-Id: Iea13eb64b3d5af0b283bff096587a3039227b5c0
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Tested-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/27326
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since SeaBIOS 1.11.0 implements serial console and etc/sercon-port
runtime config file is present in CBFS, SeaBIOS additionally
redirects iPXE output to configured IO port. For boards which use
the same UART for SeaBIOS and iPXE console it causes doubled
output.
The option is enabled by default and passes UART configuration
to iPXE Makefile as before. When unselected, only SeaBIOS handles
printing output from iPXE.
Change-Id: Ia3c74cfbee4f816782161fcff286a14f46be78c5
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-on: https://review.coreboot.org/27302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This change ensures that keyboard scanning is disabled and keyboard is
set to default state while disconnecting the keyboard. This is
required to ensure that the controller doesn't keep scanning and
buffering keystrokes which could lead to OS drivers reading stale
data.
BUG=b:110024487
TEST=Verified that kernel driver is able to probe correctly even if
multiple keys are pressed during handoff from payload to OS.
Change-Id: I1ffb8904d545284454c1825ee2e7c0087fc13762
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add CONFIG_LP_CHROMEOS to configuration file
Change-Id: I528dee96cf5052b99b8f7573010d98fd80680688
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/26711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The packge uuid-devel doesn't provide the required files,
but libuuid-devel does.
Change-Id: I61d537e4f1fca0d7172c129a75e13aa58452763f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/27136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
`freetype-config` is gone and was obsolete for a long time.
Change-Id: Id3058e55b1630f43225d3cd1ad91801c4085874f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/26822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* Add support for parsing and booting FIT payloads.
* Build fit loader code from depthcharge.
* Fix coding style.
* Add Kconfig option to add compiletime support for FIT.
* Add support for initrd.
* Add default compat strings
* Apply optional devicetree fixups using dt_apply_fixups
Starting at this point the CBFS payload/ can be either SELF or FIT.
Tested on Cavium SoC: Parses and loads a Linux kernel 4.16.3.
Tested on Cavium SoC: Parses and loads a Linux kernel 4.15.0.
Tested on Cavium SoC: Parses and loads a Linux kernel 4.1.52.
Change-Id: I0f27b92a5e074966f893399eb401eb97d784850d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
In order to support booting a GNU/Linux payload on non x86, the FIT format
should be used, as it is the defacto standard on ARM.
Due to greater complexity of FIT it is not converted to simple ELF format.
Add support for autodecting FIT payloads and add them as new CBFS_TYPE 'fit'.
The payload is included as is, with no special header.
The code can determine the type at runtime using the CBFS_TYPE field.
Support for parsing FIT payloads in coreboot is added in a follow on
commit.
Compression of FIT payloads is not supported, as the FIT sections might be
compressed itself.
Starting at this point a CBFS payload/ can be either of type FIT or SELF.
Tested on Cavium SoC.
Change-Id: Ic5fc30cd5419eb76c4eb50cca3449caea60270de
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Per PCI specification, function 0 must be present,
so functions 1 to 7 can be skipped in this case.
For a device that is not multi-function, it may not
decode function number in the hardware at all. To
avoid registering such a device eight times, skip
scanning functions 1 to 7.
Without the latter fix, a single-function PCI bridge
may call pci_scan_bus() second time and secondary
side devices would get appended second time in the
array devices[]. At that point, quicksort() apparently
hits an infinite recursion loop.
Since pci_scan_bus() is called in part of the early
modules->init() sequence early in main(), the errors
here left coreinfo payload completely silent when
PCI module was built-in on affected system.
Terminal screen was cleared, though.
Change-Id: Ifc6622f050b98afb7196de0cc3a863c4cdfa6c94
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Last time there was a request to change a link from HTTP to HTTPS, also
it seems more ethical to use a link to the Free Software Foundation
server. SHA1 is the same - 7fcaa428c6d0de7096d1e4fbfd14848096ae5aad.
Change-Id: I55147ee2668de03ba6e9feb84936de24b2a001df
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-on: https://review.coreboot.org/23855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Earlier this message has not been shown even at the corner of screen.
This fixes it by refreshing the screen, and moves it to the center.
Change-Id: If4e33e884c00c17f19ab330167d9293c8396ff3e
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-on: https://review.coreboot.org/23854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Earlier it was impossible to exit without pressing the power button.
Change-Id: Ia56d639fa8e563047fb3d2723695626a449ead40
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-on: https://review.coreboot.org/23853
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fixes two buffer overflows and opens a road to further improvements.
All the previous adjustments to libpayload_tint.patch (including the
latest "use the current time as random seed") have been preserved.
Change-Id: I22e65d18a0b1551f7049c4afe7f95868f584cf9b
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-on: https://review.coreboot.org/23852
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add function to get active keyboard modifiers.
Change-Id: Ifc7bd4aa86f20d67c5b542d0458b966e605c5499
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18601
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a new method to retrieve active usb keyboard modifiers.
Change-Id: Ief6679ce782b58b9ced207f4f27504fb2a517b76
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18602
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
keyboard_disconnect was called without keyboard_init being called and in this
case keyboard_havechar returns true because i8042_data_ready_ps2 is
dereferencing uninitialized variable ps2_fifo from within fifo_is_empty causing
keyboard_disconnect to be stuck in this while loop.
while (keyboard_havechar())
keyboard_getchar();
BUG=b:80299098
TEST=Check if the normal mode path in depthcharge is not causing a hang
Change-Id: I944b4836005c887a2715717dff2df1b5a220818e
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/26590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
We already have that Kconfig flag, so I guess we should use it for
consistency.
Change-Id: I61ee6a97e369ccfe5c55d4414a5fa91c8d80ecf7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This reverts commit 717ba74836.
This breaks seabios and a few other payloads. This is not
ready for use.
Change-Id: I48ebe2e2628c11e935357b900d01953882cd20dd
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/26310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Make use of i8042 driver to add PS2 mouse driver support.
Tested on Lenovot T500.
The touchpad can be used to drive the mouse cursor.
Change-Id: I4be9c74467596b94d64dfa510824d8722108fe9c
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Make use of i8042 driver in keyboard.c.
Required to add PS/2 mouse support.
Tested on Lenovo T500.
Change-Id: If60b5ed922b8fc4b552d0bfd9fe20c0fd6c776bf
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18596
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, adding a payload to CBFS using the build system, the warning
below is shown.
W: Unknown type 'payload' ignored
Update payload type from "simple elf" to "simple_elf" and rename the
word "payload" to "simple_elf" in all Makefiles.
Fixes: 4f5bed52 (cbfs: Rename CBFS_TYPE_PAYLOAD to CBFS_TYPE_SELF)
Change-Id: Iccf6cc889b7ddd0c6ae04bda194fe5f9c00e495d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26240
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a common i8042 driver that uses multiple overflowing
fifos to seperate PS/2 port and PS/2 aux port.
Required to support PC keyboard and PC mouse at the same time.
Tested on Lenovo T500.
Change-Id: I4ca803bfa3ed45111776eef1f4dccd3fab02ea39
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18594
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In preparation of having FIT payloads, which aren't converted to simple ELF,
rename the CBFS type payload to actually show the format the payload is
encoded in.
Another type CBFS_TYPE_FIT will be added to have two different payload
formats. For now this is only a cosmetic change.
Change-Id: I39ee590d063b3e90f6153fe655aa50e58d45e8b0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add: raw_read_cntfrq_el0() and raw_read_cntpct_el0()
Required to support Arch64 Timer
Change-Id: I86aa97039304b9e9336d0146febfe1811c9e075a
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/25649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
When GDB support is compiled in, halt() in libpayload will call
gdb_enter(). halt() is defined in <stdlib.h> and gdb_enter() in
<libpayload.h>. Usually files just include <libpayload.h> so this is not
a problem, but in some situatons a payload may just include <stdlib.h>
(or a file including it like <assert.h>), leading to an undeclared
identifier here. Move the GDB functions to <stdlib.h> to solve this.
Change-Id: I7b23b8ac9cd302aa6ef96f24565130490ac40071
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/25730
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The VA space needs to be extended to support 48bit, as on Cavium SoCs
the MMIO starts at 1 << 47.
The following changes were done to coreboot and libpayload:
* Use page table lvl 0
* Increase VA bits to 48
* Enable 256TB in MMU controller
* Add additional asserts
Tested on Cavium SoC and two ARM64 Chromebooks.
Change-Id: I89e6a4809b6b725c3945bad7fce82b0dfee7c262
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/24970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
SeaBIOS 1.11.1 was released with the changes below.
```
$ git log --oneline rel-1.11.0..rel-1.11.1
0551a4b paravirt: Only enable sercon in NOGRAPHIC mode if no other console
specified
a7aa43e pci: fix 'io hints' capability for RedHat PCI bridges
0e739f2 shadow: Don't invoke a shutdown on reboot unless in a reboot loop
5d9a515 build: Use git describe --always
```
Change-Id: Ia77e98edcd42b28677de9670ce13c2ea5d327315
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/25284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
GRUB2 doesn't support all architectures that coreboot supports.
Furthermore, coreboot's build script for GRUB2 doesn't support all of
these architectures.
Let the user select GRUB2 only when building for x86 and ARM, which are
known to work.
Change-Id: I5ef2020b2acb4cd008a57a2372734674f8b84a36
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The USBHID driver zero-initializes some but not all of the fields in its
usbhid_inst_t structure. This is a problem because under some
circumstances, some of the uninitialized fields may be read and lead to
incorrect behavior. Some (broken) USB keyboards keep sending reports
that contain all zeroes even when they have no new keys... these usually
get silently ignored, but if the usbhid_inst_t structure is in an
inconsistent state where 'previous' is zeroed out but 'lastkeypress'
is non-zero because it wasn't properly initialized, these reports will
be interpreted as keyrepeats of the bogus 'lastkeypress'. This patch
changes the code to just xzalloc() the whole structure so we won't have
to worry about initialization issues anymore.
Change-Id: Ic987de2daaceaad2ae401a1e12b1bee397f802ee
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/23766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Kconfig variables TIANOCORE_REVISION and TIANOCORE_REVISION_ID
do not have an effect without this fix, the build process would
checkout the hard-coded stable hash even if these variables are set.
Change-Id: I9711a370eeade3cba0a9e127deb3d96d82adc512
Signed-off-by: Gergely Kiss <mail.gery@gmail.com>
Reviewed-on: https://review.coreboot.org/22983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Both GRUB and SeaBIOS can chainload lzma compressed payloads.
Therefore it is beneficial to compress secondary payloads
like Memtest86+, coreinfo, nvramcui,... for both size reasons and
often also speed reasons since the limiting factor is generally the
IO of the boot device.
Tested with SeaBIOS and memtest86+ master on Thinkpad X220.
Change-Id: Iddfd6fcf4112d255cc7b2b49b99bf5ea4d6f8db4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Part of the original patch, commit 85a90e1, reverted edk2 commit:
1d7258f [CorebootModulePkg:Removing EFI_RESOURCE_ATTRIBUTE_TESTED]
which had the unintended effect of causing memory above 2GiB
from being unavailable (marked reserved) when booting without a
connected display (aka headles mode).
This commit strips the patch to only the component needed to fix
reading of the coreboot table low memory pointer.
TEST: boot 4GB google/panther without connected display, verify
memory above 2GB available via 'dmesg | grep BIOS-e820' and 'free -m'
Change-Id: I39327929f9b0b940fc12cdca1d744456fdc097e0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This fixes tianocore garbled framebuffer when 'x_resolution *
bits_per_pixel / 8' is not equal to 'bytes_per_line'.
This patch was also send to the edk2-devel mailing list:
https://lists.01.org/pipermail/edk2-devel/2018-January/020436.html
Tested on Thinkpad X220 with libgfxinit on 1366x768 display.
Change-Id: Ib9eaf692f86d416cd4ec3cc73a8b0aa0a28a38dd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Make is so that a different timer source can be provided instead
of TSC on x86 platforms.
BUG=b:72378235,b:72170796
Change-Id: I6faeecf7624a5aa4e1af8862036f1fbd2f54eb51
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In payloads/nvramcui/payload.sh line 5:
DIR=`dirname $0`
^-- SC2006: Use $(..) instead of deprecated `..`
^-- SC2086: Double quote to prevent globbing and word \
splitting.
In payloads/nvramcui/payload.sh line 6:
lpgcc -o $DIR/nvramcui.elf $DIR/nvramcui.c 2>&1 >/dev/null || exit 1
^-- SC2086: Double quote to prevent globbing and word \
splitting.
^-- SC2086: Double quote to prevent \
globbing and word splitting.
^-- SC2069: The order of \
of the 2>&1 and the \
redirect matters. The \
2>&1 has to be last.
Change-Id: Iceab2d0df49c642f54e6b911793aa1479f542644
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Updating from commit id f3bb31fee:
2017-09-08 (vboot: Support EC early firmware selection)
to commit 61cfcc3b:
2018-01-17 (meowth: Select CONFIG_DRIVER_BUS_SPI_INTEL_GSPI_VERSION_2)
This brings in 57 new commits.
Change-Id: Iadacc6017abbcc659e461d2fc27990ef8124871b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
With the tianocore payload on a Thinkpad X200 the filesize increased
by approximately 50% and the time to fetch and decompress the payload
increased by approximately %300 , so something is definitely wrong
with it and it shouldn't be used as the default compression method.
Change-Id: I9661c82750104d737596e7b3a8974324765938a5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Add the option to use the lz4 compression method
to compress payloads.
Also sets LZ4 as the default compression method.
Change-Id: Ic712f984f791d268440c8463eaea0d246aa31d99
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/15817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The MMIO address can change for different platforms
like Apollolake.
Change-Id: I6ec72d3a14f00212323a04e20d5a477dbc26b770
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Add just enough code and boilerplate to keep it compatible with future
libflashrom.
Change-Id: If0d46fab141da525f8f115d3f6045a8c417569eb
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The depthcharge .config only exists after depthcharge was built. Other
possible `PAYLOAD_CONFIG` files most probably miss a rule, too.
Change-Id: I8e6f79bb2bd07cbef1317f2623bbef9ca0e74880
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Tested-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/22137
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch adds support to read the SKU ID entry from the coreboot table
that was recently added in coreboot.
Change-Id: I1c3b375da6119a4f8e8e7e25a11644becb90f927
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22743
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch mirrors recent cleanups in coreboot regarding the strapping
ID entries in the coreboot table.
Change-Id: Ia5c3728daf2cb317f8e2bc72c6f1714d6cb4d080
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Using the stable version by default is consistent with
payloads/external/SeaBIOS.
Change-Id: I444ba2daaf5ecc5edde907a7842013f88e1c4c9b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/22528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This should make reproducible builds of coreboot with GRUB2 easier.
Change-Id: If855042945ab34f34c554e7490c811ec7b256980
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/22527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
SeaBIOS 1.11.0 was released on November 10th, 2017. Changes include
* Initial support for NVME drives
* Support for vga emulation over a serial port in SeaBIOS (sercon)
* Support for serial debugging using MMIO based serial ports
* Support for scsi devices with multiple LUNs
* Support for boot-to-boot persistent coreboot cbmem logs
* Improved coreboot vga (cbvga) mode setting compatibility
* Several bug fixes and code cleanups
See also https://www.seabios.org/Releases#SeaBIOS_1.11.0 and for all
details on the changes, use
git log --oneline rel-1.10.3..rel-1.11.0
in the SeaBIOS repository.
Change-Id: Ie46a526593177c5241fbd979c7fa1934478f7382
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/22429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Vasya Boytsov <vasiliy.boytsov@phystech.edu>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
SeaBIOS 1.10.3 was tagged on October 12th, 2017 with the following
changes.
```
$ git log --oneline rel-1.10.2..rel-1.10.3
b7661dd tcgbios: Fix use of unitialized variable
6055583 boot: Increase description size in boot menu
3551613 resume: Don't attempt to use generic reboot mechanisms on QEMU
```
Change-Id: I3a9ebf10a55118fc35aed688ea7ec794333c8227
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/22358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
bebitenc() just runs a downward loop over the same body as lebitenc().
That doesn't give you a byte-swapped result, it gives you the same final
value, just starting from the other side to fill it in. (Also, it
confused i++ and i--, so it really gives you a compiler error.)
The correct code needs to have the array index inverted relative to the
bit shift index to produce a big endian result.
Change-Id: I5c2da3a196334844ce23468bd0124bbe2f378c46
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When building the Go version of cbmem I found that
LB_TAG_MAC_ADDRS has the same value as LB_TAG_VERSION_TIMESTAMP.
I am guessing that this tag was little used. In any event, move it
forward to 0x33.
Change-Id: I038ad68e787e56903a2ed9cb530809a55821c313
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/22218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Since the git:// protocol is unencrypted and unauthenticated, there's a
security risk associated with using it: A man-in-the-middle attacker
could replace e.g. the master branch with malicious code.
Mitigate this risk somewhat by cloning GRUB2 via HTTPS.
Change-Id: Ice8f8d108e7dfa1a1ecd58d9735944fa9570ace8
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Updating from commit id 3f3a496a 2017-09-01 09:20:19
(image_signing: Fix loem.ini pattern for unibuilds)
to commit id 753e34e9 2017-08-31 10:12:40
(futility: Make rwsig sign command produce EC_RW image)
This brings in 5 new commits.
This also updates Depthcharge stable commit ID.
Updating from a843f262 2016-08-16 08:41:04
(kahlee: select emmc boot first if available)
to commit id f3bb31fe 2017-08-15 17:15:33
(vboot: Support EC early firmware selection)
This brings in 14 new commits.
Change-Id: I17d034e87fa642c5e30e933eb98bcfe5ceaaa3a8
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/21490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Previously the random seed was fixed, which led to the same sequence of
blocks for each run.
Now that libpayload has time(), no change is needed in the function
rand_init() of tint.
Change-Id: I2e482bbb9d33cdbbf3c15916458329f99fbc4450
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/20980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Updating from commit id 5a086f5c - Tue Jul 11 23:57:30 2017:
(ps8751: enable software sync.)
to commit id a843f262 - Wed Aug 16 23:37:52 2017:
(kahlee: select emmc boot first if available)
This brings in 20 new commits.
This matches with the updated vboot submodule.
Change-Id: If030bc3e75dd470838590540880213bd841154b8
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Credit for this patch goes to 'ReddestDream'.
The patch is pulled from https://github.com/MattDevo/edk2
TESTED on thinkpad X200.
Change-Id: I1517607cee8308c5f5443c58c16ce44056611e92
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
We were explicitly passing CC and TARGET_CC to configure but overwrote
that decision later by passing CC (with the value of TARGET_CC) directly
to a recursive make call. The latter overwrite was introduced because
`unexport` alone doesn't work on variables that were specified on a make
command line (they are added to MAKEOVERRIDES and passed to further re-
cursive make calls).
Instead of unexporting random variables, unexport those that were actu-
ally passed from payloads/external/Makefile.inc and clear MAKEOVERRIDES.
Do not pass OBJDUMP as that is nowhere to be found in the GRUB sources.
And, last but not least, add --disable-werror because building GRUB is
very susceptible to changes in the flex version.
Change-Id: Iaff2c72e89a5a540fe365eacb84811d5cff9d4d4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
this adds convenience definitions for MSECS_PER_SEC, USECS_PER_MSEC,
and USECS_PER_SEC along the lines of the time units in coreboot's
<timer.h>.
Change-Id: I489dc2d1ff55d137936acec74ac875dc7fbc1713
Signed-off-by: Caveh Jalali <caveh@google.com>
Reviewed-on: https://review.coreboot.org/20882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Create a directory patches, and add necessary patches to be applied to
upstream tianocore.
Patches include:
-Patch for no PCI address enumeration
-Patches to enable keyboard input
-Patch to disable serial to speed up boot process.
Patches pulled from https://github.com/MattDevo/edk2.
Additionally, modify tianocore Makefile to apply patches during build.
Change-Id: I4eaa602418995a68753b1ed13af8c6374eaa312f
Signed-off-by: Evelyn Huang <evhuang@google.com>
Reviewed-on: https://review.coreboot.org/20639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Currently the only testing we had was 'what-jenkins-does' and
'make lint'. While the lint testing is suitable for developers,
the 'what-jenkins-does' target really isn't, as it was designed
specifically for testing on jenkins.
This adds the infrastructure for basic tests that are more suitable
for the developer. Extended tests and improvements will follow.
Add the coreboot-builds directories to .gitignore.
TODO:
- Save/restore .config
- Update test-abuild to use existing COREBOOT_BUILD_DIR variable
Change-Id: I19e1256d79531112ff84e47a307f55791533806f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chris Ching <chingcodes@google.com>
Update the existing tianocore payload (which didn't do any more than
adding an elf payload with a specific name) to fetch and build the
UEFI corebootPayloadPackage, using the coreboot toolchain for
compilation. Only checkout the commit when changing commit IDs or if
version is master, instead of every time it builds.
Currently working if patches are merged into the upstream edk2
repository (to be included in a follow-on patch).
Change-Id: I0bf4cedec2d6821ae2a04184ebb5cf88979ccee3
Signed-off-by: Martin Roth <martinroth@google.com>
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Signed-off-by: Evelyn Huang <evhuang@google.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/15057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
libpayload needs a static copy of the out of line function
`font_glyph_filled()` in every TU that needs it. So make it static
inline.
This fixes a build error by gcc (Debian 7.1.0-12) 7.1.0 from Debian
Sid/unstable. This happens with any libpayload based payload like
coreinfo, nvramcui or tint.
```
[…]
LPCC build/coreinfo.elf (LINK)
/src/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(corebootfb.libc.o): In function `corebootfb_putchar':
/src/coreboot/payloads/libpayload/drivers/video/corebootfb.c:173: undefined reference to `font_glyph_filled'
[…]
```
Change-Id: I931f0f17b33abafdc49aa755a0dad65e28820750
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/20897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
the __must_check function attribute is pretty much straight from the
linux kernel - used to encourage callers to consume function return
values.
Change-Id: I1812d957b745d6bebe2a8d34a9c4862316aa8530
Signed-off-by: Caveh Jalali <caveh@google.com>
Reviewed-on: https://review.coreboot.org/20881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This introduces support for font scaling with a factor provided via
Kconfig. In practice, the font itself is not scaled at any point in
memory and only the logic to determine whether a pixel should be filled
or not is changed.
Thus, it should not significantly impact either the access time or
memory use.
Change-Id: Idff210617c9ec08c6034aef107cfdb34c7cdf029
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/20709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This introduces helpers for accessing the included font, instead of
using hardcoded values provided by the font's header itself.
It will allow painlessly adding support for font scaling in a subsequent
change. It should not introduce any functionality change.
Change-Id: I0277984ec01f49dc51bfc8237ef806f13e3547e2
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/20708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Bettong board with the standard configuration is not capable of
running nvramui with the default size.
malloc error happens on PDC_makelines(). Resulting in:
Booting from CBFS...
Run img/nvramcui
Calling addr 0x00100000
initscr(): Unable to create stdscr.
exited with status 1
Change-Id: I56a0fb3319fe77599bf3dd6c328a0b70be60a348
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-on: https://review.coreboot.org/20681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
AHCI spec explicitly states that we may poll.
TEST=Ran FILO on kontron/bsl6 and observed that the controller
always becomes ready during the first delay.
Change-Id: If34694abff14d719d10d89bc6771dbfa12065071
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This is (thankfully) not done by coreboot any more for recent chipsets.
Change-Id: If56e38037f7b1e53871ee63e6ff297028c59d493
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Use a `for` instead of a `while` loop and use meaningful identifiers.
Also, don't use more than one variable for one and the same purpose,
don't use more (non-const) variables than necessary, don't alter more
than one variable per statement, don't compare pointers of different
types and don't do pointer arithmetic on `void *`.
This was meant as a fix up to a regression but that has already been
fixed.
Change-Id: I0c8fd118d127a26cfcf68bfb0bf681495821e80a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This line has a weird history. It got a `|| exit 0` removed lately which
obviously was there to fix the presence of the superfluous `test` at the
beginning. Now, remove the `test` too to make the clean target always
succeed again ;)
Change-Id: I9e069cf5d9ac8416cf350161439aa60798ef7b6b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20769
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
- Add prompt so the defconfig can be selected for the build.
- Remove target rename code from makefile. The old versions don't build
with the latest vboot, so this isn't useful anymore.
- Change $(info ...) to an echo. info prints immediately when
evaluated, which made it print when it shouldn't have, on make clean
for example.
- Split up single line shell scripts into multiple lines
- Change checkout target to only update the commit id when actually
changing versions instead of on every build.
Change-Id: I46fc2822cf93c821b402e8961ceecedc088f486c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Update from commit eb583fa8 - Wed Mar 29, 2017
(rk3399_sdhci: Reintroduce PHY power-cycling at 52MHz)
to commit 5a086f5c - Tue Jul 11, 2017
(ps8751: enable software sync)
This brings the stable version of depthcharge forward by 74 commits.
Change-Id: I3a3719fa3a91824042d452de7774be85b884d96d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Fix an issue when setting an unaligned buffer where n is less
than the difference of the rounded up pointer and the pointer.
This was identified where n=1 was passed. n was decremented
once, as expected, then decremented again after the while()
evaluated to false. This resulted in a new n of 4GB.
Change-Id: I862671bbe7efa8d370d0148e22ea55407e260053
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
The memcpy(), memmove() and memcmp() functions use word by word
operations regardless of the pointer alignment. Depending on the
platform, this could lead to a crash.
This patch makes the memcpy(), memmove() or memcmp() operate byte per
byte if they are supplied with unaligned pointers.
Change-Id: I0b668739b7b58d47266f10f2dff2dc9cbf38577e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/20535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The optimization of the memset() function introduced by commit
dbadb1dd63 (libpayload: Reorder default
memcpy, speed up memset and memcmp) is provoking an issue on x86
platform when compiling without the CONFIG_GPL option.
GCC is making use of the movdqa instruction to copy words. This
instruction can raise a "General Protection Fault Exception" when it
is called on a non-aligned address argument.
Change-Id: I73382a76a4399d8e78244867f2ebb1dca176a6bf
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/20524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
When using the regular `if` construct, the compiler will check
the guarded code independently from the condition.
Change-Id: I00c5c7ae3720f75aa9415edb94cd2ce76cee8aee
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/18811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
If the framebuffer address is zero the corebootfb_init() function
should abort and not attempt to use it for video, otherwise it
will likely hang.
This was tested by booting on a board that does not have a display
attached and includes the previous patch to zero the framebuffer
structure in the coreboot tables.
Change-Id: I53ca2e947a7915cebb31b51e11ac6c310d9d6c55
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add a Kconfig value to enable building libpayload with the 586 compiler.
Update the cross compiler script to add the Kconfig value name that is
used when libpayload builds.
The Quark SOC does not support some of the instructions generated with
the 686 compiler (e.g. CMOV). Success occurs when
payloads/libpayload/build/config.h indicates that
CONFIG_LP_USE_MARCH_586=1.
TEST=Build and run on Galileo Gen2.
Change-Id: I04907e9a38ee139bae2e8b227821f54614707c25
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/20322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add the default configuration file for the Galileo board. The Quark SOC
requires building libpayload with march=i586.
TEST=Build and run on Galileo Gen2
Change-Id: Ifd4b533feacbab6f0d357e13d8cebb64bc1c18c6
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/20323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This symbol can be selected (e.g. in site-local/) to disable the user
friendly but annoying default payload choice.
Change-Id: I2f72d4efc0a428dce377c3d003b2c00a6c8d4c08
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19808
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The word 'coreboot' should always be written in lowercase, even at the
start of a sentence.
Change-Id: I2ec18ca55e0ea672343a951ab81a24a5630f45fd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
<https://coreboot.org> is redirected to <https://www.coreboot.org>.
```
$ curl -I https://coreboot.org
HTTP/1.1 301 Moved Permanently
Server: nginx/1.8.1
Date: Mon, 05 Jun 2017 10:41:33 GMT
Content-Type: text/html
Content-Length: 184
Connection: keep-alive
Location: https://www.coreboot.org/
```
So use the command below to use the final location to save a redirect.
```
$ git grep -l https://coreboot.org \
| xargs sed -i 's,https://coreboot.org,https://www.coreboot.org,g'
```
Change-Id: I4176c20ef31399f0063b41e3a0029cca0c1b0ff3
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/20035
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The coreboot sites support HTTPS, and requests over HTTP with SSL are
also redirected. So use the more secure URLs, which also saves a
request most of the times, as nothing needs to be redirected.
Run the command below to replace all occurences.
```
$ git grep -l -E 'http://(www.|review.|)coreboot.org'
| xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g'
```
Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/20034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
When using the regular `if` construct, the compiler will check the
guarded code independently from the condition.
Change-Id: I988fa9379e8c748013a67ef29fa908b4d9a970ad
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/18794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Rename `FRAMEBUFFER_KEEP_VESA_MODE` to `LINEAR_FRAMEBUFFER` and put
it together with new `VGA_TEXT_FRAMEBUFFER` into a choice. There are
two versions of `LINEAR_FRAMEBUFFER` that differ only in the prompt
and help text (one for `HAVE_VBE_LINEAR_FRAMEBUFFER` and one for
`HAVE_LINEAR_FRAMEBUFFER`). Due to `kconfig_lint` we have to model
that with additional symbols.
Change-Id: I9144351491a14d9bb5e650c14933b646bc83fab0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
coreboot and libpayload currently use completely different code to
perform a full cache flush on ARM64, with even different function names.
The libpayload code is closely inspired by the ARM32 version, so for the
sake of overall consistency let's sync coreboot to that. Also align a
few other cache management details to work the same way as the
corresponding ARM32 parts (such as only flushing but not invalidating
the data cache after loading a new stage, which may have a small
performance benefit).
Change-Id: I9e05b425eeeaa27a447b37f98c0928fed3f74340
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of storing inverted-colored bitmaps,
invert drawing of text bitmap on the fly by adding
an invert parameter down to libpayload. Merging
pivot and invert fields into flags field.
BUG=b:35585623
BRANCH=None
TEST=Make sure compiles successfully
CQ-DEPEND=CL:506453
Change-Id: Ide6893a26f19eb2490377d4d53366ad145a9e6e3
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/19698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
cbgfx currently does not support portrait screen which height >width.
so add it.
Change-Id: I66fee6d73654e736a2db4a3d191f030c52a23e0d
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Reviewed-on: https://review.coreboot.org/19474
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
input_underrun is defined but not used. A reasonably new compiler,
enabled warnings and warnings-as-error make the build break for no good
reason.
Change-Id: Ibeb7ba53aad5738938093ab7b34695c9c99c9afe
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/19482
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
This patch allows the CBMEM console to persist across reboots, which
should greatly help post factum debugging of issues involving multiple
reboots. In order to prevent the console from filling up, it will
instead operate as a ring buffer that continues to evict the oldest
lines once full. (This means that if even a single boot doesn't fit into
the buffer, we will now drop the oldest lines whereas previous code
would've dropped the newest lines instead.)
The console control structure is modified in a sorta
backwards-compatible way, so that new readers can continue to work with
old console buffers and vice versa. When an old reader reads a new
buffer that has already once overflowed (i.e. is operating in true ring
buffer mode) it will print lines out of order, but it will at least
still print out the whole console content and not do any illegal memory
accesses (assuming it correctly implemented cursor overflow as it was
already possible before this patch).
BUG=chromium:651966
TEST=Rebooted and confirmed output repeatedly on a Kevin and a Falco.
Also confirmed correct behavior across suspend/resume for the latter.
Change-Id: Ifcbf59d58e1ad20995b98d111c4647281fbb45ff
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18301
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When console input driver registers itself, perform flush of input
buffer to avoid interpreting any stale key presses before libpayload
is run.
keyboard.c: Remove the redundant buffer flush.
8250.c: Ensure that serial_hardware_is_present is set before call to
add input driver.
BUG=b:37273808
TEST=Verified that any key presses in serial console before payload is
up do not have any effect after the payload starts running.
Change-Id: I46f1b6715ccf6418f5b2c741bf90db2ece26a60d
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19345
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
CBGFX currently doesn't support portrait screens at all. This will have
to be fixed eventually but might take a bit of effort. As a first step
to make devices with a portrait panel somewhat usable, this patch will
just force a square canvas on these panels and keep the bottom part of
the screen black.
Also switch set_pixel to calculate framebuffer position via
bytes_per_line instead of x_resolution. This is supposed to be the
canonical way to do that and may differ in cases where the display
controller requires a certain alignment from framebuffer lines.
Change-Id: I47dd3bf95ab8a7d8b7e1913e0ddab346eedd46f1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19279
Tested-by: build bot (Jenkins)
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
SeaBIOS 1.10.2 was released on February 28th, 2017 [1][2] with the
changes below.
```
$ git log --oneline rel-1.10.1..rel-1.10.2
5f4c7b1 QEMU fw_cfg: Write fw_cfg back on S3 resume
c45ca70 QEMU fw_cfg: Add functions for accessing files by key
31b6229 QEMU fw_cfg: Add command to write back address of file
aa7219d romfile-loader: Switch to using named structs
2a1d88c QEMU DMA: Add DMA write capability
d2ac564 ps2port: Disable keyboard/mouse prior to resetting ps2 controller
b0e3c67 vgasrc: Increase debug level
ca3ab93 ahci: Set upper 32-bit registers to zero
```
This fixes the problem on a Lenovo X60, that the keyboard is not
initialized by SeaBIOS when for example loaded from GRUB.
[1] https://www.seabios.org/Releases#SeaBIOS_1.10.2
Change-Id: Idc078ffa896b2e105faabd2d8befeaf9a2a0b6ac
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/19290
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Update from commit 124af94f - Fri Feb 26, 2016
(skylake boards: unconditionally re-enable 8254 PIT for legacy)
To commit eb583fa8 - Wed Mar 29, 2017
(rk3399_sdhci: Reintroduce PHY power-cycling at 52MHz)
This brings the stable version of depthcharge forward by 325 commits.
Change-Id: I31b3235df6d36409ff1b365e6adb6852281df097
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/19220
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Update from commit 2afd66eb - Fri Jul 29, 2016
([pixbuf] Enable PNG format by default)
To commit fd6d1f46 - Fri Mar 31, 2017
([thunderx] Use ThunderxConfigProtocol to obtain board configuration)
This moves the stable iPXE commit forward 144 commits.
Change-Id: Ia0c97f863be39632c9206ca95b3857047fc37e26
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/19221
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This adds a gru libpayload config, that should fit all gru-based
devices such as kevin.
As gru-based devices are CrOS devices, select the associated config
to enable CrOS-specific features.
Change-Id: I6e79b763fc497c126612b8786a669a33b57ea29f
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/19137
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Enable the USB during the initialization of tint. Without it USB
keyboards don't work, which makes this payload pointless on
systems where a PS/2 keyboard port isn't available.
Based on I98f0ccdb19d6b195572941cf87ce3221f57db7c5 (tint and
nvramcui: enable USB, update tint to 0.04+nmu1 with changes) [1]
[1] https://review.coreboot.org/17507/
Change-Id: Iaa8dfac0301ef19a2d76a0975d025b00e7f3807b
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/18766
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
We have found a non-compliant USB hub (RealTek RTS 5413) that does not
set a port's Connect Status Change bit on its USB 3.0 half if the port
had already been connected while the hub was being reset. To work around
this bug, this patch adds code to initially request the status of every
port after a hub was enumerated, clear the Connect Status Change bit if
set, and then enumerate the port iff it is currently connected,
regardless of whether the change bit was set. A similar behavior can
also be found in the Linux kernel.
BRANCH=oak
BUG=b:35929438
TEST=Booted Elm with this change, my USB 3.0 sticks enumerate now even
if they had been plugged in since boot.
Change-Id: I8a28252eb94f005f04866d06e4fc61ea265cee89
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18729
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Enable the USB during the initialization of nvramcui. Without it
the USB keyboards don't work, which makes this payload pointless
on the systems where a PS/2 keyboard port isn't available.
Based on https://review.coreboot.org/#/c/17507/
Change-Id: I04697c5f582b41e6f6ffe98955bf59f4fe57f66e
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/18765
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Allows to use SSE and floating point in payloads without digging to
much into x86 assembly code.
Tested on Lenovo T500 (Intel Core2Duo).
Both floating point operation and SSE is properly working.
Change-Id: I4a5fc633f158de421b70435a8bfdc0dcaa504c72
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18345
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Since version 9332965 "serialio: Support for mmap serial ports", SeaBIOS
supports memory mapped serial ports. This patch automatically configures
SeaBIOS when the Hudson UART is enabled.
Change-Id: I072f6a957df7e143d790783546b0725bcd597d9c
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-on: https://review.coreboot.org/18025
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This change is based on the following commit:
3aa91dc payloads/seabios: Add "git revision" to the SeaBIOS version menu
Change-Id: I9987e3673e70b5cb20173d1ddff6060f42a5374a
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/18352
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
This adds an oak libpayload config, that should fit all oak-based
devices such as elm.
Change-Id: Iabb71404ff84029a5976371a353e8c92e781ca1f
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/18447
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
Configure GRUB to build with boot time statistics. That allows users
to add that module to GRUB by adding `boottime` to the list of extra
modules.
Change-Id: I76a07e49aecb37652fe8c7d6a9421fd464424287
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/18367
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Some simple implementation of the MultiBoot protocol may not pass a
memory map (MULTIBOOT_FLAGS_MMAP missing in the flags) but just the two
values for low and high memory, indicated by the MULTIBOOT_FLAGS_MEMINFO
flag.
Support those kind of boot loaders too, instead of falling back to the
hard-coded values in lib_get_sysinfo().
Tested with a multiboot enhanced version of FILO.
Change-Id: I22cf9e3ec0075aff040390bd177c5cd22d439b81
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: https://review.coreboot.org/18350
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Implement the argc/argv passing as described in coreboot’s payload API:
http://www.coreboot.org/Payload_API
While at it, give the code some love by not needlessly trashing register
values.
Change-Id: Ib830f2c67b631b7216843203cefd55d9bb780d83
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: https://review.coreboot.org/18336
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Simplify the code by directly using the arguments on the stack as base
pointer relative memory references, instead of loading them into
intermediate registers first.
Make it more robust by preserving all callee saved registers mandated by
the C calling convention (and only those), namely EBP, EBX, ESI and EDI.
Don't assume anything about the register state when the called function
returns -- beside the segment registers and the stack pointer to be
still the same as before the call.
Change-Id: I383d6ccefc5b3d5cca37a1c9b638c231bbc48aa8
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: https://review.coreboot.org/18335
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
According to coreboot’s payload API [1], the called payload should be
able to return a value via %eax. Support this by changing the prototype
of start_main() and pass on the return value of main() to the caller
instead of discarding it.
[1] https://www.coreboot.org/Payload_API
Change-Id: I8442faea19cc8e04487092f8e61aa4e5cba3ba76
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: https://review.coreboot.org/18334
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
According to coreboot’s payload API [1] the argc value should be passed
at stack offset 0x10, so we need to push a dummy value to comply to the
API.
[1] https://www.coreboot.org/Payload_API
Change-Id: Id20424185a5bf7e4d94de1886a2cece3f3968371
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: https://review.coreboot.org/18333
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The pointer to write the return value to is in %ecx, not %eax. Writing
to (%eax) leads to memory corruptions as %eax holds the return value,
e.g. would write zero to address zero for a "successful" returning
payload.
Change-Id: I82df27ae89a9e3d25f479ebdda2b50ea57565459
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: https://review.coreboot.org/18332
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
According to coreboot’s payload API [1] the magic value passed to the
payload should be 0x12345678, not 12345678. Fix that.
[1] https://www.coreboot.org/Payload_API
Change-Id: I10a7f7b1a4aec100416c5e7e4ba7f8add10ef5c5
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: https://review.coreboot.org/18331
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change depthcharge to not require a board-specific config file for
libpayload. If the Kconfig option is selected, use the settings
in libpayload/configs/defconfig instead.
Change-Id: I4fd1a5915472f28e757c62f3f2415716f1fdfc71
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/18271
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Add the capability for specifying which version of depthcharge to
checkout and build. This is similar to the existing feature for
SeaBIOS.
The depthcharge makefile already contains some structure for checking
out master vs. stable however the calling Makefile.inc ingored this
feature. Add the command-line variable assignment for these, along
with a tree-ish for any revision.
Change-Id: I99a5b088cb0ebb29e5d96a84217b3bfa852de8ac
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/18270
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Depending on the commit to build, depthcharge may have a different
target name (depthcharge vs. depthcharge_unified). Add some logic
to determine which name should be used based on the commit ID
being requested.
Change-Id: I05b853934d13696f4bd0d79d53ff6c5f59096d1c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/18269
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Drop the _unified moniker from the depthcharge build. The payload
and coreboot have drifted out of sync and there is no longer a
non-unified depthcharge.
This patch corresponds with the depthcharge change:
https://review.coreboot.org/cgit/depthcharge.git/commit/?id=74a0739
Change-Id: I8d028b14d2eee63dfdc9d3dd63695f1c58ea7984
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/18268
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
The SeaBIOS and coreboot log levels don't really align, so setting the
SeaBIOS log level to the same as coreboot's isn't really what we want.
- Update default log level to use the default SeaBIOS log level.
- Update the current help text to match the new defaults.
- Add help text for what is displayed at various levels.
- Get rid of separate type & prompt lines.
- Add comments for default seabios level & logging disabled
Change-Id: I5a8b75bd44748cb94a83a77ac3a379c8a9587e7b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18210
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kevin O'Connor <kevin@koconnor.net>
When .xcompile doesn't already exist, building libpayload fails because
the CC variable (et al) remain empty since .xcompile is only included
after the variables coming from there are evaluated.
Change-Id: I73f1cbced95afcff15839604fea5fd05d81bc3d3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/18228
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Make the code C89 compatible, which doesn’t allow loop initial
declarations. Older compilers use C89 by default, so just declare the
variable outside.
Change-Id: I3c5a8109e66f7a25687f4e4b2c72718d74276e04
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/18196
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
It takes a long time for no gain: We don't need to update the
submodules, we don't need to fetch the revision, we don't need to find
the compilers, when all we want to do is to manipulate the .config file
or clean the build directory.
Change-Id: Ie1bd446a0d49a81e3cccdb56fe2c43ffd83b6c98
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/18182
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Power button events are usually dropped because the button is not in
the keyboard matrix range. Add condition to forward it like other keys.
BUG=chrome-os-partner:61275
BRANCH=None
TEST=reboot and make sure power button selection
in depthcharge's detachable menus is processed on reef.
Change-Id: I86897fa8d73a56533ef62bba05458ac3d339237e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 25654e214f0ab8685d445ced62612a02be851126
Original-Change-Id: I516a0043bd7730789728d5c5498d0a0f30a2acac
Original-Signed-off-by: Shelley Chen <shchen@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/428199
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://review.coreboot.org/18177
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
This enables USB HID support in the veyron config, since it seems to
work correctly and is needed for interaction with depthcharge on devices
without an embedded keyboard (such as veyron_mickey).
Change-Id: Icae829e3a132005df17bcb6f7e6f8a190912576d
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/17930
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
Previously SeaBIOS's default was used (1). This patch defaults to
coreboot's console level instead which is approximately the same
verbosity as SeaBIOS and thus what a user would probably expect.
Change-Id: If79e5f40c9380bb527f870eeb7d0cb43faf00beb
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/18051
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Currently we just disabled ohci interrupts when calling ohci_shutdown,
Which would not actually shutdown the ohci controller, for example it
may still written the increased HccaFrameNumber to Hcca buffer.
Perform a soft reset to ohci controller as the linux kernel ohci-hcd
driver does.
BUG=chrome-os-partner:60996
BRANCH=None
TEST=Checked on gru, no more "BUG: Bad page state" error in kernel.
Change-Id: I128ab6ba455ac5383a4d48be0bc12b8bb4533464
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4749fc82fdd1b74ca3f2ed3fdf0ef53a5e161087
Original-Change-Id: I3f192aea627ba2fa69533bc0a4270466ca18f2a7
Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/426338
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://review.coreboot.org/18125
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
BUG=chrome-os-partner:56947
TEST=Verifed country code can be parsed from VPD in depthcharge.
BRANCH=None
Change-Id: I2fbbd4a784c50538331747e1ef78c33c6b8a679b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: acea6e2a200e8bd78fd458255ac7fad307406989
Original-Change-Id: I4616fefc6a377d7830397cdadb493927358e25cc
Original-Signed-off-by: Kan Yan <kyan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/425819
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/18124
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This updates the configuration for ARM CrOS devices (nyans and veyrons)
by using the CHROMEOS Kconfig option, thus reducing the number of
options to select. It also brings proper serial console support.
Change-Id: Iffc84c44a1d339c5bb575fbaffc40bc2d56bb6cf
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/17928
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Changes since SeaBIOS 1.9.3
Release 1.10.0:
* Initial support for Trusted Platform Module (TPM) version 2.0
* Several USB XHCI timing fixes on real hardware
* Support for "LSI MPT Fusion" scsi controllers on QEMU
* Support for virtio devices mapped above 4GB
* Several bug fixes and code cleanups
Release 1.10.1:
* Updates for QEMU for reproducible builds
Change-Id: I465700307d72fa44b6900b38b332603ea505ed09
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/18026
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
This fixes the generic timer driver to get the current tick from the
high register, so that comparison with the high count value (obtained
previously from the same register) has a chance to succeed.
Change-Id: I5ce02bfa15a91ad34641b8e24813a5b7ca790ec3
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/17929
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Coverity considers this a copy&paste error, and maybe it is. In any
case, it makes sense to check the variable that (if the condition is
true) is changed, and the values are the same before that test, so the
change is harmless.
Change-Id: I163c6a9f5baa05e715861dc19643b19a9c79c883
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1347376
Reviewed-on: https://review.coreboot.org/17837
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Coverity erroneously complains that we call wmove with x or y == -1,
even though our copy of that function properly checks for that.
But: setsyx is documented to always return OK (even on errors), so let
it do that. (and make coverity happy in the process)
Change-Id: I1bc9ba2a075037f0e1a855b67a93883978564887
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1260797
Reviewed-on: https://review.coreboot.org/17836
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Coverity complains and that (unfortunately) means that some compiler
might take advantage of the same fact.
Change-Id: I59aff77820c524fa5a0fcb251c1268da475101fb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1261105
Reviewed-on: https://review.coreboot.org/17835
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
MAX_ARGC_COUNT limits the payload to ten parameters which is not
enough when used with a proprietary first stage bootloader providing
hardware description using around 20 parameters.
This patch makes the libpayload able to get up to 32 parameters.
Change-Id: I49925040d951dffb9c11425334674d8d498821f2
Signed-off-by: Jeremy Compostella <jeremy.compostella@gmail.com>
Reviewed-on: https://review.coreboot.org/17467
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
On QEMU using SeaVGABIOS breaks some bootloaders, e.g. ISOLINUX does not
work and GRUB works but is forced in txtmode, instead of graphical mode.
Change-Id: If31d4e5ed19cbeed3f8f9dbc23cc738dd55986e5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17122
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The STABLE build of FILO does not build anymore with the
current HEAD of coreboot. However, the current HEAD of FILO
does build with the current HEAD of coreboot. Update FILO
STABLE to FILO HEAD.
Change-Id: I4eece3aaada0dfdf4da106d5d260b5b361537558
Signed-off-by: Kevin Paul Herbert <kph@platinasystems.com>
Reviewed-on: https://review.coreboot.org/15195
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG should only occur together with
MAINBOARD_HAS_NATIVE_VGA_INIT. It seems to be used to just have to have
the option to be able to select SEABIOS_VGA_COREBOOT.
This patch makes these boards use MAINBOARD_DO_NATIVE_VGA_INIT and
MAINBOARD_HAS_NATIVE_VGA_INIT to have it select SEABIOS_VGA_COREBOOT
by default when SeaBIOS is chosen.
Change-Id: If0a36af1883a3d62b16a61483733be981a85e5e2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16981
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Chrome OS builds always have some inherent differences to "standard"
libpayload configurations: they don't want to use curses or things like
storage drivers, they always use the coreboot framebuffer and USB, etc.
This patch reintroduces CONFIG_LP_CHROMEOS as an option that only
affects Kconfig defaults. This allows Chrome OS builds to select most of
what they need in one go and reduces board-specific .config files to
only the options that are really specific to that board.
Also restricts the 8250_SERIAL_CONSOLE Kconfig to only default to yes on
x86 boards, which probably makes sense for all of libpayload (some but
far from all ARM boards use 8250-compatible UARTs, and we should
probably not default a platform option unless it's going to be correct
with very high probability).
BRANCH=None
BUG=None
TEST=Built and booted Jerry and Oak.
Change-Id: Ie0c0593ffd399608d2cbfb83d20891f6f1864914
Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Id: e558f59
Original-Change-Id: I609637cd2ea7dfb4558aa3c04c90b64038c9ab57
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/347970
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17024
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Currently every non-x86 platform supported by libpayload needs to
provide its own timer driver. Most of the ones we have accumulated there
look almost identical: For the frequency, return a preset constant. For
the value, read a 32-bit register, possibly read another 32-bit register
and shift+OR it with the previous one, then return that.
Let's replace this with a single .c file that can easily handle all of
those cases. Menuconfig convenience can still be maintained by providing
several presets that select different defaults for the driver's
configuration options (register address(es) and frequency).
Removes an "enabled" check from Samsung MCT driver since coreboot always
unconditionally enables that timer anyway.
CQ-DEPEND=CL:344809
BRANCH=None
BUG=None
TEST=Booted Oak and Veyron, observed how dev-mode delay was still ~30s
Change-Id: I61cb7d2ffd4902aa841c57f9afa9cd991f770acd
Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Id: a036af6
Original-Change-Id: I9784e7c6aa5abd6d92478ea7ec1cf42c9a437546
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/347749
Reviewed-on: https://review.coreboot.org/17023
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This enables viewing more than ~20 files in the file list on the left.
Arrows are added to indicate that more items are available off-screen.
This mimics what was done in pci_module.
Change-Id: Idd1363e1abe98ba51c795879db061cc54808da8e
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/14546
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Raul E Rangel