Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SMI handler was not present in jasperlake rvp to handle wake events
when platform goes to sleep or shutdown or s0ix.
Adding this support for board which supports chromeec.
BUG=None
BRANCH=None
TEST=Check wake event on board and platform wakes up due to events
lid wake event or power button press.
Change-Id: I8e35955b06d6efaf9275ec03f519c9bcaa9ba345
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
This replaces GPLv2-or-later and GPLv2-only long form text with the
short SPDX identifiers.
Commands used:
perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.*of.*the.*License.*or.*(at.*your.*option).*any.*later.*version.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-or-later */|s' $(cat filelist)
perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist)
perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation[.;,].+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist)
perl -i -p0e 's|/\*[*\n\t ]*This software is licensed under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation,.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist)
Change-Id: I7a746088a35633c11fc7ebe86006e96458a1abf8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Also split "this is part of" line from copyright notices.
Change-Id: Ibc2446410bcb3104ead458b40a9ce7819c61a8eb
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
That makes it easier to identify "license only" headers (because they
are now license only)
Script line used for that:
perl -i -p0e 's|/\*.*\n.*This file is part of the coreboot project.*\n.*\*|/* This file is part of the coreboot project. */\n/*|' # ...filelist...
Change-Id: I2280b19972e37c36d8c67a67e0320296567fa4f6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Kernel pinctrl driver changed for Tiger Lake and went to old scheme.
Kernel patch: https://chromium-review.googlesource.com/c/chromiumos/
third_party/kernel/+/2116670
BUG=b:151683980
BRANCH=none
TEST=Build and boot tgl board. In /sys/kernel/debug/pinctrl
verify INTC34C5:00 listing all the pins.
Cq-Depend:chromium:2116670
Change-Id: I9f1d399ff7380125ad5b935f9590a7d9cc442b04
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39801
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch configures all IP related GPIOs as per mainboard schematics.
Till now, we were relying on FSP to do IP specific GPIO programming but
now we'll program all GPIOs from mainboard.
This will remove ambiguity of GPIO programming done by FSP and coreboot
will do full GPIO programming
Programming GPIOs of following IPs
- I2C
- Emmc
- Display
- CPU specific gpio (SLP lines)
- Cnvi
- SD
BUG=None
BRANCH=None
TEST=compile coreboot and checked that all IP functionality working.
Change-Id: I98583b768cbd8ab4af536b31d758cb1cee93edfb
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.
In order to make it easier to review, this change is being split into
multiple CLs. This is change 3/5 which basically is generated by
running the following command:
$ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g'
BUG=b:155428745
Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
These parameters were found to work fine for 2-socket configuration,
for FSP based on tag 16.D.21.
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: I466a7f2951ef307036ddaed0be0aacf98dd2710f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This CL selects the PcieRpClkReqDetect for the required root ports
which is needed to allow proper clksrc gpio configuration.
Also, sets the unused PcieClkSrcUsage to 0xFF.
BUG=None
BRANCH=None
TEST=Build and boot jslrvp with NVMe
Change-Id: Ie4ae1365a7621b8be3b795798c171e3f7ea9e487
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
This format of PCH GPIOs configuration, unlike the raw DW0 and DW1
registers values from the inteltool dump, is more understandable and
makes the code much cleaner. The gpio.h file with PAD_CFG macros was
automatically generated using the util/intelp2m [1] utility:
./intelp2m -p lbg -file cedarisland/vendorbios/inteltool_gpio.log
According to the documentation [2], the Host Software Pad Ownership
register only affects the pads that are configured as input. The
intelp2m utility takes this into account when converting macros and
ignores bits from this register for the corresponding pads.
[1] https://review.coreboot.org/c/coreboot/+/35643
[2] Intel Document Number: 549921
Change-Id: Id671a9021a8313d8c3359b89c2934b929bcab1a4
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40736
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We should be sure that after romstage the pads will be configured
according to the config from gpio.h only. This patch sets the GPIO
configuration from gpio.h using the soc/intel/common/gpio.c driver
again in ramstage.
[1] https://review.coreboot.org/c/coreboot/+/40730
Change-Id: Ic49e504d96fe4fd44434e7b981f8d8d9e76880ef
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
According to changes in the soc/xeon_sp code [1,2], server motherboards
with Lewisburg PCH can use the soc/intel/common/gpio driver to configure
GPIO controller. This patch adds pads configuration map, which has the
format required by the GPIO driver. The data for this was taken from the
inteltool register dump with vendors firmware. The gpio.h file with pad
configuration was generated automatically using the util/intelp2m [3]:
./intelp2m -raw -p lbg -file cedarisland/vendorbios/inteltool_gpio.log
[1] https: //review.coreboot.org/c/coreboot/+/39425
[2] https: //review.coreboot.org/c/coreboot/+/39428
[3] https: //review.coreboot.org/c/coreboot/+/35643
Change-Id: I90b91e6dbf8c65c747d0e0d94c61023e610f93ab
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
.write_acpi_tables() should not be updating the device structure. This
change makes the struct device * argument to it as const.
Change-Id: I50d013e83a404e0a0e3837ca16fa75c7eaa0e14a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
We need to configure GSPI related gpios for external EC and TPM.
Along with GSPI configuring gpios for LAN (power down), FSP_INT
and PCH_INT.
BUG=None
BRANCH=None
TEST=External EC card works and LAN is powered down.
Change-Id: I1f2d32537b56802d0631a94590a6ebe156c5cdd0
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40362
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1)Change Mainboard Part Number to jslrvp
2)Change Mainboard Family to Intel_jslrvp
3)Generate SMBIOS table and fill sku id information in SMBIOS
BUG=None
BRANCH=None
TEST=Mosys works on jslrvp and Sku ID info is generated
Change-Id: Iad0b394fea017223a5b98fff0cb4c2bd1d5a7bd7
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40011
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The WDB (Write Data Buffer) is a data region in CAR, used as a
scratchpad in the read and write training algorithms of memory
initialization. Both SNB and IVB use this buffer, but HSW does not.
Unlike earlier chipsets, Haswell contains much more in-hardware memory
training machinery, known as REUT (Robust Electrical Unified Testing).
Among other changes, the REUT hardware has a pattern storage buffer,
which renders the need for a pattern storage buffer in CAR obsolete.
Deprecate the WDB-related parameters in the pei_data structure for
Haswell, as they are leftovers from the previous generation's MRC.
Remove them from the mainboards, and explain why they are not required.
Because the MRC ABI has to remain the same, the layout of pei_data must
not be changed, so rename the WDB parameters instead of deleting them.
Tested on Asrock B85M Pro4, still boots with the MRC from Google Wolf.
Change-Id: I7acc9353a22f8c6f9fe6407617162f35849a79dd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Enable Wifi and Bluetooth for Jasper Lake RVP with following changes:
1. Enable related pci root ports for WLAN and BT
2. Disable unused root ports and clkreq for unused clocks
3. Configure GPIOs properly for M.2 port
BUG=None
BRANCH=None
TEST=Code compiles and able to detect Wifi/BT module on board.
Change-Id: Ifbd07022c05769c04ecd49c81a4430947125b32a
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39933
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
M.2 WWAN interface has GPIOs which requires coreboot to
configure all related GPIOs as per board schematics.
BUG=None
BRANCH=None
TEST=code compiles and WWAN device is detected in OS
Change-Id: I8ad978a619b50e16ad754177f1eb05cf7670b79f
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Remove explicit setting of iDisp Link parameters. These settings are
related to configuration for the link between HD-Audio controller and
Display unit for purposes of HDMI/DP Audio playback. During PO,
observed that without setting these params display part was not
binding. With the latest code verified that we dont need to explicitly
set these parameters anymore. HDMI/DP audio playback works fine with
default settings.
BUG=b:151451125
BRANCH:none
TEST= build and boot volteer/ripto and verify HDMI/DP audio playback
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ie003d119918d363e2ff9172936b70416fd73c7f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40263
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jairaj Arava <jairaj.arava@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The weak definition of board_id() in coreboot_table.c returns a
uint32_t, so update this function to match. This fixes a compiler error
when using LTO.
Change-Id: I6ad03ecedcf4a4d9f0c917cdc760f81ddde06d11
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Guckian
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Remove extra USB port entry because it came in from copy
patch from the previous board and configure USB over-current
pins as per JSLRVP.
Change-Id: If9df8e330d31ed81207dfdfa2ab96fd4d49f3f0c
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39403
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=b:151166040
TEST= build and boot volteer and check LTR and AER value
from FSP log
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I8ab7667d788563ffcb9287a64254590ef9bea5d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40269
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable audio for Jasper Lake RVP board. It has 2 Audio codec chips
connected on I2C0: DA7219 and MAX98373
1. Enable Kconfig to enable I2C drivers for both chips.
2. Make necessary devicetree changes to enable FSP UPDs and ACPI entry
for I2C0.
3. Enable audio related GPIO configurations.
BUG=None
BRANCH=None
TEST=Checked that dmic and speaker are functional on Jasper Lake RVP
Change-Id: Ibf76eb36c478bd33cbc0c86099236452b397fcc5
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39695
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I1ea2eebfdd43610e42b4cf04409ec76c2e8b0042
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40082
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These two identifiers were always very confusing. We're not filling and
injecting generators. We are filling SSDTs and injecting into the DSDT.
So drop the `_generator` suffix. Hopefully, this also makes ACPI look a
little less scary.
Change-Id: I6f0e79632c9c855f38fe24c0186388a25990c44d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39977
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: David Guckian
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change reorganizes memory initialization code for LPDDR4x on
TGL to allow sharing of code when adding support for other memory
types. In follow-up changes, support for DDR4 will be added.
1. It adds configuration for memory topology which is currently only
MEMORY_DOWN, however DDR4 requires more topologies to be
supported.
2. spd_info structure is organized to allow mixed topologies as well.
3. DQ/DQS maps are organized to reflect hardware configuration.
TEST=Verified that volteer still boots and memory initialization is
successful.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ib625f2ab30a6e1362a310d9abb3f2051f85c3013
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Switch to using Jasper Lake SoC code from soc/intel/jasperlake and stop
referring from soc/intel/tigerlake.
Addtionally mainboard changes are done to support build.
BUG=b:150217037
TEST=Build and boot waddledoo. Build jasperlake_rvp and volteer board.
Change-Id: I39f117bd66cb610a305bcdb8ea65332fd0ff4814
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
In order to create a working baseline all ports are being set to have
retimers. Setting the TcssAuxOri UPD to 0 in order for the SoC to not
misconfigure the ports. Volteer will need some additional changes after
this is implemented to account for ports that do not have a retimer.
This setting is in the process of being documented in the TGL EDS and we
can update once it is fully understood what this setting is changing on
the SOC side.
BUG=b:145943811
BRANCH=none
TEST=Boot to OS and check Type-C port1 Display on Volteer,
Connecting Type-c display should work regardless of Type-c cable
orientation.
Change-Id: I29eb0513299126ad8d1ee11ded2c771f28ad13f3
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39460
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use it wherever the standard numbers were copied to. Bit 31 is set
at runtime unconditionally, so we don't need it here.
Change-Id: I0d853c3b8250a2c7b2d1a91985a555e4b17ad76c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39731
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Just a minimal set of board files needed to get it to boot
in 1 CPU mode.
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: Ie2f944964e938d8026a6d5d8a22a8449199d08aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
