Commit Graph

44778 Commits

Author SHA1 Message Date
Sean Rhodes c9bc7a7591 util/lint: Fix linters to work with coreboot-configurator
* Exclude .gif files from newline checking
* Exclude coreboot-configurator from checkpatch checking

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1b07b7b05340409e5c1695cc7bbdea68f8190097
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2021-11-19 13:34:55 +00:00
Meera Ravindranath 98e827ea74 mb/intel/adlrvp: Enable CPU PCIe RP 2
Disabling CPU PCIe RP 2 (commit:3fd39467b Fix S0ix regression)
causes regression in NVMe boot on ADL-P RVP boards.

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0b8b76a5537d8b80777cb7588ce6b22281af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59392
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-19 06:21:21 +00:00
Sean Rhodes d58599dcb8 drivers/fsp: Rewrite post code hex values in lowercase
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I65a83fcd69296f13c63329701ba9ce53f7cc2cb3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-18 23:33:58 +00:00
Rob Barnes 188be6b270 mb/google/guybrush: Add variant_tpm_gpio_table
Add separate gpio table for TPM i2c and interrupt. Remove TPM gpios from
early_gpio_table. This allows for initializing TPM gpios separately from
other gpios.

BUG=b:200578885
BRANCH=None
TEST=Build and boot guybrush

Change-Id: I51d087087b166ec3bb3762bc1150b34db5b22f2f
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59083
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-18 23:33:15 +00:00
Eric Lai eae7bf2327 mb/google/brya/var/felwinter: Correct USB3 TCSS setting
Based on Intel Kit#615686, USB3 only needs to disable TBT and DMA per
port. And if uses USB3 directly you need to set TcssAuxOri accordingly.

BUG=b:206716691,b:205235144
TEST=USB function work as expected at USB3 only sku.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I303d042d6c80194ff48130fe4e9c04b49ca13ee8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-18 23:32:43 +00:00
Mark Hsieh 88295c35cc mb/google/brya/var/gimble: Include 2 new SPDs
Add SPD support to gimble for LPDDR4 memory part MT53E1G32D2NP-046 WT:B
and MT53E512M32D1NP-046 WT:B.

BUG=b:191574298
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Id3fc35605675b953bf993a29f35140f7721eedab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59299
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-18 23:32:22 +00:00
Wisley Chen da815303a3 mb/google/brya/var/redrix: De-assert SSD PERST# in romstage
After CB:57539 applied, it can support romstage GPIO table override.
We can move SSD PERST# de-assertion to romstage.

The reason for this is to give enough time after PERST#
deassertion so that the SSD has enough time to initialize before
the FSP scans the RPs for downstream devices.

BUG=b:199714453
TEST=build

Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I242cb1517f564d9d135d523b1e7f95ac34d601f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-18 23:31:58 +00:00
Wisley Chen cd04c6e07d mb/google/brya/var/redrix: Correct WWAN power sequence
Correct the WWAN power sequence to meet spec

BUG=b:206079177
TEST=build

Change-Id: Ibba1ecc04b563ae4eedd7596594f33812cbac150
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-18 23:31:40 +00:00
Wisley Chen e589ee3879 mb/google/brya/var/redrix: Configure Acoustic noise mitigation
Enable Acoustic noise mitigation for redrix and set slew rate to 1/8

BUG=b:204009588
TEST=build and verified by power team

Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I0fc0bb68c4de6fca60ee290eb46a77200d748ca8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-18 23:31:21 +00:00
Wisley Chen c510346b08 soc/intel/alderlake: Add Acoustic noise mitigation UPDs
This patch expose the following FSP UPD interface into coreboot:
- AcousticNoiseMitigation
- FastPkgCRampDisable
- SlowSlewRate

BUG=b:204009588
TEST=build

Change-Id: I0b9c18f9b40d30525028e64754dd1dc86c3b2ec6
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-18 23:31:04 +00:00
Zheng Bao 570645dc2a amdfwtool: Call the set_efs_table for Stoneyridge
Related to https://review.coreboot.org/c/coreboot/+/58555
commit-id: 35b7e0a2d82ac
In 58555, we added the SOC ID for Stoneyridge in amdfwtool
command line. But it raised building error because it then called
"set_efs_table" without setting SPI mode. So we skipped calling that.

But in set_efs_table, it has case for Stoneyridge. The boards also
need to have this setting. So we remove the skipping and give the
proper SPI mode in mainboard Kconfig.

Change-Id: I24499ff6daf7878b12b6044496f53379116c598f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-18 23:29:48 +00:00
Zheng Bao 6e2c5a3d18 amdfwtool: Set flag comboable as bool type
Fix the CL:
https://review.coreboot.org/c/coreboot/+/58942
The type comboable was int but set as true.

Change-Id: Id2c43378735c089a27a5aa683b55a0f7ec3677de
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-18 23:28:59 +00:00
Zheng Bao b749d3f0d2 amdfwtool: Add a union for combo and psp directory
For combo layout, this is for combo header.
For non-combo layout, this is for PSP directory.

Change-Id: Ie7b5aec6b511ad61972908d1d22a13aeb7dd73a9
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-18 23:28:47 +00:00
Jonathan Zhang b846b42a36 doc/mb/ocp: update Delta Lake documentation
Update Delta Lake document following the publish of OCP blog
and the Wiwynn press release.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I3eaa765bf9918988b4b5cb01e8607a5c27b9bd17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-11-18 12:31:26 +00:00
Eric Lai 3feddeb398 mb/google/brya/var/felwinter: Add MT53E1G32D2NP-046 WT:B SPD
Add MT53E1G32D2NP-046 WT:B SPD.

BUG=b:205669003
TEST=Boot up without issues.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If084a8af941b36a8f3f608271078e32b093d9108
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17 23:46:03 +00:00
Matt DeVillier 9afe02798a mb/google/cyan: use shared touchpad/touchscreen interrupts
Windows (10/11) freaks out and generates an interrupt storm
if two ACPI devices are enabled and share an interrupt, even
when only one device is actually present. To mitigate this,
mark Cyan's touchpad/touchscreen interrupts as SharedAndWake
rather than ExclusiveAndWake.

Test: build/boot Windows 10 on Relm, observe normal CPU
usage in Task Manager for System Interrupts task when
touchpad/touchscreen in use.

Change-Id: I09bc878318f9fa6252f65a42ad46109418805fa0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17 23:45:50 +00:00
Tim Wawrzynczak f6c53c0543 security/vboot: Use default kernel secdata size
When fetching antirollback information for the kernel, it is not always
known ahead of time what the current size of the kernel secdata area
is. If the incorrect size is passed, the TPM will return back the
correct size, but at the cost of an extra transaction; when using cr50
over I2C, this can be as much as 20ms. Currently, the first attempt uses
the minimium size (aka version 0 or 0.2), and if another size is used
(which is the case for all modern cr50-based boards, version 1 or 1.0),
then a transaction is wasted on every boot.

Therefore, change the default size sent to the TPM to be the default one
used in the VB2 API instead of the minimum one.

BUG=b:201304784
TEST=verify TPM initialization time drops by ~20ms. Also the Kernel NV
Index is read correctly in the BIOS logs.

src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

 504:finished TPM initialization                       99,953 (65,606)

Change-Id: I22d9c0079bb1175f24ff7317d116e79aa5ba08ed
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-17 23:05:21 +00:00
Karthikeyan Ramasubramanian 2e445ad1af security/tpm/tcg-2.0: Handle TPM_RC_NV_RANGE return code
As per the TPM spec, if offset and the size field of data add to a value
that is greater than the dataSize field of the NV Index referenced by
nvIndex, the TPM shall return an error (TPM_RC_NV_RANGE). Handle the TPM
error and map it to an appropriate vboot error.

BUG=None
TEST=Build and boot to OS in Guybrush.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I8b403e2f33cc1368065cc21f73df1102695f73eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-17 23:05:11 +00:00
Zanxi Chen e1095496e1 mb/google/trogdor: Adjust mipi panel backlight gpio
According hareware design, mipi panel backlight relies on
AP_BKLTEN(GPIO_12) and TP_EN(GPIO_85). Meanwhile, TP_EN(GPIO_85)
needs pull up to enable PP3300_DISP_ON before AP_BKLTEN(GPIO_12) up.

BUG=b:197709288,b:199081803,b:205166230
BRANCH=trogdor
TEST=emerge-strongbad coreboot

Change-Id: Ie9920e5366f6b1ea9e0da228bd211317516b390a
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-17 18:50:37 +00:00
Joey Peng 0087de817a mb/google/brya/var/taeko: Correct touchpad GPE settings
Correct GPE settings so touchpad can wake up DUT.

BUG=b:206526991
TEST=emerge-brya coreboot and builds without error

Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I1978e9220ad7a275d351ad5eeff7036131926b24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17 18:44:16 +00:00
Joey Peng fcb267a81d mb/google/brya/var/taeko: disabled autonomous GPIO power management
Used H1 firmware where the last version number is 0.0.22, 0.3.22 or
less to production that will need to disable autonomous GPIO power
management and then can get H1 version by gsctool -a -f -M

BUG=b:205315500
TEST=emerge-brya coreboot and test that DUT can boot to OS.

Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Ib26797fa2d4d0b1a6eb28c5d79b9ac0a6054abd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17 18:44:05 +00:00
Maulik V Vaghela 85d9f47014 Revert "soc/intel/adl: Drop SGPM, RGPM and EGPM methods"
This reverts commit 1399442289.

Reason for revert:
Some Cr50 chips with old firmware version (x.y.22) don't support
long pulse interrupt command, requiring dynamic GPIO PM to be disabled
to intercept short pulse interrupt.

Due to this coreboot needs to expose SGPM, RGPM and EGPM ACPI methods
to support power gating of GPIO communities from the kernel when dynamic
GPIO PM is disabled.

BUG=b:204832081
BRANCH=None
Test= S0ix works with dynamic PM disabled.

Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Change-Id: I2b5b00878062f8a499641d7a47db54ed078cd6cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-11-17 15:54:10 +00:00
Casper Chang d16a085110 mb/google/brya/variants/primus: Correct SSD power sequence
SSD sometimes can't be detected in in warm/cold boot stress.
M.2 spec describes SSD_PERST# should be sequenced after power enable.

BUG=b:199967106
TEST=SSD was always discovered in warm/cold boot stress.

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I74c21cd96cf1c4518c4ed7c0b3b39e915b6b1ff7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17 14:32:48 +00:00
Boris Mittelberg 5c3d12eaee mb/google/brya: Enable early EC sync
Enable VBOOT_EARLY_EC_SYNC in corebot

BUG=b:201356952
BRANCH=None
TEST=Tested on Brya id 2

Signed-off-by: Boris Mittelberg <bmbm@google.com>
Change-Id: I6e480d64a5d90d5bb9cf59ed60b7b53af9edf46a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17 14:32:31 +00:00
Matt DeVillier f9df79e8d6 mb/google/hatch: Add VBTs for variants
Add VBTs for all hatch variants currently supported by
ChromeOS recovery images. For variants which use multiple
VBTs and select at runtime, ensure these are added directly
to CBFS.

Change-Id: I3c62ce204e3272e778ba0a34f7a47a65d8125f53
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17 14:32:10 +00:00
Matt DeVillier f347166928 mb/google/hatch: Alphabetize variants in Kconfig.name
Change-Id: Ie29242e635bae1e2754bc1109754a64cb496af29
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17 14:31:40 +00:00
Eric Lai 6296ae0258 mb/google/brya: Move typeC AUX configuration to variant
TypeC AUX configuration is variant specific. So move into variant level.

BUG=b:205235144
TEST=No typeC port 0 AUX in felwinter.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I02bfea462cf4c6359fd8d5cca4368786ee03bc8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17 14:31:23 +00:00
Kevin Chiu a592bef03f mb/google/guybrush: Update SPKR GPIO configuration for guybrush/nipperkin
For Guybrush Board Version 2, Nipperking Board Version 1,
update SPKR GPIO to match H/W schematic:
SPKR: GPIO31

For Nipperkin Board Version 2, update SPKR GPIO to
match H/W schematic:
SPKR: GPIO70

BUG=b:202992077
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage

Change-Id: I3d82292b116f53d85d9518364ffd2169bd915a7e
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59051
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-17 14:30:34 +00:00
Rob Barnes 847a39fec7 soc/amd/psp_verstage: Split up verstage_soc_init
Make psp verstage initialization more granular be splitting
verstage_soc_init into separate functions. Specifically, create
soc init functions for espi, i2c spi, and aoac.

BUG=b:200578885
BRANCH=None
TEST=Build and boot guybrush

Change-Id: I489889a0dfd4016aa4f2b53a2c6a7a1ea4459e60
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-11-17 14:30:01 +00:00
Matt DeVillier 1a4b132413 mb/google/octopus: Add missing VBTs for variants
Add VBTs for all octopus variants currently supported by
ChromeOS recovery images. For variants which use multiple
VBTs and select at runtime, ensure these are added directly
to CBFS.

Change-Id: I4b5c4268f9255d658f9762d94488db66e0677830
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17 14:28:46 +00:00
Matt DeVillier e08df8e138 mb/google/octopus: Alphabetize variants in Kconfig.name
Change-Id: I2e57c4f1baa8a42bde2642e7f76ddead7bfd6a58
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17 14:27:47 +00:00
Matt DeVillier a952b3f794 mb/google/slippy/peppy: use shared touchpad interrupts
Windows (10/11) freaks out and generates an interrupt storm
if two ACPI devices are enabled and share an interrupt, even
when only one device is actually present. To mitigate this,
mark Peppy's interrupts as Shared rather than the default
of Exclusive.

Test: build/boot Windows 10 on Peppy, observe normal CPU
usage in Task Manager for System Interrupts task when
touchpad in use.

Change-Id: Ida78ddec3105cef6581cdde78da2e2c97d983a0a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17 14:27:32 +00:00
Werner Zeh 98c7d55eaa mb/siemens/mc_ehl1: Send POST codes to NC FPGA via PCI
This board does not have a LPC or eSPI connection to the NC FPGA anymore
and therefore IO port 0x80 is not useable for POST codes anymore. Enable
the feature of sending the POST codes to the NC FPGA via PCI so that the
POST codes are visbile again in coreboot.

Change-Id: I9043e4ec9a2ad6b946e373bb3dce9da3d42d00d1
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-11-17 14:27:03 +00:00
Werner Zeh 42b8835beb drivers/siemens/nc_fpga: Add POST code over PCI
So far POST codes were mapped on IO port 0x80 inside the NC FPGA which
was connected via the LPC bus to the host CPU. On recent x86 generations
the LPC bus was replaced with eSPI and not all Siemens boards have the
eSPI routed to the NC FPGA. In order to have POST codes visible on those
boards the display is accessible via PCI in addition.
This patch adds the feature of sending the POST codes to the NC FPGA via
a PCI mapped register.

Change-Id: Ie15686de49cface17830365d78fe7c54cce183a0
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-11-17 14:26:47 +00:00
Julius Werner 57d4bc63f0 cbfs: Add helper functions to look up size and type of a file
This patch adds cbfs_get_size() and cbfs_get_type() helper functions
(and _ro_ variations) to look up the size or type of a CBFS file without
loading it. Generally, use of these should be discouraged because that
tends to mean that the file needs to be looked up more than once, and
cbfs_alloc() or cbfs_type_load() are usually the more efficient
alternative... but sometimes they're unavoidable, so we might as well
offer them.

Also remove the <cbfs_private.h> header which had already become sort of
unnecessary with previous changes. cbfs_boot_lookup() is now exported in
<cbfs.h> for use in inlines, but should not be used directly by other
files (and is prefixed with an underscore to highlight that).

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I8092d8f6e04bdfb4df6c626dc7d42b402fe0a8ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
2021-11-17 12:46:25 +00:00
Yuchen Huang 9a640c0f69 soc/mediatek/mt8186: Add RTC and clkbuf drivers
Add support for RTC and clkbuf.

TEST=boot to kernel and check log ok
BUG=b:202871018

Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com>
Change-Id: Ia02a74f685feb2466c113a77cbfa3a7d8fedb595
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-17 10:31:32 +00:00
Chun-Jie Chen c7e17bce06 soc/mediatek/mt8186: Add mtcmos init support
Add mtcmos to support display and audio.

TEST=build pass
BUG=b:202871018

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Change-Id: Ib9d41d47f235376f524c3ff78f1fcc069cbc60cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-17 10:31:23 +00:00
Rex-BC Chen ad5fda5fbf mb/google/corsola: Initialize SPM
Initialize SPM (System Power Management) in RAM stage.
This adds 55ms to the boot time.

TEST=program counter of SPM is correct value(0x250) after booting up
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I822417f7a679107760b202dd43fb79d1934940bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-17 10:31:14 +00:00
Rex-BC Chen bade5caedb soc/mediatek/mt8186: add SPM loader
This patch adds support for loading SPM firmware from CBFS to SPM SRAM.
SPM needs its own firmware to enable SPM suspend/resume function which
turns off several resources such as DRAM/mainpll/26M clk when linux
system suspend.

TEST=program counter of SPM is correct value(0x250) after booting up
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia13e5a2ecf09561856b7e958128cd2f045c39f33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59341
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-17 10:31:04 +00:00
Rex-BC Chen d8e8c873c0 soc/mediatek/mt8186: initialize SSPM
SSPM is "Secure System Power Manager" that provides power control in
secure domain. The initialization flow is to load SSPM firmware to
its SRAM space and then enable.

TEST=build pass
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I92eb501a1e48dd02d2f94ff392933261e6a42391
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-17 10:30:51 +00:00
Rex-BC Chen 15486f44a2 soc/mediatek: move MSDC drivers to soc folder
Setting of MSDC is defined by soc, so we move them to soc folder.

TEST=emerge-cherry coreboot; emerge-asurada coreboot

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I84ad8a4cde120c97024870ebf750d44b36c2284d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-17 10:30:27 +00:00
Edward-JW Yang e3964c75d7 soc/mediatek/mt8186: Enable DCM
DCM (dynamic clock management) can dynamically slow down or gate clocks
during CPU or bus idle. Enable DCM settings on the MT8186 platform.

TEST=build pass and check register ok
BUG=b:202871018

Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com>
Change-Id: I82add5ae629d59f7d6773e26ac9cba9d54ab8caf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-17 10:30:17 +00:00
Housong Zhang 7c14ff0261 soc/mediatek/mt8186: Add I2C driver support
Add I2C controller drivers.

TEST=build pass
BUG=b:202871018

Signed-off-by: Housong Zhang <housong.zhang@mediatek.corp-partner.google.com>
Change-Id: Ia3800e3a30b0796a64213d3b1ab688580c6ddbca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-17 10:30:06 +00:00
Rex-BC Chen 9d321588d0 soc/mediatek: move i2c function to common folder
Move mtk_i2c_max_step_cnt, mtk_i2c_check_ac_timing, mtk_i2c_speed_init
and mtk_i2c_calculate_speed to common folder to share with MT8186.

TEST=test on tomato ok
TEST=emerge-asurada coreboot
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I4a702741c763bf9261cea90d0d71c08b6e28c261
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-17 10:29:55 +00:00
Subrata Banik e2cc773f71 soc/intel/../thermal: Fix return type of `pch_get_ltt_value()`
This patch modifies the pch_get_ltt_value() function return type from
uint16_t to uint32_t to accommodate platforms with more than one thermal
threshold.

For example: Alder Lake PCH Trip Point = T2L | T1L | T0L
where T2L > T1L > T0L.

BUG=b:193774296

Change-Id: I5f46ccb457b9cfebf13a512eabb3fb0fab8adb39
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-11-17 08:47:21 +00:00
Bora Guvendik db85b096d4 mb/intel/adlrvp: Fix sagv point3 clipping to 4800Mhz
Update board type to 4 as per MRC team's input. This
fixes LP5 sagv point 3 being clipped from the expected
5200Mhz to 4800Mhz.

TEST=Boot to OS, verify frequency locked.

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I9472aec41537425c1ed648b949f484939ee9ff99
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17 00:35:59 +00:00
Reka Norman 86a9cdd589 util/mb/google: Change comments in memory Makefile.inc templates
Begin comments with # instead of ## to match the Makefile.inc generated
by spd_tools.

BUG=None
TEST=None

Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: If2d716a7338fd5af8216b2bcd894fc88a9df137e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17 00:35:36 +00:00
Meera Ravindranath 3fd39467b5 mb/intel/adlrvp: Fix S0ix regression
The following changes are needed to fix S0ix regression on RVP
1) Disable Clk src 3
2) Disable Ext FIVR settings

TEST=Boot adlrvp to OS, confirm S0ix is working.

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0b8b76b5527d8b80776cb7588ce6b12281af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-11-17 00:35:18 +00:00
Malik_Hsu df99e57289 mb/google/brya/variants/primus: enable ALC5682I-VS
In next phase build, the audio codec will change to ALC5682I-VS

BUG=b:205883511
TEST=emerge-brya coreboot chromeos-bootimage and check audio function

Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I5906ef9bb88da7fe450a986bf7dd1ee701227f95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17 00:34:41 +00:00
Raul E Rangel b25576fa63 src/lib/prog_loaders: Add preload_ramstage
This will enable preloading ramstage. By preloading the file into
cbfs_cache we reduce boot time.

BUG=b:179699789
TEST=Boot guybrush to OS and see 12ms reduction in boot time.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ibe12de806449da25bc0033b02fcb97c3384eddc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-16 21:45:36 +00:00