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26164 Commits

Author SHA1 Message Date
Stefan Reinauer 0502b7a64c fix buildrom statement if there's only one romimage specified. 
roms always needs to be an array.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1143 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-26 11:40:05 +00:00
Stefan Reinauer dfe7d53a09 ignore target temp build dir 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1142 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-26 10:07:13 +00:00
Stefan Reinauer 261f2bb70a add cvsignore files for target files. Use gcc -m32 to build on AMD64 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1141 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-26 10:03:47 +00:00
Stefan Reinauer 63afbd4fdc ignore temp. build directory 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1140 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-26 09:53:38 +00:00
Stefan Reinauer 5e837b7791 get rid of pointer/int cast warnings on 64bit. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1139 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-26 09:47:41 +00:00
Ronald G. Minnich c817926a6b via epia; also yh lu tyan. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1138 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-26 04:45:52 +00:00
Ronald G. Minnich 10941401e8 allow default settings in the mainboard file 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1137 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-25 23:03:18 +00:00
Ronald G. Minnich 3ff7bdaad7 new from yh lu 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1136 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-25 22:04:19 +00:00
Ronald G. Minnich 1621e9303c new from tyan 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1135 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-25 22:04:04 +00:00
Ronald G. Minnich 6e71aec6cd no default rom size 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1134 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-25 17:35:30 +00:00
Ronald G. Minnich ca34c040e5 ROM_SIZE has no default now. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1133 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-25 17:34:56 +00:00
Ronald G. Minnich 57cef6590b added via vt8231 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1132 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-25 17:21:57 +00:00
Ronald G. Minnich 2b664dd0a0 first cut at 8601 support 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1131 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-25 17:01:28 +00:00
Stefan Reinauer c22465fc49 add another compat chain keepalife fix 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1130 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-25 13:39:53 +00:00
Stefan Reinauer 71e3c9ab15 khepri resource map update to keep compatibility chain 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1129 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-25 13:37:00 +00:00
Stefan Reinauer bb79b0efb8 remove last occurence of AMD8111_DEV 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1128 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-25 12:54:55 +00:00
Stefan Reinauer 0fff41e261 new target configuration: newisys khepri 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1125 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-23 22:44:12 +00:00
Stefan Reinauer 71e481d24e update hypertransport setup for khepri 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1124 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-23 20:02:02 +00:00
Stefan Reinauer a2241c821a fix hypertransport setup for quartet. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1123 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-23 18:51:28 +00:00
Stefan Reinauer 9719cce5a3 make coherent ht setup capable of non-standard link configurations 
(i.e. with CPU1 not connected to ACROSS link of CPU0)


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1122 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-23 18:50:35 +00:00
Stefan Reinauer dcdbdfb46e first shot of legacybios emulation. 
does not work yet.. sorry :-(


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1119 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-18 14:16:08 +00:00
Stefan Reinauer 59549598c0 fix romcc compiling 32bit code on amd64 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1118 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-17 12:18:40 +00:00
Stefan Reinauer e27b08d41c add filename to buildrom 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1117 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-17 12:17:58 +00:00
Stefan Reinauer ed10c390ad add filename to buildrom command 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1116 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-17 11:05:29 +00:00
Stefan Reinauer 0a5f865a27 add cvsignore file 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1113 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-12 12:39:04 +00:00
Stefan Reinauer bcb9f858e5 add "clean" target 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1112 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-12 12:35:18 +00:00
Stefan Reinauer 57398af2a4 update Config.lb and add khepri ht chain 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1111 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-11 13:53:29 +00:00
Stefan Reinauer 1bb45d5a42 add quartet and dspace targets, disable reboot in Solo target. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1110 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-11 11:55:18 +00:00
Stefan Reinauer 79249e3dbc add new target for DSPACE DS1006 card, make quartet auto.c all verbose 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1109 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-11 11:53:15 +00:00
Stefan Reinauer 5282cd0875 remove old config files, adopt to new config method. fix resource map (?) 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1107 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-09 13:30:58 +00:00
Stefan Reinauer dad60489d5 automatically build config.py if it's not there. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1104 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-08 15:01:19 +00:00
Stefan Reinauer 9714894d4f add solo target config file for new config method 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1103 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-08 14:17:24 +00:00
Stefan Reinauer 75d42640d5 update SOLO code (untested but compiling and pretty much complete!?!) 
drop old configuration method.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1102 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-08 14:03:50 +00:00
Eric Biederman ff0e8465e8 - Include hypertransport.h in hypertransport.c 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1101 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-04 03:00:54 +00:00
Eric Biederman 6638755a23 - Remove dead argument to hypertransport_scan_chain 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-04 01:25:55 +00:00
Greg Watson 481b5688b5 moved init_timer() to static initialization 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-03 21:30:18 +00:00
Stefan Reinauer f72ff36e76 cosmetics 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1098 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-03 12:09:44 +00:00
Eric Biederman 0ac6b41e70 - 1.1.4 
Major restructuring of hypertransport handling.
  Major rewerite of superio/NSC/pc87360 as a proof of concept for handling superio resources dynamically
  Updates to hard_reset handling when resetting because of the need to change hypertransport link
    speeds and widths.
    (a) No longer assume the boot is good just because we get to a hard reset point.
    (b) Set a flag to indicate that the BIOS triggered the reset so we don't decrement the
       boot counter.
  Updates to arima/hdama mptable so it tracks the new bus numbers


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1097 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-02 17:16:48 +00:00
Eric Biederman e9a271e32c - Major update of the dynamic device tree so it can handle 
* subtractive resources
  * merging with the static device tree
  * more device types than just pci
- The piece to watch out for is the new enable_resources method that was needed in all of the drivers


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1096 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-02 03:36:25 +00:00
Eric Biederman d4c14524f5 - Update the version number to 1.1.2 and update the NEWS file 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1095 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-01 23:47:37 +00:00
Eric Biederman 30e143a5f0 - Add back in the hard reset code from the freebios1 tree. 
This allows generic code to reset the box.
- Update the hypertransport code to automatically calculate link
  widths and freequencies, and to call hard_reset if neecessary for
  the changes to go into effect.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1094 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-01 23:45:32 +00:00
Eric Biederman 9bdb460a97 - Updates to config.g so that it works more reliably and has initial support 
for paths
- Renamed some configuration variables
  SMP -> CONFIG_SMP
  MAX_CPUS -> CONFIG_MAX_CPUS
  MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS
- Removed some dead configuration variables
MAX_CPUS -> CONFIG_MAX_CPUS
MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS
SMP -> CONFIG_SMP
FINAL_MAINBOARD_FIXUP
SIO_BASE
SIO_SYSTEM_CLK_INPUT
NO_KEYBOARD
USE_NORMAL_IMAGE
SERIAL_CONSOLE
USE_ELF_BOOT
ENABLE_FIXED_AND_VARIABLE_MTRRS
START_CPU_SEG
DISABLE_WATCHDOG
ENABLE_IOMMU
AMD8111_DEV

- Removed some assembly files that are no longer needed
killed src/southbridge/amd/amd8111/smbus.inc
killed src/southbrideg/amd/amd8111/cmos_boot_failover.inc
killed src/ram/ramtest.inc
- Updates to config.g so that it works more reliably and has initial support
  for paths
- Renamed some configuration variables
  SMP -> CONFIG_SMP
  MAX_CPUS -> CONFIG_MAX_CPUS
  MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS
- Removed some dead configuration variables
MAX_CPUS -> CONFIG_MAX_CPUS
MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS
SMP -> CONFIG_SMP
FINAL_MAINBOARD_FIXUP
SIO_BASE
SIO_SYSTEM_CLK_INPUT
NO_KEYBOARD
USE_NORMAL_IMAGE
SERIAL_CONSOLE
USE_ELF_BOOT
ENABLE_FIXED_AND_VARIABLE_MTRRS
START_CPU_SEG
DISABLE_WATCHDOG
ENABLE_IOMMU
AMD8111_DEV

- Removed some assembly files that are no longer needed
killed src/southbridge/amd/amd8111/smbus.inc
killed src/southbrideg/amd/amd8111/cmos_boot_failover.inc
killed src/ram/ramtest.inc
killed src/sdram/generic_dump_spd.inc
killed src/sdram/generic_dump_spd.inc

- Updated the arima/hdama to build with the new configuration system
- Updated config.g to list all of the variables with make echo


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-09-01 23:17:58 +00:00
Ronald G. Minnich 0e97fe3904 more targets 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1092 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-08-29 03:02:00 +00:00
Ronald G. Minnich b4b031cd44 new targets 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1091 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-08-29 03:00:49 +00:00
Stefan Reinauer b980e39c81 add first bunch of newisys khepri files. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1090 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-08-28 17:23:15 +00:00
Stefan Reinauer f4440e65a4 more motherboard specific cleanups 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-08-28 15:08:43 +00:00
Stefan Reinauer f5f10d1097 cleaning out motherboard specific changes from the generic directories. 
Moving tyan resource map to tyan directory. Making IOMMU for hammer choosable
via ENABLE_IOMMU


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1088 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-08-28 13:43:03 +00:00
Ronald G. Minnich fa2df758f2 support for new mobos and fixes 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1087 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-08-27 14:33:13 +00:00
Ronald G. Minnich bee6575d7c fixed irq tables for hdama 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1086 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-08-26 13:28:50 +00:00
Stefan Reinauer 235c254563 more quartet fixes 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1085 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2003-08-07 14:11:08 +00:00