Commit Graph

39994 Commits

Author SHA1 Message Date
Patrick Georgi 157f9f567b docker/coreboot-sdk: clone coreboot submodules when doing test build
Change-Id: I2315beda31bdc8edc92d21b6665eb5ebd07da2e6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-01-28 09:27:36 +00:00
FrankChu d22f256e03 mb/google/dedede/var/galith: Add Wifi SAR for convertibles
Add wifi sar for galith
Using convertible mode of fw config to decide to load custom wifi sar or not.

BUG=b:176206495
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage.

Cq-Depend: chromium:2649378,chrome-internal:3559387
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I0f9a7ddedef550317da4bf798317619ffd1fa979
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-28 09:27:11 +00:00
Subrata Banik ac8c357ddc mb/intel/adlrvp: Configure SATA DEVSLP as per latest schematics
1. GPP_E5 =>  Remove unused GPIOs
2. GPP_H12, GPP_H13 => Program the correct Native Functions for GPIO

Change-Id: I588a8c1153eaa1bf818a081c6c5d18a669017d95
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-28 09:26:48 +00:00
Elyes HAOUAS 316466b765 mb/google/parrot: Convert to ASL 2.0 syntax
Change-Id: Ie802b540cea13000227c969bbc262f034d1b6b84
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-28 09:26:03 +00:00
Zheng Bao db11fa46ad soc/amd/common: Handle I2C resource only if base address is defined
Change-Id: I767ad58f442bc5561bda4dd1de2d9593c8434615
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-01-28 09:25:52 +00:00
Yidi Lin ef5c235541 mb/google/asurada: Improve boot time by raising little CPU frequency
Raise little CPU to 2GHz at romstage to improve boot time.

BUG=b:177389446
TEST=observe boot time by `cbmem`
     Before: 1,062,359 us
     After: 907,458 us

Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: I723a916d7f708627525ef11e3c5ea0b381f269aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-28 09:25:00 +00:00
Patrick Rudolph 0bea950a47 cpu/intel/microcode: Add caching layer in intel_microcode_find
Cache the found microcode for faster subsequent accesses.

Change-Id: Ic40d57964600f8f20ddb26c7d1691b043fd89f29
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49896
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28 09:23:45 +00:00
Huayang Duan 27c9fcfc48 soc/mediatek/mt8192: Implement dram all channel calibration
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: I62cc654d5a6b861f72eec66e09d24483b993f0e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-28 09:22:28 +00:00
Yidi Lin 602943f8da soc/mediatek/mt8192: Add mt6315_romstage_init
Initialize pmif_arb in romstage.

BUG=b:177389446

Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: I3ffe7277c9ecb04269c832693d42799ba1711384
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-28 09:21:52 +00:00
Weiyi Lu 8dfeb06eb1 soc/mediatek/mt8192: Add function to raise the CCI frequency
Implement mt_pll_raise_cci_freq() in MT8192 to raise the CCI frequency.
Usage: mt_pll_raise_cci_freq(1400UL * MHz);

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: I084cd7888b1dcfdeaef308b8bb3677d034497a30
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-28 09:21:39 +00:00
Seunghwan Kim e9fed766df mb/google/dedede/var/sasuke: Configure GPP_G7 as native
Configuring GPP_G7 as NC causes SD card detection issue on sasuke.
So we'd like to remove the GPP_G7 override and keep the baseboard
configuration as native function (SDIO_WP).

BUG=b:175831709
BRANCH=firmware-dedede-13606.B
TEST=Built and verified SDR104 SD card operation on sasuke

Change-Id: If73337b482f04fd263caaa6fed0e54aa87bd876e
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-28 09:19:20 +00:00
Angel Pons 73c967665b bayhub bh720: Factor out common HS200 init code
Except for one debug print in sarien, both functions are identical.
Move them to driver code to avoid unnecessary redundancy.

Change-Id: I82635a289e3c05119eab4ee1f7a6bf3a8a1725c1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-01-28 09:18:18 +00:00
Frans Hendriks a4ecf9654e drivers/elog: Correct code style
lint report errors

Solve the POINTER_LOCATION errors

BUG = N/A
TEST = N/A

Change-Id: I65926abd6bbaff1efce39efad9ec92c4f364b533
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49971
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28 09:18:00 +00:00
Frans Hendriks 9d732d3462 cpu/intel/common/fsb.c: Correct code style
lint report warning

Solve the RETURN_VOID

BUG = N/A
TEST = N/A

Change-Id: I3b8088494049b5c3244531a4a77af4153edbdff4
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-28 09:17:52 +00:00
Frans Hendriks e5aafb6fbe cpu/amd/agesa/family15tn/fixme.c
lint report errors and warnings

Solve the next issues:
- BRACES

BUG = N/A
TEST = N/A

Change-Id: I27a712ec93c216fc3aa836baa53d6e2f2e68d3a3
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-01-28 09:17:40 +00:00
Yu-Ping Wu aafa1621e1 mb/google/asurada: Add config for spherion
BUG=b:178440482
TEST=emerge-asurada coreboot
BRANCH=none

Change-Id: Ica09b73f97509db065c93c6be757c0d77c9b7a87
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-01-28 09:17:23 +00:00
Elyes HAOUAS a2c4cd7e08 mb/emulation/qemu-i440fx: Convert to ASL 2.0 syntax
Generated 'build/dsdt.dsl' files are identical.

Change-Id: I9157d9fc61339792dbbc45e82e1cb04fa51c6aae
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46077
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28 09:16:58 +00:00
Elyes HAOUAS 6245d076b9 mb/emulation/qemu-q35: Convert to ASL 2.0 syntax
Generated 'build/dsdt.dsl' files are identical.

Change-Id: I4e0f64def6c4c712793d3b2ede99dd74f9046fcb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46163
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28 09:16:49 +00:00
Wayne3_Wang fda6e6f305 mb/google/volteer: Add GL9755 support to Drobit
Add the GL9755 support to drobit and also fixes the S0ix can't into C3~C9 problem

BUG=b:174348200
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot

Signed-off-by: Wayne3_Wang <Wayne3_Wang@pegatron.corp-partner.google.com>
Change-Id: I52df6b2cdebfaf8a5eb010c4af1a2cf3d918f5e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49921
Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Reviewed-by: Paul2 Huang <paul2_huang@pegatron.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28 09:16:27 +00:00
Eric Lai a0f68cd8d3 mb/google/brya: Add variants overridetree.cb path and remove unused registers
Add variants overridetree.cb path remove unused registers

BUG=b:174266035
TEST=Build Test

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I2940332044aa4c2de6d58f5d0d2a2a7c1b2c3478
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-28 09:16:12 +00:00
Shiyu Sun 000ee73e8c mb/google/zork: add MST details to trembyle devicetree
Added device hid info to the MST RTD2141b device on
trembyle.

BRANCH=zork
BUG=b:147402710
TEST=Build and flash BIOS image, see 10EC2141 appears
under /sys/bus/i2c/devices

Signed-off-by: Shiyu Sun <sshiyu@chromium.org>
Change-Id: I97a67f9dbc31cd788d579252d7d355b24d97ca30
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
2021-01-28 09:15:46 +00:00
Marc Jones e3b18bf63d soc/intel/xeon_sp/skx: Add soc_acpi_name
Add the soc_scpi_name to the soc pci_ops. This is used by ACPI table
generation and required by the intel common XHCI device.

Change-Id: Idc09d53f14dfb1e42f904dfd4e87e8c09e155135
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
2021-01-28 09:15:15 +00:00
Tim Crawford fdc8fd3602 mb/system76/oryp5: Add System76 Oryx Pro 5
Tested with TianoCore payload (UefiPayloadPkg).

Working:

- PS/2 keyboard, touchpad
- Both DIMM slots
- Both NVMe ports
- SATA port
- All USB ports
- Webcam
- Ethernet
- Integrated graphics
- Internal microphone
- S3 suspend/resume
- Flashing with flashrom
- Booting to Ubuntu Linux and Windows

Not working:

- Discrete/Hybrid graphics
- Internal speakers

These two require new drivers to work correctly, which will be added and
enabled later.

Change-Id: Iae6e530dcd52df3642cdfe74b65bfff5aa0dd402
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-28 09:15:00 +00:00
Tim Chu 1ee8ddc484 arch/x86/smbios: Update SMBIOS type 16 Extended Maximum Capacity
Update Extended Maximum Capacity field in SMBIOS type 16 so that
maximum dimm size can be over 2TB.

Tested=Execute "dmidecode -t 16" to check maximum capacity is over 2TB.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I61901c815f9d0daae102e5077a116c0de87240ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-01-28 09:14:32 +00:00
Jakub Czapiga 7435e254d4 acpi/acpigen.c: Remove unused and incorrect functions
acpigen_write_name_zero() and acpigen_write_name_one() are not
implemented correctly, and are not used anywhere. Drop them in
favor of the more flexible acpigen_write_name_integer() function.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I116fd41624a8e8b536d18d747f21d3131b734dfc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-28 09:10:28 +00:00
Kyösti Mälkki ade4f3520b ACPI: Move include for <vc/google/chromeos.asl>
Change-Id: I4356a8bda71e84afe8c348d366479c5006bf2459
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49796
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28 08:59:54 +00:00
Kyösti Mälkki ae7ac8a723 ACPI: Separate ChromeOS NVS in ASL
For builds with MAINBOARD_HAS_CHROMEOS=y but CHROMEOS=n, there
is reduced dsdt.aml size and reduced GNVS allocation from cbmem.

More importantly, it's less error-prone when the OperationRegion
size is not hard-coded inside the .asl files.

Change-Id: I54b0d63a41561f9a5d9ebde77967e6d21ee014cd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49477
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28 08:59:11 +00:00
Kyösti Mälkki fa5f9b5aff ACPI: Declare GNVS variables globally
There is a common place where acpigen generates these,
so the declarations for the OperationRegions should be
centralized too.

Change-Id: I772492ca9e651b60244c565d1e926dc2ad33cfd8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49795
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28 08:58:13 +00:00
Kyösti Mälkki e76ce871c8 arch/x86: Remove most C_ENV_BOOTBLOCK_SIZE limits
With top-aligned bootblock this is no longer globally needed.
The default maximum is now a generous 256 KiB with couple
platforms having lower limits of 32 KiB and 64 KiB.

Change-Id: Ib1aee44908c0dcbc17978d3ee53bd05a6200410c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-28 08:55:31 +00:00
Kyösti Mälkki 49dbbe99c2 arch/x86: Top-align .text in bootblock
Move .text section closer to .init. This reduces the size
of the flat bootblock binary and footprint in CBFS.

Change-Id: I64325bd633e1104853cfb928c7f801d94ff3045a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-28 08:54:50 +00:00
Kyösti Mälkki 2289a70b6f arch/x86: Top-align .init in bootblock
Link .init section near the end of bootblock program.
It contains _start16bit, gdtptr and gdt that must be
addressable from realmode, thus within top 64 KiB.

Change-Id: If7b9737650362ac7cd82685cfdfaf18bd2429238
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-28 08:54:21 +00:00
Kyösti Mälkki 6c7441f5e6 cpu/x86: Rename __protected_start symbol
It was confusing to have this defined while there was another
symbol bootblock_protected_mode_entry that was not really used
as an entry point.

Change-Id: I3da07ba9c0a9fc15b1515452adfb27f963659951
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48404
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28 08:53:30 +00:00
Kyösti Mälkki 47d58e5df0 cpu/x86: Link entry32.inc
Change-Id: Ib475f40f950f8cc54f0e3c50a80970ba3d2b628f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-28 08:53:07 +00:00
Kyösti Mälkki 404c0c455c cpu/x86: Link reset16.inc
Change-Id: If2caab67286cf77e37928e03be4f581070e771d8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47968
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28 08:52:35 +00:00
Kyösti Mälkki 0308313e07 cpu/x86: Link entry16.inc
Change-Id: I78ecd15716169b58cf6696ff8c5069ac2d5038ef
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47967
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28 08:51:40 +00:00
Kyösti Mälkki 952e6b1ef8 soc/intel: Refactor acpi_wake_source()
Change-Id: I44cb499260fdd0ea37308909a24cdf5ca1afa025
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49879
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28 08:48:07 +00:00
Kyösti Mälkki f67e67510b soc/intel: Refactor fill_acpi_wake()
Change-Id: I7fcc2b36cfe57adf8ae3a6acf8b54e19504202a5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49878
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28 08:47:47 +00:00
Subrata Banik 1476f6992a mb/intel/adlrvp: Remove ClkReq assignment for RP8
CLKSRC6 for RP8 is free-running CLK hence ClkReq is not required.

TEST=Able to detect PCIe SD card over x1 slot.

Change-Id: I550d5be9cc7566708b0b86fcd1da833bc4bc828f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-01-28 04:09:39 +00:00
V Sowmya 1b8906a529 mb/intel/shadowmountain: Add flash layout
This patch adds the flash layout for shadowmountain.

BUG=b:175808146
TEST=util/abuild/abuild -p none -t intel/shadowmountain -a -c max

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I7073d9c783684051e33e7a33eca50007d286bb00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-01-28 03:11:35 +00:00
Raul E Rangel c3d7846a33 soc/amd/picasso/acpi: Fix PCI0 MMIO window
The PCI0 MMIO window was defined between TOM and 4 GiB. This was
overlapping with the FCH MMIO devices. The first MMIO device after TOM
is the FCH IOAPIC.

This wasn't causing a problem for linux other than the fact that
/proc/iomem showed all the MMIO devices under the PCI root bridge.
On Windows this was causing all the MMIO devices to have conflicting
resource errors.

BUG=b:175146875
BRANCH=zork
TEST=Boot linux and verify peripherals all work. Boot windows and
verify the i2c controllers show up. The GPIO controller still has a
problem related to power.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Idc409f1318e6da5a693ccbb3da74aafd13f1e058
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49853
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28 00:29:52 +00:00
Kangheui Won ac7ec27e5c soc/amd/picasso: fix CBFS MCACHE on Zork
Zork platform was not booting with MCACHE enabled since psp_verstage
had following issues with MCACHE.
Fix all the issues and re-enable MCACHE for Zork.

* psp_verstage should call vboot_run_logic, not verstage_main.
vboot_run_logic calls after_verstage which handles RW MCACHE build.

* It should avoid low-level apis for cbfs access.
cbfs_map will build RO MCACHE if it's the first stage, while other
low-level apis won't.

* It should call update_boot_region before save_buffers
MCACHE should be transferred to x86 so we should build it before
calling save_buffers

BUG=b:177323348
BRANCH=none
TEST=boot Ezkinil

Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I08c5f8474600a06e3a08358733a38f70787e944a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49468
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28 00:26:47 +00:00
Raul E Rangel 892a423de8 soc/amd/picasso/acpi: Remove DMA addresses for UARTs
This is not the correct way to specify the FixedDMA devices. I'm
removing for now since it adds confusion.

BUG=none
BRANCH=zork
TEST=Boot zork to linux and make sure UART still works

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I17b9c8dbe4f9c4b64ee1bd69cb9b30998e727632
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-28 00:24:33 +00:00
Felix Held 613f9fc91f soc/amd/cezanne/chip: add empty SoC device operations
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic6321223b3b4b8d27ac696fdeeec75fd4bd1e6bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49952
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28 00:16:55 +00:00
Felix Held c963499791 soc/amd/cezanne: compress FSP binaries in CBFS
Compressing the FSP binaries in CBFS reduces the load time.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0faf9a3937e4a5027eba6327a51060025971450f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49951
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28 00:16:05 +00:00
Felix Held 58dfc6c479 Revert "mb/amd/mandolin: Clean up IRQ numbers"
This reverts commit 2a1638a9ce.

The original commit broke Mandolin and with the revert applied, I can
boot into Linux via SeaBIOS again.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7024b6ff1e772bbc89f810c766655a5887ed8b41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49950
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28 00:15:55 +00:00
Clay ffa033e13a superiotool: Add ID for Nuvoton NCT6797D
Test Result:
clay@clay-MS-7C37:~$ sudo superiotool
[sudo] password for clay:
superiotool r4.13-823-g221351f81b
Found Nuvoton NCT6797D (id=0xd451) at 0x4e

Change-Id: I1a5f962f2fd9dc479ddbbaf5e1bebea2c7c9e03f
Signed-off-by: Clay <clay.daniels.jr@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49112
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-27 23:21:10 +00:00
Angel Pons e2ec60f28b nb/intel/haswell/haswell.h: Do not include `pch.h`
Avoid indirect header inclusion, include `pch.h` where necessary.

Change-Id: I6b72976a28ffaad68bcf558c8a13b5c221070522
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-01-27 21:28:18 +00:00
Felix Held cbd5bb9cc7 soc/amd/picasso/chip: use switch/case statement in enable_dev()
The default case is only needed to make the compiler happy.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Idf54e7128f9e9d96f15ac7ab121f22621e033fac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49941
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-27 19:25:36 +00:00
Kyösti Mälkki 78f52fb7d6 soc/amd/stoneyridge: Change set_sb_nvs_final()
Change-Id: I0de8033bae8c1dcfbc6fd7655ba748a3514e74e9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-27 15:44:58 +00:00
Zheng Bao b04405ff76 soc/amd/cezanne: Add UCODE firmware to CBFS
Change-Id: I0de08b98e73c61db55ff994af00c84cf24273a98
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-27 15:43:55 +00:00