Commit Graph

35111 Commits

Author SHA1 Message Date
Patrick Georgi d906b21e2e util/release: Improve reporting of required tools
genrelnotes checks for cloc, git and rename but only reported about
needing the first two, so mention `rename` in missing message.

Change-Id: If91d759fc68760fd89b98756ac5b19ac3589c197
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-18 07:06:22 +00:00
Patrick Georgi 33e19ac619 Documentation: Fix 4.12 release notes, improve checklist
Since I seem to forget to remove "Upcoming" in the release notes
every single time, and others might as well, fix it here and also
tell future release managers to take care of that.

Change-Id: I8ffe34f25e954621bdd635e115a8b1a914df9c27
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-18 07:04:04 +00:00
Angel Pons 6aa7cca815 nb/intel/sandybridge: Use or-based logic for RANKSEL
NO_RANKSEL was introduced because it appeared less often and it did not
cause any lines to become too long. To simplify macro transmutation, add
the RANKSEL opposite and keep NO_RANKSEL as a no-op to ease replacement.

Line length limits are not for review. Breaking the lines unnecessarily
complicates search and replace operations, and wil be taken care of in
subsequent commits.

Tested with BUILD_TIMELESS=1, ASUS P8Z77-V LX2 remains unchanged.

Change-Id: I5d7aad59fc79840da7de2e9421b84834a6024eb9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40977
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18 07:03:44 +00:00
Angel Pons ca00dec624 nb/intel/sandybridge: Program IOSAV with macros
This is a temporary solution to simplify refactoring verification.
Programming a subsequence involves writing a group of four registers.
Abstract this into a "program subsequence" operation. This eliminates
register write noise, which should improve the readability of the code.
To replace the register writes with assignments to struct fields, we
would need to have the values as parameters of a single macro. So,
unroll SUBSEQ_CTRL and SP_CMD_ADDR into parameters of IOSAV_SUBSEQUENCE.

Line length limits are not for review. Breaking the lines unnecessarily
complicates search and replace operations, and wil be taken care of in
subsequent commits.

Tested with BUILD_TIMELESS=1, ASUS P8Z77-V LX2 remains unchanged.

Change-Id: I23f7706ba8a87c1c26f9d40a50b6d47dcf95106a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-05-18 07:03:22 +00:00
Angel Pons 8e66124240 nb/intel/sandybridge: Add and use BROADCAST_CH for IOSAV
We have a single IOSAV sequence that is broadcast across all channels.
Introduce the BROADCAST_CH macro, so that we can use the per-channel
register definitions. Treating all IOSAV sequence writes the same eases
the refactoring done in subsequent commits. Also, drop the broadcast
register definitions for the IOSAV commands, as they are now obsolete.

Line length limits are not for review. Breaking the lines unnecessarily
complicates search and replace operations, and wil be taken care of in
subsequent commits.

Tested with BUILD_TIMELESS=1, ASUS P8Z77-V LX2 remains unchanged.

Change-Id: I2dbb100fcad68d128e92b1bc9321fc1e53b748c9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40976
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18 07:03:02 +00:00
Elyes HAOUAS d13bd05b7a nb/intel: Const'ify pci_devfn_t devices
Change-Id: Ib470523200929868280f57bb0cc82b038d2fedf6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-18 07:02:05 +00:00
Elyes HAOUAS 2b79203bdb x86/include/arch/mmio.h: Convert to 96 characters line length
Change-Id: I93d0ef6db417904c345fe7b76730bcb70ba25089
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41361
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18 07:01:41 +00:00
Elyes HAOUAS b3162b5a38 mainboard/*/*/*.cb: Remove leading blank lines from SPDX header
Change-Id: Ia0dbf7b946d42bda11b904a9caff5a402b553b33
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-18 07:01:11 +00:00
Elyes HAOUAS 44e310bc6c mainboard/*/*/Kconfig*: Remove leading blank lines from SPDX header
Change-Id: I7089b29e881d74d31477e2df1c5fa043fe353343
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41358
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18 07:00:58 +00:00
Elyes HAOUAS c4b70276ed src: Remove leading blank lines from SPDX header
Change-Id: I8a207e30a73d10fe67c0474ff11324ae99e2cec6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41360
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18 07:00:27 +00:00
Seunghwan Kim 189e753cbf driver/i2c/max98390: Correct included file path
Fix coreboot build error with adding this driver

BUG=b:149443429
BRANCH=None
TEST=built without errors

Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I46bced77a50903c16239a5162d144697e9d704a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41389
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18 05:53:17 +00:00
Marshall Dawson 3e30c1284f 3rdparty/amd_blobs: Update with Picasso images
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ie886815ed354762ea52fd6a76169cf25576f8852
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-05-17 21:06:52 +00:00
Angel Pons 7449b625f8 sb/intel/lynxpoint/lp_gpio.h: Include stdint.h
The struct definition makes use of types defined in that header.

Change-Id: I1d989298b8bf6266905330491c136874be7f5e28
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-17 20:19:16 +00:00
Angel Pons c1c6c51ec0 drivers/xgi: Remove dead code
This was used by the now-gone Asus KFSN4-DRE mainboard. Drop it.

Change-Id: Id00c883ed0f80e7af96fdf3f6e2985dd5b227831
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-17 15:34:17 +00:00
Keith Hui 81f9ae9ff1 mb/asus/p2b: Remove variant validation guards from DSDT
With conversion to variant structure complete, remove temporary guards
inserted to help validate the move.

With this change, all P2B family boards (currently p2b and p2b-ls)
share the same S-state declarations.

TEST=No apparent ACPI regression observed on p2b-ls.

Change-Id: Ibd6e49adeae2a42800ee5bfd74b3850eb19843a5
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-17 14:19:15 +00:00
Sridhar Siricilla 99dbca381b soc/intel/common: Rename cse_is_hfs3_fw_sku_custom()
Rename cse_is_hfs3_fw_sku_custom() to cse_is_hfs3_fw_sku_lite() and
rename custom_bp.c to cse_lite.c. Also, rename all CSE Custom SKU
references to CSE Lite SKU.

TEST=Verified on hatch

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I20654bc14f0da8d21e31a4183df7a2e34394f34e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-05-17 08:33:00 +00:00
Furquan Shaikh 17b4803381 soc/intel/common/block/acpi: Mask lower 20 bits of TOLUD
Lower 20bits of TOLUD register include 19 reserved bits and 1 lock
bit. If lock bit is set, then northbridge.asl was reporting the base
address of low MMIO incorrectly i.e. off by 1. This resulted in Linux
kernel complaining that the MMIO window allocated to the device at the
base of low MMIO is incorrect:

pci 0000:00:1c.0: can't claim BAR 8 [mem 0x7fc00000-0x7fcfffff]: no compatible brw
pci 0000:00:1c.0: [mem 0x7fc00000-0x7fcfffff] clipped to [mem 0x7fc00001-0x7fcfff]
pci 0000:00:1c.0:   bridge window [mem 0x7fc00001-0x7fcfffff]

This change masks the lower 20 bits of TOLUD register when exposing it
in the ACPI tables to ensure that the base address of low MMIO region
is reported correctly.

TEST=Verified that kernel dmesg no longer complains about the BAR at
base of low MMIO.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I4849367d5fa03d70c50dc97c7e84454a65d1887a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41455
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-17 04:07:16 +00:00
Furquan Shaikh edf2c8eb55 soc/intel/common/block/acpi: Update northbridge.asl to ASL2.0 syntax
This change updates northbridge.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: If8eabb6b934b74e69cdf4e18981082028399244d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-17 04:06:03 +00:00
Furquan Shaikh 6186cbcdc7 Revert "device: Enable resource allocator to use multiple ranges"
This reverts commit 3b02006afe.

Reason for revert: Resource allocator patches need to be reverted
until the AMD chipsets can be fixed to handle the resource allocation
flow correctly.

BUG=b:149186922

Change-Id: Id9872b90482319748b4f3ba2e0de2185d5c50667
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41413
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-16 17:48:52 +00:00
Furquan Shaikh bca71f643c Revert "device: Enable resource allocation above 4G boundary"
This reverts commit 44ae0eacb8.

Reason for revert: Resource allocator patches need to be reverted
until the AMD chipsets can be fixed to handle the resource allocation
flow correctly.

BUG=b:149186922

Change-Id: I90f3eac2d23b5f59ab356ae48ed94d14c7405774
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41412
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-16 17:48:11 +00:00
Furquan Shaikh 196d8559d9 Revert "pciexp_device: Add option to allocate prefetch memory above 4G boundary"
This reverts commit dcbf6454b6.

Reason for revert: Resource allocator patches need to be reverted
until the AMD chipsets can be fixed to handle the resource allocation
flow correctly.

Change-Id: I58c9fff1a18ea1c9941e29c2c6e60e338c517c30
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
2020-05-16 17:48:04 +00:00
Furquan Shaikh 563424e986 Revert "mb/google/volteer: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports"
This reverts commit 2412924bc7.

Reason for revert: Resource allocator patches need to be reverted
until the AMD chipsets can be fixed to handle the resource allocation
flow correctly.

BUG=b:149186922

Change-Id: Iea6db8cc0cb5a0e81d176ed3199c91dcd02d1859
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41411
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-16 17:47:57 +00:00
Michał Żygowski 72f06ca554 mb/dell/optiplex_9010: Add Dell OptiPlex 9010 SFF support
Based on the autoport. The OptiPlex 9010 comes in four different sizes:
MT, DT, SFF and USFF. Tested on SFF only. The other PCBs are slightly
different, but they are designed with intercompatibility in mind. With
small devicetree overrides it should work on OptiPlex 7010 and other
OptiPlex 9010 variants as well.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I88d65cae30d08ca727d86d930707c2be25a527cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40351
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-16 17:38:46 +00:00
Michał Żygowski fba08308f0 superio/smsc/sch5545: add support for SMSC SCH5545
The SMSC SCH5545 is very similar to the publicly available
datasheet for the SCH5627.

TEST=use PS2 keyboard and mouse, serial port, runtime registers and
Embedded Memory Interface on Dell Optiplex 9010

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: If8a60d5802675f09b08014ed583d2d8afa29fc04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40350
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-16 17:37:29 +00:00
Raul E Rangel 6191b85f87 drivers/i2c/designware: Check if the device is powered
If the device doesn't return a valid component type, that means the
device is non-functional.

The dw_i2c_regs had invalid offsets for the version field. I got the
correct value from the DesignWare DW_apb_i2c Databook v2.02a. It also
matches what the Picasso PPR says.

I also print out the version field of the controller.

BUG=b:153001807
BRANCH=none
TEST=Tested on PSP where I2C is non functional. Also tested on trembyle
and verified i2c was initialized.
Saw the following in the logs
I2C bus 2 version 0x3132322a

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If5527972508e0f4b35cc9ecdb1491b1ce85ff3af
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2144540
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40870
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-15 17:32:47 +00:00
Sridhar Siricilla 6ad7010542 soc/intel: Correct comment on HMRFPO_ENABLE HECI command
Correct comment on HMRFPO_ENABLE flow for CSE Lite SKU. In order to place
CSE into SECOVER_MEI_MSG mode, below procedure has to be followed.
1. Ensure CSE boots from RO(BP1).
	- Set CSE's next boot partition to RO
	- Issue GLOBAL_RESET HECI command to reset the system
2. Send HMRFPO_ENABLE command to CSE. Further, no reset is required.

TEST=Verified on hatch

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I213e02ba3898194fa6c8fe38fab34b5c19f25aa1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41340
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-15 07:33:50 +00:00
Alex Levin 9e8dd06cd4 mb/google/volteer: Add delay to WWAN GPIO init sequence
Based on Fibocom HW user manual RESET should be deasserted at least 20ms after the power on pin.
The design for the reset pin is open drain connected to a pull up, so it is set to high-Z (configured as GPIO in) after 20ms.

BUG=b:152013143
BRANCH=none
TEST=traced the signals using a scope to verify timing is met.

Signed-off-by: Alex Levin <levinale@chromium.org>
Change-Id: I7c947d1bc4cce1f97383a2f2c254986e182661c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41356
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-15 04:32:41 +00:00
Rajat Jain ecc4c4e5f1 acpigen_ps2_keybd: Add keymap for Power key
Power key is a special non-matrixed key. Chrome /powerd
only listens to the keyboard device for this key, so add
its keymap.

BUG=b:155941390
TEST=Test that power key generates KEY_POWER in linux evtest

Change-Id: I570602d9febcb5c17e58761f2004ee88be16c27f
Signed-off-by: Rajat Jain <rajatja@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-15 03:52:39 +00:00
Shaik Sajida Bhanu 9a41af60c4 trogdor: Update pull for Sd-card detect pin
Configuring pull for SD-card detect pin.
Without this SD-card detection is not working as expected

Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org>
Change-Id: I77bf355a049224784a160defa6bee66d0f9ceb75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-05-14 23:29:42 +00:00
vsujithk e8ee6f975b sc7180: GPIO: Add I2S configuration for sc7180
Configuring GPIO Pins as I2S mode for Audio speaker.

Change-Id: I681aa6d0d57671b0fd9b7bc88de6f2cc202a7af0
Signed-off-by: V Sujith Kumar Reddy <vsujithk@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-05-14 23:29:06 +00:00
Furquan Shaikh cd6804cd16 samsung/exynos5420: add resources during read_resources()
The chipset code was incorrectly adding memory resources
to the domain device after resource allocation occurred.
It's not possible to get the correct view of the address space,
and it's generally incorrect to not add resources during
read_resources(). This change fixes the order by adding resources in
read_resources().

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I49ce6ac88c4cb7cd05ff9d78133593ce97304596
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41374
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-14 21:27:34 +00:00
Furquan Shaikh d6973e811b soc/samsung/exynos5250: add resources during read_resources()
The chipset code was incorrectly adding memory resources
to the domain device after resource allocation occurred.
It's not possible to get the correct view of the address space,
and it's generally incorrect to not add resources during
read_resources(). This change fixes the order by adding resources in
read_resources().

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I419be7edf289636b24b9a7d6c390866ade638de3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-14 21:27:26 +00:00
Furquan Shaikh bcac1cbacd soc/nvidia/tegra124: add resources during read_resources()
The chipset code was incorrectly adding memory resources
to the domain device after resource allocation occurred.
It's not possible to get the correct view of the address space,
and it's generally incorrect to not add resources during
read_resources(). This change fixes the order by adding resources in
read_resources().

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I16f0439679471366723a0084918a20cd95834831
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41372
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-14 21:26:54 +00:00
Furquan Shaikh 1dac605872 aspeed/ast2050: Fix when resources are added
This change moves adding of resources to read_resources() instead of
set_resources().

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I7d5e4aa0fc28dd35f774957ef303d8854aa07913
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41370
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-14 21:25:59 +00:00
Furquan Shaikh fc752b6918 soc/amd/stoneyridge: add resources during read_resources()
The chipset code was incorrectly adding memory resources
to the domain device after resource allocation occurred.
It's not possible to get the correct view of the address space,
and it's generally incorrect to not add resources during
read_resources(). This change fixes the order by adding resources
during read_resources().

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I532f508936d5ec154cbcb3538949316ae4851105
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41369
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-14 21:25:50 +00:00
Furquan Shaikh ffa5e8ddcf nb/intel/i440bx: add resources during read_resources()
The chipset code was incorrectly adding memory resources
to the domain device after resource allocation occurred.
It's not possible to get the correct view of the address space,
and it's generally incorrect to not add resources during
read_resources(). This change fixes the order by adding resources in
read_resources().

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I84c1ba8645b548248a8bb8bf5bc4953d3be12475
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Keith Hui <buurin@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-14 21:25:38 +00:00
Aaron Durbin 1ca24332c4 nb/intel/sandybridge: add resources during read_resources()
The chipset code was incorrectly adding memory resources
to the domain device after resource allocation occurred.
It's not possible to get the correct view of the address space,
and it's generally incorrect to not add resources during
read_resources(). Fix the order by hanging the resources off
of the host bridge device.

Change-Id: I8a7081020be43da055b7de5a56dd97a7b5a9f09c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-05-14 21:24:55 +00:00
Anil Kumar 7ac6a987d0 mb/google/deltaur: Configure GPIO B11 as PMCALERT
GPIO B11 pin should be configured as PMCALERT function. This is
required for the intergrated USB-C feature to work in the SOC

BUG=b:154778458, b:156288164
TEST= build and boot coreboot image on deltan. Test Type-C port
enumeration on Chrome OS

Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I8f995901b0a50d2c74f57aba96f86134c9d569e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41378
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-14 15:36:21 +00:00
Furquan Shaikh 2412924bc7 mb/google/volteer: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports
This change enables PCIEXP_HOTPLUG to support resource allocation for
TCSS TBT/USB4 ports.

BUG=b:149186922

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I4cb820e83da40434b00198b934453805e35ef1ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-14 15:08:11 +00:00
Furquan Shaikh cc35f723fd soc/intel: Drop ABOVE_4GB_MEM_BASE_SIZE and use cpu_phys_address_size()
This change uses cpu_phys_address_size() to calculate the size of high
MMIO region instead of a macro for each SoC. This ensures that the
entire range above TOUUD that can be addressed by the CPU is used for
MMIO above 4G boundary.

Change-Id: I01a1a86c0c65856f9f35185c2f233c58f18f5dfe
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-14 15:06:39 +00:00
Furquan Shaikh abd4714ee0 soc/intel: Always advertise MMIO window above 4G in ACPI tables
There should be no harm in advertising the MMIO window above 4G in
ACPI tables unconditionally. OS can decide whether or not to use the
window. This change removes the config option enable_above_4GB_mmio
and instead adds the correct MMIO window (above 4G) details to ACPI
tables always.

Change-Id: Ie728f6ee7f396918e61b29ade862b57dac36cb08
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41276
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-14 15:06:28 +00:00
Furquan Shaikh 1085fee761 soc/intel/common/block/systemagent: Use TOUUD as base for MMIO above 4G
This change sets the base for MMIO above 4G to TOUDD. It matches what
is used by resource allocator if MMIO resources are allocated above 4G
and also matches the expectation in northbridge.asl. This change
also gets rid of the macro ABOVE_4GB_MEM_BASE_ADDRESS since it is now
unused.

BUG=b:149186922
TEST=Verified that kernel does not complain about MMIO windows above
4G.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ibbbfbdad867735a43cf57c256bf206a3f040f383
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41155
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-14 15:06:15 +00:00
Bill XIE 6b95507ec5 mainboard/lenovo/x230: Add ThinkPad x230s as a variant
The code is based on autoport and that for X230. Major differences are:
    - Only one DDR3 slot
    - HM77 PCH
    - M.2 socket instead of mini pci-e
    - no docking
    - no tpm

Tested:
    - CPU i5-3337U
    - Slotted DIMM 8GiB
    - Camera
    - pci-e and usb2 on M.2 slot with A key for wlan
    - sata and usb2  (no superspeed components) on M.2 slot with B key for wwan
    - On board SDHCI connected to pci-e
    - USB3 ports
    - libgfxinit-based graphic init
    - NVRAM options for North and South bridges
    - Sound
    - Thinkpad EC
    - S3
    - Linux 4.9 within Debian GNU/Linux stable, loaded from
      Seabios.

Untested:
    - Touch screen, which is said to work under ubuntu but not debian.

Change-Id: Ie537645d5ffaee799e79af2f821f80c3ebd2dfec
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-13 12:10:38 +00:00
Jamie Chen 7410992391 mb/google/puff: add a region to cache SPD data
This patch adds a SPI rom region RW_SPD_CACHE on Puff and it can be used
on spd_cache to reduce reading SPD data from SODIMM by smbus. It's for
saving the boot time and it can be used to trigger MRC retraining when
memory DIMM is changed.

BUG=b:146457985
BRANCH=None
TEST=Build puff successfully and verified below two items.
     1. To change memory DIMM can trigger retraining.
     2. one DIMM save the boot time : 158ms
        two DIMM save the boot time : 265ms

Change-Id: I8d07fddf113a767d62394cb31e33b56f22f74351
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-05-13 12:04:32 +00:00
Jamie Chen 92ba06fb3e lib/spd_cache: add spd_cache common code
This patch adds some spd_cache functions. They are for implementing the
spd_cache. It's for reducing the SPD fetch time when device uses SODIMMs.
The MRC cache also includes SPD data, but there is no public header file
available to decode the struct of MRC. So SPD cache is another solution.

BUG=b:146457985
BRANCH=None
TEST=Build puff successfully and verified below two items.
     one DIMM save the boot time : 158ms
     two DIMM save the boot time : 265ms

Change-Id: Ia48aa022fabf8949960a50597185c9d821399522
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-05-13 12:04:18 +00:00
Jamie Chen 7adcfde079 lib/spd_bin: add get_spd_sn function
This patch adds the get_spd_sn function. It's for reading SODIMM serial
number. In spd_cache implementation it can use to get serial number
before reading whole SPD by smbus.

BUG=b:146457985
BRANCH=None
TEST=Wrote sample code to get the serial number and ran on puff.
     It can get the serial number correctly.

Change-Id: I406bba7cc56debbd9851d430f069e4fb96ec937c
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40414
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13 12:04:03 +00:00
Nick Vaccaro 7d1a4b2584 mb/google/volteer/variants/halvor: add two SPD files
Adds SPD_LPDDR4X_556b_1R_32Gb_8GbD_QDP_4267.spd.hex, which will be used
initially for the "H9HKNNNCRMBVAR-NEH" SKhynix part as DRAM ID #0.

Adds SPD_LPDDR4X_556b_1R_64Gb_16GbD_QDP_4267.spd.hex, which will be
used initially for the "MT53E1G64D4SQ-046 WT:A" Micron part as
DRAM ID #1.

BUG=b:155423877
TEST=none

Change-Id: I5580f602cd411e415dafcb36bd1ffa43c4f02f60
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41076
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13 08:55:51 +00:00
Elyes HAOUAS bc867d5b1d src/mainboard: Remove unused 'include <stdlib.h>'
Found using following commande:
diff <(git grep -l '#include <stdlib.h>' -- src/) <(git grep -l '
memalign\|malloc\|free' -- src/) |grep -v vendorcode |grep '<'

Change-Id: Ib2ee840a10de5c10d57aa7a75b805ef69dc8da84
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41241
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13 08:54:14 +00:00
Nick Vaccaro 6a197964d9 mb/google/volteer/variants/volteer: Add three generic SPD files
- Add SPD_LPDDR4X_200b_1R_16Gb_16Row_DDP_4267.spd.hex, initially
used for the SKhynix H9HCNNNBKMMLXR-NEE part with DRAM ID #2

- Add SPD_LPDDR4X_200b_2R_64Gb_ODP_4267.spd.hex, initially
used for the SKhynix H9HCNNNFAMMLXR-NEE part with DRAM ID #3

- Add SPD_LPDDR4X_200b_2R_32Gb_QDP_4267.spd.hex, initially
used for the Micron MT53E1G32D2NP-046 WT:A part with DRAM ID #4

BUG=b:147857288
TEST=none

Change-Id: I60d8bb05a4d6d3608adc7de69efc8623d1ca610d
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41126
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13 08:53:45 +00:00
Elyes HAOUAS e30c396ffa src: Remove unused '#include <stddef.h>'
Unused includes found using following commande:
diff <(git grep -l '#include <stddef.h>' -- src/) <(git grep -l
'size_t\|ssize_t\|wchar_t\|wint_t\|NULL\|DEVTREE_EARLY\|DEVTREE_CONST\
|MAYBE_STATIC_NONZERO\|MAYBE_STATIC_BSS\|zeroptr' -- src/)|grep '<'
|grep -v vendor |grep -vF '.h'

Change-Id: Ic54b1db995fe7c61b416fa5e1c4022238e4a6ad5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41150
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13 08:48:50 +00:00