Commit Graph

224 Commits

Author SHA1 Message Date
Peter Stuge 4d77ed9d99 Kconfig: Move vendorcode menu up from the bottom to above Chipset menu
Change-Id: Ic97a497a634533f44d94df297ca6e35d94c34565
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/5160
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-11 21:37:29 +01:00
Aaron Durbin 9a7d7bcea5 baytrail: add initial support
The initial Bay Trail code is intended to support
the mobile and desktop version of Bay Trail. This support
can train memory and execute through ramstage. However,
the resource allocation is not curently handled correctly.
The MRC cache parameters are successfully saved and reused
after the initial cold boot.

BUG=chrome-os-partner:22292
BRANCH=None
TEST=Built and booted on a reference board through ramstage.

Change-Id: I238ede326802aad272c6cca39d7ad4f161d813f5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/168387
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4847
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-31 16:36:59 +01:00
Aaron Durbin 75e297428f coreboot: config to cache ramstage outside CBMEM
Haswell was the original chipset to store the cache
in another area besides CBMEM. However, it was specific
to the implementation. Instead, provide a generic way
to obtain the location of the ramstage cache. This option
is selected using the CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
Kconfig option.

BUG=chrome-os-partner:23249
BRANCH=None
TEST=Built and booted with baytrail support. Also built for
     falco successfully.

Change-Id: I70d0940f7a8f73640c92a75fd22588c2c234241b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172602
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4876
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-30 06:04:02 +01:00
Aaron Durbin 6ac3405fdf x86: include optional reference code blob in cbfs
In order to incorporate external blobs into
CBFS besides MRC have a notion of a reference code
blob. By selecting HAVE_REFCODE_BLOB and providing
the file name the refcode blob will be added to
cbfs as a stage file.

BUG=chrome-os-partner:22866
BRANCH=None
TEST=Using this option and other patches able to build,
     boot, and run blob code.

Change-Id: I472604d77f4cb48f286b5a76b25d8b5bfb0c7780
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174423
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4895
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-30 05:49:47 +01:00
Vladimir Serbinenko 2657e84109 Multiboot: remove multiboot tables generation.
GRUB2-as-payload doesn't use them. Libpayload can live with just coreboot tables
if loaded as payload. memtest86+ can use them but is buggy with them. Solaris
needs a huge boot archive not supported by coreboot and too big to fit in
flash (dozens of megabytes). All-in-all looks like no users are left for this.

Change-Id: Id92f73be5a397db80f5b0132ee57c37ee6eeb563
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4628
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-23 20:37:48 +01:00
Kyösti Mälkki 107f72e674 Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR
This change allows Kconfig options ROM_SIZE and CBFS_SIZE to be
set with values that are not power of 2. The region programmed
as WB cacheable will include all of ROM_SIZE.

Side-effects to consider:

Memory region below flash may be tagged WRPROT cacheable. As an
example, with ROM_SIZE of 12 MB, CACHE_ROM_SIZE would be 16 MB.
Since this can overlap CAR, we add an explicit test and fail
on compile should this happen. To work around this problem, one
needs to use CACHE_ROM_SIZE_OVERRIDE in the mainboard Kconfig and
define a smaller region for WB cache.

With this change flash regions outside CBFS are also tagged WRPROT
cacheable. This covers IFD and ME and sections ChromeOS may use.

Change-Id: I5e577900ff7e91606bef6d80033caaed721ce4bf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4625
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-01-15 15:26:48 +01:00
Kyösti Mälkki 0946190e15 AMD K8 (rev-F): Always have RAMINIT_SYSINFO
K8 Rev F raminit code cannot be built without RAMINIT_SYSINFO,
so have the option enabled together with K8_REV_F_SUPPORT.
Also move the option under AMD K8.

Change-Id: I91fa0b4ae7e3e54fbcb4a4f91eb043956cd0fb60
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4582
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-29 19:45:50 +01:00
Vladimir Serbinenko 113a366848 Add GRUB2 payload to build system
Since a long time GRUB 2 is a viable payload alternative to SeaBIOS and
FILO. So make it easy for coreboot users to use GRUB 2 as a payload by
integrating it into coreboot’s build system, so it can be selected in
Kconfig.

As the last GRUB 2 release 2.00 is too old and has several bugs when
used as a coreboot payload only allow to build GRUB 2 master until a new
GRUB release is done. The downside is, that accidental breakage in
GRUB’s upstream does not affect coreboot users.

Currently the GRUB 2 payload is built with the default modules which
results in an uncompressed size of around 730 kB. Compressed it has a
size of 340 kB, so it should be useable with 512 kB flash ROMs.

Tested with QEMU.

Change-Id: Ie75d5a2cb230390cd5a063d5f6a5d5e3fab6b354
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4058
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-11-19 01:07:25 +01:00
Kyösti Mälkki 2644793ef4 Have option of timestamps, CBMEM console and usbdebug for most boards
As boards without EARLY_CBMEM_INIT do not initialize CBMEM in romstage,
and have no CAR migration, these features are available for ramstage only.

Change-Id: Ic3f77ccdedd4e71ba693619c02c9b98b328a0882
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3970
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-15 13:15:18 +02:00
Kyösti Mälkki f8bf5a10c5 Revert "CBMEM: Always have early initialisation"
This reverts commit de1fe7f655.

While things appeared to work, there were actually invalid references
to CAR storage after CAR was torn down on boards without
EARLY_CBMEM_INIT. It was discussed use of CAR_GLOBAL should be
restricted to boards that handle CAR migration properly.

Change-Id: I9969d2ea79c334a7f95a0dbb7c78065720e6ccae
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3968
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-14 17:16:22 +02:00
Kyösti Mälkki de1fe7f655 CBMEM: Always have early initialisation
Assume EARLY_CBMEM_INIT=y everywhere and remove option from Kconfig.

If romstage does not make the cbmem_initialize() call, features like
COLLECT_TIMESTAMPS and early CBMEM_CONSOLE will execute during
romstage, but that data will get lost as no CAR migration is
executed.

Change-Id: I5615645ed0f5fd78fbc372cf5c3da71a3134dd85
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3917
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21 06:26:54 +02:00
Kyösti Mälkki ecd8424919 Fix whitespace leaked into tree
Clean whitespace errors that have gotten past lint-stable-003-whitespace
and gerrit review.

Change-Id: Id76fc68e9d32d1b2b672d519b75cdc80cc4f1ad9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3920
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-09-17 21:04:35 +02:00
Patrick Georgi 16ae95c4bc Add Kconfig options for Linux as payload
These allow to define a kernel image, initrd and command line.

Change-Id: I40155b812728a176b6d15871e1e6c96e4ad693c8
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/3893
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-08-31 08:58:39 +02:00
Patrick Georgi 2f39eae41d Remove NRV2B compression support
It wasn't even hooked up to the build system anymore.

Change-Id: I4b962ffd945b39451e19da3ec2f7b8e0eecf2e53
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/3892
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-08-31 08:58:37 +02:00
Patrick Georgi 1e44c3ff5a Fix lint-stable target
SEABIOS_PS2_TIMEOUT needs a default, otherwise the "allyesconfig" target
hangs in an endless loop.
The given default is correctly overridden by the (currently sole) user,
the lenovo/x60 target.

Change-Id: I3f5e347c29ccbb4d711a489d067b6c909f030bd0
Reported-by: Kyösti Mälkki
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/3874
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2013-08-16 10:32:43 +02:00
Peter Stuge f040858ec3 payload/SeaBIOS: Add SEABIOS_PS2_TIMEOUT Kconfig variable
This allows mainboards to preconfigure a ps2-keyboard-spinup
timeout when SeaBIOS is chosen as the payload.

The Kconfig option can be changed manually if CONFIG_EXPERT is set.

Change-Id: I5732b18ef04f4bdef6236f35039656ad02011aec
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/3734
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-08-15 20:46:21 +02:00
Kyösti Mälkki 3be80cce29 usbdebug: Add option for verbose logging of connection
Add option to log changes in USB 2.0 EHCI debug port connection.
For romstage move usbdebug as the last initialised console so one
actually can see these messages.

Init order of consoles in ramstage is undetermined and unchanged.

Change-Id: I3aceec8a93064bd952886839569e9f5beb6c5720
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3387
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-10 18:45:34 +02:00
Gabe Black 545c0caac8 Add a HAVE_ARCH_MEMMOVE option to allow overriding memmove.
Change-Id: I4b6a57e7d8e7e685c609b1d85368585b9dd197dc
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3761
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-14 20:33:58 +02:00
Gabe Black 5fbfc911c1 Move the HAVE_ARCH_* config options from src/arch/x86 to src/.
The options that keep track of whether there are arch versions of the standard
string functions shouldn't be in the arch/x86 directory since they apply to
all architectures. Move them into the higher level, shared Kconfig defaulting
to off. Then, in each applicable arch (currently all of them) they can be
selected to on.

Change-Id: I7ea64a583230fdc28773f17fd7cc23e0f0a5f3d6
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3760
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-11 17:55:36 +02:00
Denis 'GNUtoo' Carikli 4cdc5d6fc6 Yabel : Add tracing option needed by i915tool.
This patch was made by listenning to what Ron Minnich told
  me to do on #coreboot IRC channel on Freenode with my
  adaptations on top.

i915tool is at https://code.google.com/p/i915tool/ ,
  the one in coreboot is outdated.

Change-Id: I13cd684f4c290114836fbd7babd461153e8d6124
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3277
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 22:57:26 +02:00
Paul Menzel 1e24f4b37f Kconfig: Remove duplicate entry for `USE_OPTION_TABLE`
The following commit

    commit eb50c7d922
    Author: Edwin Beasant <edwin_beasant@virtensys.com>
    Date:   Tue Jul 6 21:05:04 2010 +0000

    Re-integrate "USE_OPTION_TABLE" code.

added a duplicate entry `config USE_OPTION_TABLE`. Remove it again.

Change-Id: I3ff64c360bad531439e74fa1b25a06c4a447a33f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3165
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-05-23 10:42:41 +02:00
Stefan Reinauer b0fb2234be Drop llshell
This feature has not been used and was never fully integrated.
In the progress of cleaning up coreboot, let's drop it.

Change-Id: Ib40acdba30aef00a4a162f2b1009bf8b7db58bbb
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3251
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-20 08:42:28 +02:00
Aaron Durbin 38c326d041 x86: add thread support
Thread support is added for the x86 architecture. Both
the local apic and the tsc udelay() functions have a
call to thread_yield_microseconds() so as to provide an
opportunity to run pending threads.

Change-Id: Ie39b9eb565eb189676c06645bdf2a8720fe0636a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3207
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-14 05:24:18 +02:00
Aaron Durbin 4409a5eef6 coreboot: add thread cooperative multitasking
The cooperative multitasking support allows the boot state machine
to be ran cooperatively with other threads of work. The main thread
still continues to run the boot state machine
(src/lib/hardwaremain.c).  All callbacks from the state machine are
still ran synchronously from within the main thread's context.
Without any other code added the only change to the boot sequence
when cooperative multitasking is enabled is the queueing of an idlle
thread. The idle thread is responsible for ensuring progress is made
by calling timer callbacks.

The main thread can yield to any other threads in the system. That
means that anyone that spins up a thread must ensure no shared
resources are used from 2 or more execution contexts. The support
is originally intentioned to allow for long work itesm with busy
loops to occur in parallel during a boot.

Note that the intention on when to yield a thread will be on
calls to udelay().

Change-Id: Ia4d67a38665b12ce2643474843a93babd8a40c77
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3206
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-14 05:18:47 +02:00
Stefan Reinauer 3949e37834 Drop CONFIG_AP_CODE_IN_CAR
This option has not been enabled on any board and was considered
obsolete last time it was touched. If we need the functionality,
let's fix this in a generic way instead of a K8 specific way.
This was mostly a speedup hack back in the day.

Change-Id: Ib1ca248c56a7f6e9d0c986c35d131d5f444de0d8
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3211
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-05-08 19:14:21 +02:00
Paul Menzel e62b8e9a8f Kconfig: Capitalize CBMEM in description of `EARLY_CBMEM_INIT`
Capitalizing CBMEM seems to be the official spelling as can be seen
in the descriptions around the `EARLY_CBMEM_INIT` Kconfig option.

Change-Id: I046a678c3b04ef7e681de46aa137cedc405d546f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3143
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-03 06:26:19 +02:00
Aaron Durbin 340ca91f18 coreboot: add timer queue implementation
A timer queue provides the mechanism for calling functions
in the future by way of a callback. It utilizes the MONOTONIC_TIMER
to track time through the boot. The implementation is a min-heap
for keeping track of the next-to-expire callback.

Change-Id: Ia56bab8444cd6177b051752342f53b53d5f6afc1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3158
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-01 07:19:12 +02:00
Aaron Durbin a421791db8 coreboot: introduce monotonic timer API
The notion of a monotonic timer is introduced. Along with it
are helper functions and other types for comparing times. This
is just the framework where it is the responsibility of the
chipset/board to provide the implementation of timer_monotonic_get().

The reason structs are used instead of native types is to allow
for future changes to the data structure without chaning all the
call sites.

Change-Id: Ie56b9ab9dedb0da69dea86ef87ca744004eb1ae3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3152
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-01 07:13:43 +02:00
Aaron Durbin c15551ab08 dynamic cbmem: fix memconsole and timestamps
There are assumptions that COLLECT_TIMESTAMPS and CONSOLE_CBMEM
rely on EARLY_CBMEM_INIT. This isn't true in the face of
DYNAMIC_CBMEM as it provides the same properties as EARLY_CBMEM_INIT.
Therefore, allow one to select COLLECT_TIMESTAMPS and CONSOLE_CBMEM
when DYNAMIC_CBMEM is selected.  Lastly, don't hard code the cbmem
implementation when COLLECT_TIMESTAMPS is selected.

Change-Id: I053ebb385ad54a90a202da9d70b9d87ecc963656
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2895
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-23 19:44:25 +01:00
Aaron Durbin dd4a6d2357 coreboot: dynamic cbmem requirement
Dynamic cbmem is now a requirement for relocatable ramstage.
This patch replaces the reserve_* fields in the romstage_handoff
structure by using the dynamic cbmem library.

The haswell code is not moved over in this commit, but it should be
safe because there is a hard requirement for DYNAMIC_CBMEM when using
a reloctable ramstage.

Change-Id: I59ab4552c3ae8c2c3982df458cd81a4a9b712cc2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2849
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-22 00:13:42 +01:00
Aaron Durbin df3a109b72 cbmem: dynamic cbmem support
This patch adds a parallel implementation of cbmem that supports
dynamic sizing. The original implementation relied on reserving
a fixed-size block of memory for adding cbmem entries. In order to
allow for more flexibility for adding cbmem allocations the dynamic
cbmem infrastructure was developed as an alternative to the fixed block
approach. Also, the amount of memory to reserve for cbmem allocations
does not need to be known prior to the first allocation.

The dynamic cbmem code implements the same API as the existing cbmem
code except for cbmem_init() and cbmem_reinit(). The add and find
routines behave the same way. The dynamic cbmem infrastructure
uses a top down allocator that starts allocating from a board/chipset
defined function cbmem_top(). A root pointer lives just below
cbmem_top(). In turn that pointer points to the root block which
contains the entries for all the large alloctations. The corresponding
block for each large allocation falls just below the previous entry.

It should be noted that this implementation rounds all allocations
up to a 4096 byte granularity. Though a packing allocator could
be written for small allocations it was deemed OK to just fragment
the memory as there shouldn't be that many small allocations. The
result is less code with a tradeoff of some wasted memory.

           +----------------------+ <- cbmem_top()
  |   +----|   root pointer       |
  |   |    +----------------------+
  |   |    |                      |--------+
  |   +--->|   root block         |-----+  |
  |        +----------------------+     |  |
  |        |                      |     |  |
  |        |                      |     |  |
  |        |   alloc N            |<----+  |
  |        +----------------------+        |
  |        |                      |        |
  |        |                      |        |
 \|/       |   alloc N + 1        |<-------+
  v        +----------------------+

In addition to preserving the previous cbmem API, the dynamic
cbmem API allows for removing blocks from cbmem. This allows for
the boot process to allocate memory that can be discarded after
it's been used for performing more complex boot tasks in romstage.

In order to plumb this support in there were some issues to work
around regarding writing of coreboot tables. There were a few
assumptions to how cbmem was layed out which dictated some ifdef
guarding and other runtime checks so as not to incorrectly
tag the e820 and coreboot memory tables.

The example shown below is using dynamic cbmem infrastructure.
The reserved memory for cbmem is less than 512KiB.

coreboot memory table:
 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
 1. 0000000000001000-000000000002ffff: RAM
 2. 0000000000030000-000000000003ffff: RESERVED
 3. 0000000000040000-000000000009ffff: RAM
 4. 00000000000a0000-00000000000fffff: RESERVED
 5. 0000000000100000-0000000000efffff: RAM
 6. 0000000000f00000-0000000000ffffff: RESERVED
 7. 0000000001000000-000000007bf80fff: RAM
 8. 000000007bf81000-000000007bffffff: CONFIGURATION TABLES
 9. 000000007c000000-000000007e9fffff: RESERVED
10. 00000000f0000000-00000000f3ffffff: RESERVED
11. 00000000fed10000-00000000fed19fff: RESERVED
12. 00000000fed84000-00000000fed84fff: RESERVED
13. 0000000100000000-00000001005fffff: RAM
Wrote coreboot table at: 7bf81000, 0x39c bytes, checksum f5bf
coreboot table: 948 bytes.
CBMEM ROOT  0. 7bfff000 00001000
MRC DATA    1. 7bffe000 00001000
ROMSTAGE    2. 7bffd000 00001000
TIME STAMP  3. 7bffc000 00001000
ROMSTG STCK 4. 7bff7000 00005000
CONSOLE     5. 7bfe7000 00010000
VBOOT       6. 7bfe6000 00001000
RAMSTAGE    7. 7bf98000 0004e000
GDT         8. 7bf97000 00001000
ACPI        9. 7bf8b000 0000c000
ACPI GNVS  10. 7bf8a000 00001000
SMBIOS     11. 7bf89000 00001000
COREBOOT   12. 7bf81000 00008000

And the corresponding e820 entries:
BIOS-e820: [mem 0x0000000000000000-0x0000000000000fff] type 16
BIOS-e820: [mem 0x0000000000001000-0x000000000002ffff] usable
BIOS-e820: [mem 0x0000000000030000-0x000000000003ffff] reserved
BIOS-e820: [mem 0x0000000000040000-0x000000000009ffff] usable
BIOS-e820: [mem 0x00000000000a0000-0x00000000000fffff] reserved
BIOS-e820: [mem 0x0000000000100000-0x0000000000efffff] usable
BIOS-e820: [mem 0x0000000000f00000-0x0000000000ffffff] reserved
BIOS-e820: [mem 0x0000000001000000-0x000000007bf80fff] usable
BIOS-e820: [mem 0x000000007bf81000-0x000000007bffffff] type 16
BIOS-e820: [mem 0x000000007c000000-0x000000007e9fffff] reserved
BIOS-e820: [mem 0x00000000f0000000-0x00000000f3ffffff] reserved
BIOS-e820: [mem 0x00000000fed10000-0x00000000fed19fff] reserved
BIOS-e820: [mem 0x00000000fed84000-0x00000000fed84fff] reserved
BIOS-e820: [mem 0x0000000100000000-0x00000001005fffff] usable

Change-Id: Ie3bca52211800a8652a77ca684140cfc9b3b9a6b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2848
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21 23:24:19 +01:00
Aaron Durbin 8e4a355773 coreboot: introduce CONFIG_RELOCATABLE_RAMSTAGE
This patch adds an option to build the ramstage as a reloctable binary.
It uses the rmodule library for the relocation. The main changes
consist of the following:

1. The ramstage is loaded just under the cmbem space.
2. Payloads cannot be loaded over where ramstage is loaded. If a payload
   is attempted to load where the relocatable ramstage resides the load
   is aborted.
3. The memory occupied by the ramstage is reserved from the OS's usage
   using the romstage_handoff structure stored in cbmem. This region is
   communicated to ramstage by an CBMEM_ID_ROMSTAGE_INFO entry in cbmem.
4. There is no need to reserve cbmem space for the OS controlled memory for
   the resume path because the ramsage region has been reserved in #3.
5. Since no memory needs to be preserved in the wake path, the loading
   and begin of execution of a elf payload is straight forward.

Change-Id: Ia66cf1be65c29fa25ca7bd9ea6c8f11d7eee05f5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2792
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-03-21 22:28:28 +01:00
Aaron Durbin 81108b9059 cbfs: alternative support for cbfs_load_payload()
In certain situations boot speed can be increased by providing an
alternative implementation to cbfs_load_payload(). The
ALT_CBFS_LOAD_PAYLOAD option allows for the mainboard or chipset to
provide its own implementation.

Booted baskingridge board with alternative and regular
cbfs_load_payload().

Change-Id: I547ac9881a82bacbdb3bbdf38088dfcc22fd0c2c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2782
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-19 18:47:57 +01:00
Aaron Durbin ad93552b86 lib: add rmodule support
A rmodule is short for relocation module. Relocaiton modules are
standalone programs. These programs are linked at address 0 as a shared
object with a special linker script that maintains the relocation
entries for the object. These modules can then be embedded as a raw
binary (objcopy -O binary) to be loaded at any location desired.

Initially, the only arch support is for x86. All comments below apply to
x86 specific properties.

The intial user of this support would be for SMM handlers since those
handlers sometimes need to be located at a dynamic address (e.g. TSEG
region).

The relocation entries are currently Elf32_Rel. They are 8 bytes large,
and the entries are not necessarily in sorted order. An future
optimization would be to have a tool convert the unsorted relocations
into just sorted offsets. This would reduce the size of the blob
produced after being processed. Essentialy, 8 bytes per relocation meta
entry would reduce to 4 bytes.

Change-Id: I2236dcb66e9d2b494ce2d1ae40777c62429057ef
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2692
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-18 18:40:34 +01:00
Idwer Vollering 1a43309bf7 bump SeaBIOS to 1.7.2.1
Update coreboot to use SeaBIOS' tag rel-1.7.2.1

Change-Id: I01969407964a7cf64f7c4800b59c6aed845b24f9
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/2575
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-03-04 11:00:17 +01:00
Paul Menzel a46a712610 GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«
In the file `COPYING` in the coreboot repository and upstream [1]
just one space is used.

The following command was used to convert all files.

    $ git grep -l 'MA  02' | xargs sed -i 's/MA  02/MA 02/'

[1] http://www.gnu.org/licenses/gpl-2.0.txt

Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2490
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-03-01 10:16:08 +01:00
Stefan Reinauer 1bc9efaf65 CBMEM: always initialize early if the board supports it
This allows to drop some special cases in romstage.c

Change-Id: I53fdfcd1bb6ec21a5280afa07a40e3f0cba11c5d
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2551
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-02-28 18:02:29 +01:00
Stefan Reinauer fd611f9c2c Drop CONFIG_WRITE_HIGH_TABLES
It's been on for all boards per default since several years now
and the old code path probably doesn't even work anymore. Let's
just have one consistent way of doing things.

Change-Id: I58da7fe9b89a648d9a7165d37e0e35c88c06ac7e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2547
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-28 00:00:30 +01:00
Patrick Georgi 70c85eab83 build system: Retire REQUIRES_BLOB
REQUIRES_BLOB assumes that all blob files come from the 3rdparty directory,
builds failed when all files were configured to point to other sources.

This change modifies the blob mechanism so that cbfs-files can be tagged as
"required" with some specification what is missing.

If the configured files can't be found (wrong path, missing file), the build
system returns a list of descriptions, then aborts.

Change-Id: Icc128e3afcee8acf49bff9409b93af7769db3517
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2418
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-19 11:00:41 +01:00
Stefan Reinauer a957b7ad21 ARMv7: drop multiboot support
Multiboot is an x86 only thing. Drop support on ARM.

Change-Id: I13fafa464a794206d5450b4a1f23a187967a8338
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2392
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14 23:55:34 +01:00
David Hendricks c146d668ef DEBUG_CBFS should not depend on TPM
This seemed to have been introduced in fe422184.

Change-Id: I4f9ecfbec42aa8c0bb8887675a3add8951645b98
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2327
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-09 01:46:26 +01:00
Hung-Te Lin ad173ea70b console: Revise serial console configuration names.
The console drivers (especially serial drivers) in Kconfig were named in
different styles. This change will rename configuration names to a better naming
style.

 - EARLY_CONSOLE:
        Enable output in pre-ram stage. (Renamed from EARLY_SERIAL_CONSOLE
        because it also supports non-serial)

 - CONSOLE_SERIAL:
        Enable serial output console, from one of the serial drivers. (Renamed
        from SERIAL_CONSOLE because other non-serial drivers are named as
        CONSOLE_XXX like CONSOLE_CBMEM)

 - CONSOLE_SERIAL_UART:
	Device-specific UART driver. (Renamed from
	CONSOLE_SERIAL_NONSTANDARD_MEM because it may be not memory-mapped)

 - HAVE_UART_SPECIAL:
        A dependency for CONSOLE_SERIAL_UART.

Verified to boot on x86/qemu and armv7/snow, and still seeing console
messages in romstage for both platforms.

Change-Id: I4bea3c8fea05bbb7d78df6bc22f82414ac66f973
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2299
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-02-08 01:56:15 +01:00
Stefan Reinauer 275fb63832 Don't add another Kconfig special case for Tiano
We don't need a special Kconfig variable anymore
because the FV _is_ the payload, unlike with the
old tianocoreboot implementation.

Change-Id: I349b5a95783e4146e3ab7f926871188cf2021935
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2284
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2013-02-05 23:37:54 +01:00
Patrick Georgi ed08bcc12d Hook up corebootPkg as Tianocore payload
This unplugs Stefan's PIANO project.

Change Tianocore payload configuration to use corebootPkg.
As argument you have to give it the COREBOOT.FD generated by
the Tianocore build system.

It automatically determines base address and entry point.

Compression setting is honored (ie. no compression if you don't
want), but corebootPkg currently assumes that coreboot is doing
it. Loading a 6MB payload into CBFS without compression will fail
more often than not.

Change-Id: If9c64c9adb4a846a677c8af40f149ce697059ee6
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2280
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-04 22:57:20 +01:00
Stefan Reinauer cc5b344662 Project PIANO aka tianocoreboot
This is a Tiano Core loader payload based on libpayload.  It
will load a Tiano Core DXE core from an UEFI firmware volume
stored in CBFS.

Currently Tiano Core dies because it does not find all the UEFI services it needs:

coreboot-4.0-3316-gc5c9ff8-dirty Mon Jan 28 15:37:12 PST 2013 starting...
[..]
Tiano Core Loader v1.0
Copyright (C) 2013 Google Inc. All rights reserved.

Memory Map (5 entries):
  1. 0000000000000000 - 0000000000000fff [10]
  2. 0000000000001000 - 000000000009ffff [01]
  3. 00000000000c0000 - 0000000003ebffff [01]
  4. 0000000003ec0000 - 0000000003ffffff [10]
  5. 00000000ff800000 - 00000000ffffffff [02]

DXE code:  03e80000
DXE stack: 03e60000
HOB list:  03d5c000

Found UEFI firmware volume.
  GUID: 8c8ce578-8a3d-4f1c-9935-896185c32dd3
  length: 0x0000000000260000

Found DXE core at 0xffc14e0c
  Section 0: .text     size=000158a0 rva=00000240 in file=000158a0/00000240 flags=60000020
  Section 1: .data     size=00006820 rva=00015ae0 in file=00006820/00015ae0 flags=c0000040
  Section 2: .reloc    size=000010a0 rva=0001c300 in file=000010a0/0001c300 flags=42000040

Jumping to DXE core at 0x3e80000
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 3E96708
HOBLIST address in DXE = 0x3E56010
Memory Allocation 0x00000003 0x3E80000 - 0x3EBFFFF
FV Hob            0xFFC14D78 - 0xFFE74D77
InstallProtocolInterface: D8117CFE-94A6-11D4-9A3A-0090273FC14D 3E95EA0
InstallProtocolInterface: EE4E5898-3914-4259-9D6E-DC7BD79403CF 3E9630C

Security Arch Protocol not present!!

CPU Arch Protocol not present!!

Metronome Arch Protocol not present!!

Timer Arch Protocol not present!!

Bds Arch Protocol not present!!

Watchdog Timer Arch Protocol not present!!

Runtime Arch Protocol not present!!

Variable Arch Protocol not present!!

Variable Write Arch Protocol not present!!

Capsule Arch Protocol not present!!

Monotonic Counter Arch Protocol not present!!

Reset Arch Protocol not present!!

Real Time Clock Arch Protocol not present!!

ASSERT_EFI_ERROR (Status = Not Found)
ASSERT /home/reinauer/svn/Tiano/edk2/MdeModulePkg/Core/Dxe/DxeMain/DxeMain.c(461): !EFI_ERROR (Status)

Change-Id: I14068e9a28ff67ab1bf03105d56dab2e8be7b230
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2154
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-30 17:34:40 +01:00
Stefan Reinauer d37ab454d4 Implement GCC code coverage analysis
In order to provide some insight on what code is executed during
coreboot's run time and how well our test scenarios work, this
adds code coverage support to coreboot's ram stage. This should
be easily adaptable for payloads, and maybe even romstage.

See http://gcc.gnu.org/onlinedocs/gcc/Gcov.html for
more information.

To instrument coreboot, select CONFIG_COVERAGE ("Code coverage
support") in Kconfig, and recompile coreboot. coreboot will then
store its code coverage information into CBMEM, if possible.
Then, run "cbmem -CV" as root on the target system running the
instrumented coreboot binary. This will create a whole bunch of
.gcda files that contain coverage information. Tar them up, copy
them to your build system machine, and untar them. Then you can
use your favorite coverage utility (gcov, lcov, ...) to visualize
code coverage.

For a sneak peak of what will expect you, please take a look
at http://www.coreboot.org/~stepan/coreboot-coverage/

Change-Id: Ib287d8309878a1f5c4be770c38b1bc0bb3aa6ec7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2052
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-12 19:09:55 +01:00
Stefan Reinauer 3600e960b6 Fix UART8250 console prototypes
and disable IO mapped UARTs on ARMV7 per default

Change-Id: I712c4677cbc8519323970556718f9bb6327d83c8
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2021
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2012-12-12 00:27:10 +01:00
Stefan Reinauer 6edb729cee Drop ARCH_ARM in favor of ARCH_ARMV7
The ARM architecture is really many architectures, and most
of them need their own toolchain. After discussing with Ron
and David, we decided that we're going to call the architecture
of our ARM board armv7.. This patch cleans out the remainders
of ARCH_ARM in the tree and moves on to consistent ARMv7 naming.
As of now, we only support little endian ARMv7 CPUs. We can
fix that for big endian if/when it comes our way.

Change-Id: Id70c7ef615f600e4d09961d811e7ac974fce4811
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1968
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-06 02:26:42 +01:00
Stefan Reinauer 8d7115560d Rename devices -> device
to match src/include/device

Change-Id: I5d0e5b4361c34881a3b81347aac48738cb5b9af0
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1960
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2012-11-30 23:59:58 +01:00
Ronald G. Minnich 78a1667cbc Create a a new configuration variable for PCI
Not all architectures have PCI. This new config variable allows control
of whether PCI support is configued in. It is selected for ARCH_X86.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Change-Id: Ic5fe777b14fd6a16ba605ada1e22acf3e8a2c783
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/1947
Tested-by: build bot (Jenkins)
2012-11-30 19:02:58 +01:00
David Hendricks 5367e47ef1 Add dummy Kconfig options for armv7
This adds a dummy config for ARMV7 for developing various
follow-up patches which rely on ARCH_ARMV7.

Change-Id: Id913054d916f41607d10ebc02aaf74082e14b554
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/1939
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-11-30 00:03:37 +01:00
Ronald G. Minnich 6e3728bb12 Add .h files for samsung exynos 5250
Per a conversation with Stefan, these chip-dependent files are moved
to the src tree, in the manner of other chips (north and southbridge).

Change-Id: I12645ba05eb241eda200ed06cb633541a6a98119
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Reviewed-on: http://review.coreboot.org/1925
Tested-by: build bot (Jenkins)
2012-11-28 07:55:59 +01:00
Stefan Reinauer 56cd70bba2 Fix Kconfig GENERATE_*_TABLE usage
Some boards selected GENERATE_ instead of HAVE_

Change-Id: I450c22d7b044f0c88c21692246d452d516a68a83
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1841
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-16 01:15:55 +01:00
Stefan Reinauer 95a6396ae3 Clean up Kconfig
- move VGA handling options into devices/Kconfig
- make Devices a top level menu
- move some  options "closer" to the code they control

Change-Id: Ia79541d18b2b0d9b89a8b154255e312060627c48
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1840
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-16 01:13:47 +01:00
Stefan Reinauer 8483344802 Drop Kconfig.deprecated_options
Both remaining options, DRIVERS_PS2_KEYBOARD and ID_SECTION_OFFSET
are not likely to go away any time soon, so let's not keep them
in Kconfig.deprecated_options but move them close to the code they
control.

Change-Id: I310b877c5b3d5a3444056641c4aee07a48c4c4be
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1839
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-16 01:13:40 +01:00
Stefan Reinauer fa2fc339c5 Drop Kconfig variable BOARD_HAS_HARD_RESET
hard_reset was indeed consolidated and moved into the southbridge
code a while ago, but the config variable was still kept alife, with
some duplicate code.

Change-Id: I60d4a87de916667f6e89353dfbe1a7b9eca380f7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1837
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-16 01:13:10 +01:00
Stefan Reinauer 5b635795cc SandyBridge/IvyBridge: Add IFD and ME firmware automatically
Right now coreboot's build process produces images that are
not booting on actual hardware because they are smaller than
the actual flash device and also don't have an IFD nor an ME
firmware in them. In order to produce bootable images, you
needed a wrapper script / extra step until now. With this
change, the resulting coreboot.rom is actually bootable.

Change-Id: I82714069fb004d4badc41698747a704bd9fed4da
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1771
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13 00:24:26 +01:00
Peter Stuge 9b48ef2733 Update SeaBIOS stable to the release-1.7.1 commit
Change-Id: I0dffe89c31e45914f795d9ad8efb787b5fdbb7a8
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/1583
Tested-by: build bot (Jenkins)
2012-10-16 03:31:05 +02:00
Alexandru Gagniuc 70c660fd14 pirq_routing: Allow routing with more than 4 PIRQ links
pirq_routing_irqs assumed that only four links are available for PIRQ
routing, INTA to INTD. Some chipsets provide more, up to INTH.
When pirq_routing_irqs found a link number greater than 4 in the pirq table,
it would not assign that IRQ. This is a shame, as it limits the flexibility
of routing IRQs.
Make the maximum number of links a Kconfig variable, and modify the code to
respect it. This works beatifully on the VX900, which provides 8 routable
interrupts.
While we're at it, also refactor pirq_routing_irqs, and add some much
needed comments.
Rename pirq_routing_irqs to pirq_route_irqs to demistify the role of this
function.
The copyrights added were determined from git log filename.

Change-Id: I4b565315404c65b871406f616474e2cc9e6e013e
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/1482
Tested-by: build bot (Jenkins)
2012-10-04 04:27:29 +02:00
Kyösti Mälkki 651339bb5d Fix mptable build troubles
A missing mptable.c file got passed jenkins, got merged
and broke the build. Hopefully finally fix this.

Deletes unused files:
   src/mainboard/asus/dsbf/mptable.c
   src/mainboard/supermicro/x7db8/mptable.c

Change-Id: Ie81f5a6c4c69ab381f86a243bc8874395e69ee26
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1486
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-25 00:34:46 +02:00
Kyösti Mälkki 1c5071d175 Drop HAVE_MAINBOARD_RESOURCES
These existed to provide a hook to add reserved memory regions
in the coreboot memory table. Reserved memory are now
added as resources.

Change-Id: I9f83df33845cfa6973b018a51cf9444dbf0f8667
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1414
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-08-08 03:44:51 +02:00
Denis 'GNUtoo' Carikli e4cece0d6f Add an option for Waiting for gdb connection if the gdb stub configuration is chosen.
Here's a quick demonstration on how to use it(tested on M4A785T-M).
  (gdb) file ./build/cbfs/fallback/coreboot_ram.debug
  Reading symbols from [...]/build/cbfs/fallback/coreboot_ram.debug...done.
  (gdb) set remotebaud 115200
  (gdb) target remote /dev/ttyUSB0
  Remote debugging using /dev/ttyUSB0
  _text () at src/arch/x86/lib/c_start.S:85
  85		call	hardwaremain

Change-Id: Ia49cbecc41deb061433bc39f5b81715da49edc98
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/1134
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-23 07:50:07 +02:00
Steve Goodrich f026912776 Converted the FRAMEBUFFER_VESA_MODE to a choice.
Being a diligent soul, I changed the "enter a numeric value for the
mode you want" option to a choice of common modes.  New modes can be
added quite easily.

Change-Id: I8cf4572c2d36ced6549541ec173c0c02d8eaca4a
Signed-off-by: Steve Goodrich <steve.goodrich@se-eng.com>
Reviewed-on: http://review.coreboot.org/1036
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-05-24 21:54:08 +02:00
Stefan Reinauer 1c56d9b102 Add SPI flash driver
This driver is taken from u-boot and adapted to match
coreboot. It still contains some hacks and is ICH specific
at places.

Change-Id: I97dd8096f7db3b62f8f4f4e4d08bdee10d88f689
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/997
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-10 23:52:44 +02:00
Stefan Reinauer fe4221848f Make CBFS output more consistent
- Prefix all CBFS output messages with CBFS:
- Add an option DEBUG_CBFS that is off by default. Without DEBUG_CBFS
  enabled, the code will no longer print all the files it walks for
  every file lookup.
- Add DEBUG() macro next to LOG() and ERROR() to specify which messages
  should only be visible with DEBUG_CBFS printed.
- Actually print a message when the file we're looking for was found. :)

old:
Searching for fallback/coreboot_ram
Check cmos_layout.bin
Check pci8086,0106.rom
Check fallback/romstage
Check fallback/coreboot_ram

Change-Id: I2d731fae17a5f6ca51d435cfb7a58d6e017efa24
Stage: loading fallback/coreboot_ram @ 0x100000 (540672 bytes), entry @ 0x100000
Stage: done loading.
new:
CBFS: Looking for 'fallback/coreboot_ram'
CBFS: found.
CBFS: loading stage fallback/coreboot_ram @ 0x100000 (507904 bytes), entry @ 0x100000
CBFS: stage loaded.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/993
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-04 08:11:28 +02:00
Patrick Georgi 7e9b9d893c Add Kconfig options to handle the blobs repository
One option to allow using the repo (defaults to no),
one to let boards state that they require it in the
current configuration.

The build system checks out the repo if allowed, and
fails if the repo is requested by the configuration
but not desired by the user.

Change-Id: If71d80b329cf528aa467fcb0b4d9d7c7434aab27
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/957
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-05-01 00:09:27 +02:00
Uwe Hermann ad8c95f03b kconfig: Improve 'General setup' menu docs.
- Add documentation for COMPILER_GCC, and COMPILER_LLVM_CLANG.

 - SCANBUILD_ENABLE, CCACHE: Amend documentation.

 - SCANBUILD_REPORT_LOCATION: Document default dir, names of scan-build dirs.

 - INCLUDE_CONFIG_FILE: Add more verbose docs, show how to use it.

 - Fix typos/cosmetics/indentation, improve wording on some items.

Change-Id: I6b67b2c777868e4421405caaffe6631e69dddad2
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Reviewed-on: http://review.coreboot.org/893
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-04-17 10:56:16 +02:00
zbao f72237346d S3 code in coreboot public folder.
1. Move the Stack to high memory.
2. Restore the MTRR before Coreboot jump to the wakeup vector.

Change-Id: I9872e02fcd7eed98e7f630aa29ece810ac32d55a
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/623
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-04-16 18:22:47 +02:00
Stefan Reinauer 8e073829ec Add support for Intel Panther Point PCH
Change-Id: Iac3cd25b36493bb203e849674320e113cc5fce32
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/853
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-04 19:10:51 +02:00
Stefan Reinauer dfb098d359 Add DEBUG_TPM option to Debugging menu
instead of having to edit the source code of tpm.c

Change-Id: I519d9ada14dd383e668a2da4219e5373a24c7c3d
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/757
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-30 17:56:22 +02:00
Stefan Reinauer 3008bbadcb Add TPM support to coreboot
and initialize the TPM on S3 resume

This patch integrates the TPM driver and runs TPM resume upon an ACPI S3
resume without including any other parts of vboot.

We could link against vboot_fw.a but it is compiled with u-boot's CFLAGS
(that are incompatible with coreboot's) and it does a lot more than we
want it to do.

Change-Id: I000d4322ef313e931e23c56defaa17e3a4d7f8cf
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/731
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-30 02:04:20 +02:00
Stefan Reinauer b89a761a63 Add Google ChromeOS vendorcode directory
... and hook it up in Kconfig. More code to come.

Change-Id: I24542d8ef97e2bce112c3aface681ceeb1a7c061
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/813
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-30 01:59:38 +02:00
Vadim Bendebury 9202473d07 Add a config flag to enable time stamp collection
Add a new flag, make it dependent on EARLY_CBMEM_INIT

Change-Id: Idbebcaf298238f31a73e9eb4a9af7b03e857bc74
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/712
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2012-03-28 20:43:36 +02:00
Vadim Bendebury e6b6aff28a Introduce config option to initialize CBMEM early.
We want to be able to communicate information between rom and ram
stages of coreboot. This configuration option will be used to
compile such ability in.

Change-Id: I6736fdc264ecd0b63369b28462d7bb96e4c2b012
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/710
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-28 20:28:05 +02:00
Rudolf Marek 6588802fa7 Disable the GDB stub by default
I would prefer to see the exception dump on serial rather than cryptic
GDB protocol.

Change-Id: Ib25513d33e6a31da24586fecb00adb5206bb43bd
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/811
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2012-03-26 16:06:21 +02:00
Stefan Reinauer aff6dc2149 Move SeaBIOS output out of coreboot source tree
Make sure SeaBIOS build files live under $(OUT) instead of
in the source tree.

Change-Id: I7d357773e32bc25ba7e7eae3fb6ddc31feb413ec
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/552
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-02-07 00:21:03 +01:00
Patrick Georgi a31bb0779a Unify ID_SECTION_OFFSET and mark it deprecated
We used to put the id section at -0x10, with some boards overriding
this to avoid collisions with romstraps.
Hardcode the location at -0x80, at the possible expense of some space
(0x70 bytes).
This also makes the section easier to find in a binary image.

At some point, CONFIG_ID_SECTION_OFFSET can be removed, so this option
is moved to src/Kconfig.deprecated_options.

Change-Id: I6ce2d6e94e57717939bda070bfe0c9df80ca2a89
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/549
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-01-18 11:21:39 +01:00
Stefan Reinauer c1efb90384 refactor vesa mode setting code and bootsplash code
- adds possibility to set a vesa mode without showing a bootsplash
- make bootsplash / mode setting code available in real mode.

Change-Id: I0045c9d75757657f4ce531889593102ea1e39ce5
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/256
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13 20:00:50 +02:00
Rudolf Marek 7f0e93060e Add support for the tracing infastructure in coreboot.
The compiler is forced to emmit special functions on every
entry/exit of the function. Add a compile time option
to support it. Function entries will be printed in
the console. The CONFIG_TRACE has more documentation.

Patch for userspace tools will follow.

Change-Id: I2cbeb3f104892b034c8756f86ed05bf71187c3f3
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/178
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-07 01:26:47 +02:00
Sven Schnelle 164bcfdd1b Add automatic SMBIOS table generation
Change-Id: I0ae16dda8969638a8f70fe1d2e29e992aef3a834
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/152
Tested-by: build bot (Jenkins)
2011-08-26 20:08:52 +02:00
Cristian Măgherușan-Stanciu 9f52ea4c3c added a config option for ACPI debugging
Change-Id: Ie6296f5652196c6258aa6902d84dd86c17e224cb
Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Reviewed-on: http://review.coreboot.org/36
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2011-07-02 00:49:53 +02:00
Cristian Măgherușan-Stanciu d367b00c5b Add the coreboot config to CBFS
The CBFS will contain a new file, named 'config' of type 'raw' that is a
stripped-down version of the .config file that was used to build the
current coreboot image. For space savings, all the comments and empty
lines were removed from the original config, except for one that lists
the coreboot git revision that's built into the image.

This is done in order to easily reproduce the work of  someone else when
only having their ROM image. In theory the reproduce could even be
automated by a new dedicated make target.

This should work even with abuild now.

Change-Id: I784989aac0227d3679d30314b06dadaec402749e
Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Reviewed-on: http://review.coreboot.org/46
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-22 06:43:23 +02:00
Sven Schnelle 8eee19d0ea Add option 'compress ramstage'
Add an option to make compression of ramstage configurable. Right now
it is always compressed. On my Thinkpad, the complete boot to grub takes
4s, with around 1s required for decompressing ramstage. This is probably
caused by the fact the decompression does a lot of single byte/word/qword
accesses, which are really slow on SPI buses. So give the user the option
to store ramstage uncompressed, if he has enough memory.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6552 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-02 19:53:04 +00:00
Stefan Reinauer 4885daadb3 Add support for memory mapped UARTs to coreboot and add the OXPCIe952 as an
example.

This newer version reflects the recent changes to further simplify the console
code and partly gets rid of some hacks in the previous version.

Signed-off-by: Stefan Reinauer <reinauer@google.com>
Acked-by: Peter Stuge <peter@stuge.se>                                                                                                                                          



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6544 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-26 23:47:04 +00:00
Stefan Reinauer e50952f532 add FILO easy payload option
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6504 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-15 03:34:05 +00:00
Stefan Reinauer d85400d805 Handle drivers/ equally to any other sub directory.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6503 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-15 03:30:03 +00:00
Sven Schnelle 91321028ec Use subsystem id from devicetree.cb instead of Kconfig and move
all boards to the new config scheme.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6421 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-01 19:58:47 +00:00
Sven Schnelle 7592e8bd9c Add new ec subdir for Embedded Controllers and common ACPI EC support
Adds a new src/ec subdir for embedded controllers (mostly found in laptops)
and converts Getac P470 and Roda RK886EX to use the new ACPI EC instead
of having their own copies of those functions.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6304 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-27 11:43:03 +00:00
Stefan Reinauer f1939bb29b Per default, use SeaBIOS payload instead of no payload.
Add choice to use stable or master version of seabios repository

Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6223 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-30 17:39:50 +00:00
Stefan Reinauer bccbbe6b69 The same mechanisms are used for normal and fallback images.
Hence drop the FALLBACK_ prefix

Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6204 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-19 21:20:14 +00:00
Stefan Reinauer 8aedcbc436 - Fix shortcoming in Kconfig when handling multiple "choice"s
- move some variables where they belong

Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6186 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-16 23:37:17 +00:00
Stefan Reinauer 8677a23d5b After this has been brought up many times before, rename src/arch/i386 to
src/arch/x86. 

Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6161 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-11 20:33:41 +00:00
Peter Stuge 5015f79857 Ensure that config options hidden by r6054 have defaults, and fix MALLOCDBG()
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6055 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-10 02:00:32 +00:00
Uwe Hermann a953f371dd Debugging facility improvements.
- Hook up malloc() debug code via CONFIG_DEBUG_MALLOC. Only show it in
   menuconfig if at least DEBUG or SPEW are selected as loglevel, as this
   code does additional printk(BIOS_DEBUG, ...) calls which would otherwise
   not be visible anyway.

 - Similarly, make DEBUG_CAR and REALMODE_DEBUG only visible if thr DEBUG or
   SPEW loglevel is selected.

 - Get rid of a custom "debug" macro, use printk() as usual.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6054 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-10 00:14:32 +00:00
Peter Stuge 51eafdeae6 Enable or disable the power button in Kconfig
Some mainboards need to disable the power button to avoid turning off
right after being turned on, while other boards ship with a jumper over
the power button and should allow the user to configure the behavior.

This adds infrastructure in the form of four mutually exclusive options
which can be selected in a mainboard Kconfig (power button forced on/off,
and user-controllable with default on/off) and one result bool which
source code can test. (Enable the button or not.)

The options have been implemented in CS5536 code and for all mainboards
which select SOUTHBRIDGE_AMD_CS5536, but should be used also by other
chipsets where applicable. Note that if chipset code uses the result
bool ENABLE_POWER_BUTTON, then every board using that chipset must
select one out of the four control options in order to build.

All touched boards should have unchanged behavior, except
pcengines/alix1c, traverse/geos and lippert/hurricane-lx where the
power button can now be configured by the user.

Build tested for alix1c, alix2d, hurricane-lx and wyse-s50. Confirmed
to work as advertised on alix1c both with button enabled and disabled.

Includes additional traverse/geos changes from Nathan and
lippert/hurricane-lx changes from Jens to correctly use the new
feature on those boards.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Aurelien Guillaume <aurelien@iwi.me>
Acked-by: Nils Jacobs <njacobs8@hetnet.nl>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5948 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-13 06:23:02 +00:00
Jonathan Kollasch e5b7507882 Remove duplicate line from pci_ids.h.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5920 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-07 23:02:06 +00:00
Patrick Georgi e82618d037 Move CACHE_AS_RAM_ADDRESS_DEBUG out of romstage.c into Kconfig,
rename it slightly, make it visible only on relevant northbridges,
drop it entirely from via boards (as they seem to have picked it
up from AMD code without using it themselves), and make it
default to false for all boards.

Some romstages used to set this to "true" (ie. "print debug output"),
but I didn't follow up on it in Kconfig - if you need it to debug CAR,
enable it yourself.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5898 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-01 14:50:12 +00:00
Myles Watson 6c9bc01b0e Make a Kconfig option for debugging output from realmode emulation. Trivial.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5783 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-07 22:30:15 +00:00
Jens Rottmann b3f8090f4e drop three unneeded config variables:
- HAVE_HIGH_TABLES
- HAVE_LOW_TABLES
- FALLBACK_SIZE

Jens Rottmann sent an almost identical patch at the same time, so
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5745 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-27 09:36:41 +00:00
Jens Rottmann 0d11f2db1f CONFIG_DEBUG_RAM_SETUP and CONFIG_DEBUG_SMBUS are only available if the board /
chipset support it.  But this involves a long list of 'depends', which you have
to remember updating manually.  Converted this into HAVE_... properties, which
will be inherited automatically if someone copies a chipset to create a new
one.

Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5743 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-26 12:46:02 +00:00