Commit Graph

17735 Commits

Author SHA1 Message Date
Patrick Rudolph d4c53e3fdd nb/intel/sandybridge/raminit: Do code cleanup
Calculate the value from current DDR frequency.

Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16).

Change-Id: I57ffbfeb291fc2fede278d18527993e7432e9bd8
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15184
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-06-20 21:55:54 +02:00
Patrick Rudolph 4307835d26 arch/x86/smbios: Add DRAM manufacturer
Add Ramaxel DRAM manufacturer id.

Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16).
The manufacturer name shows up in dmidecode.

Change-Id: I14cdc82c09f0f990e2ba18083748d11d79e53874
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15183
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-20 21:48:32 +02:00
Patrick Rudolph 577aad6f13 include/device/dram/ddr3: Add additional frequencies
IvyBridge memory controller supports more frequencies than SandyBridge.
Required for future patches.

Change-Id: I0bcb670c20407ec0aec20bae85c4cbe6ccc44b16
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15182
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-06-20 21:46:58 +02:00
Patrick Rudolph b7b1b2884f nb/intel/sandybridge/raminit: Do code cleanup
Simplify calculation of value.

Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16).

Change-Id: I3ecd12c431b46a8d2218f33d7eb3e10de3bcd61d
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15181
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-20 21:44:50 +02:00
Patrick Rudolph 7bddd30e94 nb/intel/sandybridge/raminit: Allow 933Mhz on Lenovo devices
Set max_mem_clock_mhz in devicetree to 933Mhz.
Allows to run the memory at up to DDR3-1866.

The same frequency was allowed within the first vendor bios,
but Lenovo than decided to limit it to DDR3-1333.

Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16).

The RAM is now running at DDR3-1600 instead of DDR3-1333.
This gives about 4% performance increase in glmark2 using the
Intel GPU.

Change-Id: If15be497402d84a2778f0434b6381a64eda832d6
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15158
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-20 21:44:15 +02:00
Arthur Heymans 4089a17cb9 amd/fam_10h-fam_15h: allow building without microcode updates
CPU_MICROCODE_MULTIPLE_FILES relies on SUPPORT_CPU_MICROCODE_CBFS,
which is not set if CPU_MICROCODE_CBFS_NONE is set.
This makes selecting CPU_MICROCODE_MULTIPLE_FILES conditional.

Change-Id: I0c28f99a1b868bbf90a6f048cce3bea4ff849f76
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/15259
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-06-20 19:28:29 +02:00
Kyösti Mälkki e6bab8fb91 amd/geode: Fix comment about ACPI S3
As RAMTOP gets removed, comment becomes inaccurate.

Change-Id: Iaf25b88a4065d15c0c0682425b1d033e4a36590f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15237
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-20 18:49:26 +02:00
Kyösti Mälkki d71cfd2041 VIA C7 NANO: Fix early MTRR setting
It would not be possible to set MTRR for range 1MiB to 4MiB.
Our RAMTOP is power of 2 and enabling cache for bottom
1MiB should cause no problems.

Change-Id: I3619bc25be60f42b68615bfcdf36f02d66796e02
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15238
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-20 18:43:30 +02:00
Kyösti Mälkki 4b86314495 intel/broadwell: Remove old USBDEBUG backup store in CAR
Required EHCI state is maintained as a CAR_GLOBAL to have it
properly migrated.

Change-Id: I8df413bec6faae4952670710c8ac804e0331c966
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15236
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-06-19 05:21:50 +02:00
Kyösti Mälkki c6986fac77 emulation/qemu-i440fx qemu-q35: Asmlinkage for romstage main()
Change-Id: I66238525c5c4d97313a589373144741f1be97483
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15226
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-06-18 20:05:01 +02:00
Kyösti Mälkki e325b223a2 intel: Fix romstage main() with asmlinkage
Backport from haswell.

Change-Id: I585639f8af47bd1d8c606789ca026c6d2d0cc785
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15225
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-18 20:02:26 +02:00
Kyösti Mälkki 5276941c8b AMD boards: Fix romstage main() declaration
Boards incorrectly used intel include file for AMD board.

Change-Id: I6d3172d1aa5c91c989a6ef63066a7cd6f70013f5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15232
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-18 20:01:48 +02:00
Kyösti Mälkki e93e7102cf dmp/vortex86ex: Drop excessive include
Change-Id: Ieeae96d53627768de98006074c8c8e826b1741fc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15233
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-18 20:00:58 +02:00
Kyösti Mälkki 831a7ef541 intel/cache_as_ram_ht.inc: Fix include
Reference to CACHE_AS_RAM was from the days we had
romcc boards using socket_mPGA605.

Change-Id: If397db83a01adeda4dd18d8b4c6e89bf0984264a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15224
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-18 20:00:16 +02:00
Kyösti Mälkki 9d2762ca6f intel cache_as_ram: Fix typo in comment
Change-Id: I2539e490e160e01cab2ad8d2086d2f242a88c640
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15223
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-18 19:59:38 +02:00
Zhao, Lijian e813c15443 google/reef: Update EMMC DLL setting in all mode
Update tuned DLL setting on all other mode, including SDR12
SDR25 and DDR50.

Change-Id: I1eb85ac6080fd78f63816d3fa9ef482484bd9f94
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/15210
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-17 21:30:45 +02:00
Antonello Dettori fda691ef53 cbfstool: Extract payload in ELF
Implement function that automatically converts a SELF payload,
extracted from the CBFS, into an ELF file.

The code has been tested on the following payloads:
Working: GRUB, FILO, SeaBIOS, nvramcui, coreinfo and tint
Currently not working: none

Change-Id: I51599e65419bfa4ada8fe24b119acb20c9936227
Signed-off-by: Antonello Dettori <dettori.an@gmail.com>
Reviewed-on: https://review.coreboot.org/15139
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-17 20:44:28 +02:00
Antonello Dettori 3bded7db7e elfwriter: Fix multi-phdrs ELFs parsing
Allow to write multiple phdrs, one for each non-consecutive section
of the ELF.
Previously it only worked for ELFs contaning a single
program header.

Change-Id: If6f95e999373a0cab4414b811e8ced4c93c67c30
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/15215
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-17 20:04:27 +02:00
Kyösti Mälkki d72cc4111b intel/model_206ax: Move platform specific defines
Change-Id: I3c517fc55dd333b1a457324f1d69aeb6f70acec2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15197
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-06-17 00:22:10 +02:00
Kyösti Mälkki a969ed34db Move definitions of HIGH_MEMORY_SAVE
This is more of ACPI S3 resume and x86 definition than CBMEM.

Change-Id: Iffbfb2e30ab5ea0b736e5626f51c86c7452f3129
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15190
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-06-17 00:19:08 +02:00
Kyösti Mälkki 465eff61f4 Fix some cbmem.h includes
Change-Id: I36056af9f2313eff835be805c8479e81d0b742bf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15196
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-06-17 00:18:28 +02:00
Kyösti Mälkki bec853e9ad Define RAMTOP for x86 only
This Kconfig is deprecated, new platforms need to locate
ramstage stack in CBMEM instead.

Change-Id: I20ece297302321337cc2ce17fdef0c55242a4fc3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15189
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-06-17 00:17:53 +02:00
Furquan Shaikh e51c20bf2c ifwitool: Calculate checksum for subpart_dir
Checksum is calculated by using 2s complement method. 8-bit sum of the
entire subpart directory from first byte of header to last byte of last
partition directory entry.

BUG=chrome-os-partner:53508

Change-Id: I991d79dfdb5331ab732bf0d71cf8223d63426fa8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15200
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-16 19:38:36 +02:00
Furquan Shaikh 4b373ca8a0 google/reef: Add NVRAM and LEGACY sections to chromeos.fmd
Now that the flash size is increased to 16MiB, add RW_NVRAM and
RW_LEGACY sections to chromeos.fmd file.

BUG=chrome-os-partner:54390

Change-Id: I6c79d35295c4bc774f05f8045ac920474d7a791f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15192
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-16 08:15:06 +02:00
Furquan Shaikh 2c4a60da35 google/reef: Update flash size to 16MiB
Use entire 16MiB flash size on reef. Adjust SIGN_CSE region
accordingly.

BUG=chrome-os-partner:54390

Change-Id: I94de509bdb2aa94625814123bf4d9758bfa37fc9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15191
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-16 08:14:39 +02:00
Prabal Saha 5a3833d2d3 mb/google: Remove whitespace from devicetree on bdw boxes.
Change-Id: I189836282b4ad084fbbb74199b24505f5e141b60
Signed-off-by: Prabal Saha <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/15207
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins)
2016-06-16 06:46:13 +02:00
Matt DeVillier f09d39db4e google/rikku: Upstream Acer Chromebox CXI2
Migrate google/rikku (Acer Chromebox CXI2) from Chromium tree to
upstream, using google/guado as a baseline.

original source:
branch firmware-rikku-6301.110.B
commit 2e71207 [CHERRY-PICK: broadwell: Update to microcode 0x1F]

TEST=built and booted Linux on rikku with full functionality

blobs required for working image:
VGA BIOS (vgabios.bin)
firmware descriptor (ifd.bin)
Intel ME firmware (me.bin)
MRC (mrc.bin)
external reference code (refcode.elf)

Change-Id: Iba618a0b2cf2d613f6429b3e7606e0b47fa97a4d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/12802
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-16 01:43:42 +02:00
Furquan Shaikh 1f40ae2d74 intel/apollolake: Correct the offsets in gnvs
Offsets start from 0 instead of 1. Fix this in the gnvs definitions.

BUG=chrome-os-partner:54342

Change-Id: Id6766a8766ef430d19ffcb801bfab43d38de37db
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15180
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-15 18:47:34 +02:00
Furquan Shaikh d01f5a01e6 intel/apollolake: Add CBMEM console to GNVS
CBMEM console stores all the console logs in CBMEM. Address of this
location in CBMEM where console logs are stored needs to be passed up to
OS using GNVS.

1. Add CBMC to GNVS fields in globalnvs.asl
2. Add cbmc member to global_nvs_t structure in nvs.h
3. Initialize gnvs->cbmc to address of cbmem console

BUG=chrome-os-partner:54342

Change-Id: Idcd4573e626fa433c1623bdcbe29921de64539b2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15177
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-15 17:56:52 +02:00
Rolf Evers-Fischer eb8b7d6ef4 ifwitool: Fix calculation of dst_size
Change-Id: I07523252eacffb323e2bb54c306f5e9ac83e4cbd
Signed-off-by: Rolf Evers-Fischer <embedded24@evers-fischer.de>
Reviewed-on: https://review.coreboot.org/15162
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-15 17:37:17 +02:00
Andrey Petrov 82a612202b drivers/intel/fsp2_0: Add FSP return types for reset
FSP methods may require reset under certain conditions. That is indicated
by returning specific return code. Add the missing return status codes.

BUG=chrome-os-partner:54149
BRANCH=none
TEST=none

Change-Id: I460353c5f835548a98255bd3e11dbfd08260ea52
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15185
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-14 23:57:58 +02:00
Elyes HAOUAS d450609145 Added CL7 support
according to "JEDEC_DDR2_SPD_Specification_Rev1.3.pdf"
Annex J: Serial Presence Detects for DDR2 SDRAM (Revision 1.3)
page 16 and page 60, CL7 support added

Change-Id: I22aaf064ab8767755f74dfdb44e32d13fc61b2c4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/14976
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-06-14 23:54:51 +02:00
Furquan Shaikh 579fdb4910 google/reef: Correct use of globalnvs.asl
Use the correct globalnvs.asl from apollolake.

BUG=chrome-os-partner:54342

Change-Id: I1a5b8f61c540bdb2668b532f032350d8e4d48010
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15178
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-14 18:26:12 +02:00
Zhao, Lijian e9cf848dad google/reef: Update EMMC DLL settings
Update EMMC DLL setting for reef board, after that system can
boot up into EMMC successfully.

BUG=chrome-os-partner:54228
TEST=Boot up into EMMC and check with Rootdev

Change-Id: I614cd624dce9069c5565599a955f87906bcea53b
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/15156
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-14 18:05:47 +02:00
Lee Leahy ce9e21a0ea soc/intel/quark: Add C bootblock
Add a bootblock which builds with C_ENVIRONMENT_BOOTBLOCK selected.
This is the first piece in supporting FSP 2.0.  Move esraminit from
romstage into the bootblock.  Replace cache_as_ram with
car_stage_entry.S and code in romstage.c

TEST=Build and run on Galileo Gen2

Change-Id: I14d2af2adb6e75d4bff1ebfb863196df04d07daf
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15132
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-12 14:52:44 +02:00
Lee Leahy 6c3c31e49d bootblock: Declare common bootblock_pre_c_entry routine
Enable uses of a common bootblock_pre_c_entry routine.  Pass in TSC
value as a uint64_t value.

TEST=Build for amenia and Galileo Gen2

Change-Id: I8be2e079ababb2cf1f9b7e6293f93e7c778761a1
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15124
Tested-by: build bot (Jenkins)
Reviewed-by: Lee Leahy <lpleahyjr@gmail.com>
2016-06-12 14:52:17 +02:00
Aaron Durbin 065b683618 soc/intel/common: don't infinitely recurse in busmaster_disable_on_bus()
If a bridge has the primary bus equal to the secondary bus the
busmaster_disable_on_bus() will infinitely call itself. Avoid the
inifinite recursion by checking current bus number against the
secondary bus number.

BUG=chrome-os-partner:54262
TEST=Ran on reef. Able to actually get the chipset to assert SLP_Sx
     signals which means no more infinite recursion.

Change-Id: I52b21fbba24e6a652ea8f9f87f5f49f60109c8f2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15157
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-06-12 12:55:57 +02:00
Aaron Durbin 1ee6f0bdc8 soc/intel/apollolake: save GNVS pointer to SMM handler
Like other boards there will likely be information needed from
GNVS in the SMM handler. Therefore, it's important that the point
is stashed accordingly.

BUG=chrome-os-partner:54275
TEST=Noted GNVS messages from SMM console on reef.

Change-Id: If12b69731330a1e0af7f8fe880635e5ffd02d715
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15152
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-12 12:55:04 +02:00
Aaron Durbin ac57f084a2 soc/intel/apollolake: allow DEBUG_SMI to work
The UART support is needed in SMM in order for DEBUG_SMI to
function.

BUG=chrome-os-partner:54262
TEST=Ran on reef with DEBUG_SMI enabled. Can observed SMI messages.

Change-Id: Ibd6b12e27d5776046b400adf72f24133b9e54af8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15151
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-12 12:54:17 +02:00
Aaron Durbin a554b71e32 soc/intel/apollolake: provide fake PM1 SMI status bit
It appears that PM1 is not wired up to the SMI status register, but
it does definitely cause SMIs to trigger. Therefore, provide a fake
PM1 status bit by checking the power button status when SMI status
is indicating no status as well as the PM1 control indicating that
SCI mode is not enabled.

BUG=chrome-os-partner:54262
TEST=Smashed power button on reef to cause SMI in firmware. No longer
     loops infinitely with constant SMIs firing.

Change-Id: I9aa1b5f79b651cbc19a2d3353d9ef65429386889
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15155
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-12 12:52:28 +02:00
Aaron Durbin 7929dd02e6 soc/intel/apollolake: add SMI status bit definitons and use them
Provide the bit definitions for the SMI status register. Also,
utilize them which means deleting some of the handlers that can't
exist because there are no status bits.

BUG=chrome-os-partner:54262

Change-Id: I389c7cb3cad01ba0eca52a337ffee352a2010bfa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15154
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-06-12 12:50:08 +02:00
Patrick Rudolph 266a1f794d nb/intel/raminit (native): Read PCI mmio size from devicetree
Instead of hardcoding the PCI mmio size read it from devicetree.
Set a default value of 2048 MiB and 1024MiB for laptops without
discrete graphics.

Tested on Sandybridge Lenovo T520.

Change-Id: I791ebd6897c5ba4e2e18bd307d320568b1378a13
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15140
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-12 12:48:44 +02:00
Furquan Shaikh e7f35cd292 ifwitool: Do not calculate checksum for subpart_dir
1. The checksum method that was documented is not correct. So, no use
filling in a value based on wrong calculations. This can be added back
once updated information is available.
2. Checksum does not seem to affect the booting up of SoC. So, fill in 0
for now.

Change-Id: I0e49ac8e0e04abb6d7c9be70323612bdef309975
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15145
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-12 12:45:25 +02:00
Furquan Shaikh fe42b11cdf ifwitool: Correct pack order and header order
Update pack and header order and mark the entries as mandatory and
recommended w.r.t. ordering (mandatory = essential for booting,
recommended = okay to change, but this config is tested and known to work).

Change-Id: Ia089bdaa0703de830bb9553130caf91a3665d2c4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15144
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-12 12:44:23 +02:00
Jonathan Neuschäfer d15e9aaa48 riscv-spike: Replace custom UART with a memory-mapped 8250
Since the HTIF is a non-standard interface, and coreboot already has a
8250 driver, I started implementing an 8250 core for spike[1].

[1]: https://github.com/riscv/riscv-isa-sim/pull/53

Change-Id: I84adc1169474baa8cc5837358a8ad3d184cfa51b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15150
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-06-12 12:43:37 +02:00
Jonathan Neuschäfer 1282b8d996 arch/riscv: Compile with -mcmodel=medany
In the default (medlow) code model, pointers are loaded with a lui, addi
instruction sequence:

	lui	a0, 0xNNNNN
	addi	a0, a0, 0xNNN

Since lui sign-extends bits 32-63 from bit 31 on RV64, lui/addi can't
load pointers just above 0x80000000, where RISC-V's RAM now lives.

The medany code model gets around this restriction by loading pointers
trough auipc and addi:

	auipc	a0, 0xNNNNN
	addi	a0, a0, 0xNNN

This way, any pointer within the current pc ±2G can be loaded, which is
by far sufficient for coreboot.

Change-Id: I77350d9218a687284c1337d987765553cf915a22
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15148
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-06-12 12:42:32 +02:00
Jonathan Neuschäfer f934efc9f8 arch/riscv: Add misc.c to bootblock/romstage to get udelay()
The uart8250mem driver needs it.

Change-Id: I09e6a17cedf8a4045f008f5a0d225055d745e8db
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15147
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-06-12 12:41:48 +02:00
Jonathan Neuschäfer a9067c6ec0 arch/riscv: copy read/write8/16/32 from x86
Change-Id: I12de8f82499074f0fbbc1c09210b00c6a9614c1b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15146
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-12 12:40:51 +02:00
Jonathan Neuschäfer 4ac82401a8 arch/riscv/trap_util.S: Use "li" pseudo-instruction to load a constant
Change-Id: I9759771fa6fc708d7d97509c5f5e0cefb8ab4c96
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14962
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-06-12 12:31:06 +02:00
Furquan Shaikh 6f762171de intel/apollolake: Use custom reset calls
Due to USB LDO issue in current steppings, cold reboot needs to be
temporarily disabled. Thus, hard_reset call should be the same as
soft_reset.

Once future steppings are available INTEL_COMMON_RESET can be enabled again.

Change-Id: If0ec56db3864d500acc93d2b363a78a6cd7632da
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15143
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-12 12:30:15 +02:00