Fill SMBIOS type 9 fields for both sarien and arcada platform.
BUG=b:129485789
TEST=Boot up into OS and check with dmidecode -t 9 to we do have entry.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I47a697131b7aeeb64e0c4b4c0556842f1cb1b02e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use the devicetree values for type 9 slots.
Tested on Lenovo T520.
Change-Id: I1961d8af2d21f755ff52ad58804ea9b31d2a5b9b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Ignore NONE devices in dev_is_active_bridge that are commonly used to
indicate hotplug capable ports.
Tested on Lenovo T520:
The empty ExpressCard Slot is no longer marked as active bridge.
Change-Id: I23347270aaab17647023969091ce4bcdd41dd57a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Add the new field 'smbios_slot_desc', which takes 2 to 4 arguments.
The field is valid for PCI devices and only compiled if SMBIOS table
generation is enabled.
smbios_slot_desc arguments:
1. slot type
2. slot lenth
3. slot designation (optional)
4. slot data width (optional)
Example:
device pci 1c.1 on
smbios_slot_desc "21" "3" "MINI-PCI-FULL" "8"
end # PCIe Port #2 Integrated Wireless LAN
Tested on Lenovo T520.
Change-Id: If95aae3c322d3da47637613b9a872ba1f7af9080
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
SMM final locks the SPI BAR, which causes flashconsole to hang.
Re-init it like SMM does with CONFIG_SPI_FLASH_SMM.
Change-Id: Ib802d7ee32f1fb0a68a84b0280480dcaefa9831f
Signed-off-by: Dan Elkouby <streetwalkermc@gmail.com>
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Checking the PrimaryDisplay parameter (added by patch with Change
Id Ie3f9362676105e41c69139a094dbb9e8b865689f) isn`t required. The
display connected to PEG works even if IGD is primary for output
image and at the same time this device is disabled
Tested on Asrock H110M-DVS with NVIDIA GTX 1060 GPU
Payload: tianocore edk2-stable201811-216-g51be9d0
Change-Id: I5615597881a151bb004676d914fbf40874ac1f68
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32615
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The DRAM base memory should be calculated even if IGD isn`t defined
in the board device tree
Tested on Asrock H110M-DVS
Change-Id: I3da51473e6c06da803bd969a4a6dff792c18f962
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
`pei_data` was a struct with blob parameters from pre-FSP times.
Somehow, it sneaked into upstream FSP1.1 support (probably because
early board ports were written for a different blob). When added
upstream, its usage was already perverted. It was declared at SoC
level but mostly used to pass mainboard data from mainboard code
to itself and FSP data from FSP code to itself. Now that no board/
SoC code uses it anymore, we can finally drop it.
Change-Id: Ib0bc402703188539cf2254bdc395cca9dd32d863
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The SoC specific `struct pei_data` was filled with values that were
never consumed anywhere again. So just merge the used code into
`romstage.c` where it's effectively used.
Change-Id: I499b3cfcdd5400ea132749555d433a2d8a9471a3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The SoC specific `struct pei_data` was filled with values that were
later only consumed by the mainboard code again. Avoid jumping through
this hoop and fill FSP UPDs directly.
Change-Id: I040f4a55b4f4bad3f6072920e5e2eceded4cb9bb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The SoC specific `struct pei_data` was filled with values that were
later only consumed by the mainboard code again. Avoid jumping through
this hoop and fill FSP UPDs directly.
The provided solution locates the SPD data in CBFS again to fill SMBIOS
tables. This is not perfect. OTOH, this code isn't mainboard specific
and doesn't belong here anyway.
Change-Id: Ib6103d5b9550846fe17c926631a013ff80b9598f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
`chip.h` is usually used as devicetree interface.
Change-Id: Ied30927d68927b86758a84ccf3f5fbd8cce632f1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32592
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SoC specific `struct pei_data` was filled with values that were
later only consumed by the mainboard code again. Avoid jumping through
this hoop and fill FSP UPDs directly.
Change-Id: I399dd89f85ccea43fdf90bd895e71324f4b409cc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The SoC specific `struct pei_data` was filled with values that were
later only consumed by the mainboard code again. Avoid jumping through
this hoop and fill FSP UPDs directly.
Change-Id: Ibc013ccea9f83ef29f22fe2da4c0d12096308636
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
These are part of a common concept and not SoC specific.
Change-Id: I9cb218d7825bd06a138f7f5d9e2b68e86077a3ec
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
This reverts commit c4ab50cdde.
Reason for revert:
vboot recently was changed so that -Wtype-limits fails, and that
was just brought upstream. Since vboot internals are more likely
to be used elsewhere while -Wtype-limits is less critical, revert
this until vboot is resolved, then bring -Wtype-limits back again.
Change-Id: I9cce10462b9e57189513fa49e11fd27ebe35ba51
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32670
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It was only used locally.
Change-Id: Iaaad760e8ceca62655f5448c30846cf11959e8e1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
The MacBook Air 4,2 uses eDP, according to the schematics.
Change-Id: Ifc98eab343fd89b8512e92e01fddf34ef8447d5f
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32606
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id 304aa429:
2019-03-12 10:38:56 -0700 - (futility: updater: Unit test for preserving sections using FMAP flags)
to commit id e7edff66:
2019-05-03 07:02:32 -0700 - (vboot: implement DISPLAY_INIT context and SD flag)
This brings in 45 new commits.
Change-Id: I7493e43bddc553f9724de46130ccb4cb44e18573
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Turn off camera power when s0ix for power saving.
BUG=b:129177593
TEST= measure camera power comsumption is 0mV under s0ix
Change-Id: I5a9b7ec1e95cc9931d8d5f2dc1254805c9d0ffed
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
A13 and A15 need to set low before H12 reset. Change
the program sequence for fit HW requirement.
BUG=b:131876963
TEST=boot up and check SD card functional
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I2f1752070f24833aaaab75dea8493caf2ed7f157
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Remove use of deprecated GoogleBinaryBlockHeader struct, and
replace with vb2_gbb_header.
BUG=b:124141368, chromium:954774
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: Iee3bd877cb1791a689efdeabda324f43f7d0c6f2
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Sunrise Point-LP is used on Skylake and KabyLake platforms,
but the PCH IDs differ.
This commit adds the PCH IDs for Skylake mobile platforms
and renames the Kabylake macros to distinguish them.
Used Intel documents:
- 332995-001EN (I/O datasheet vol. 1)
- 332996-002EN (I/O datasheet vol. 2)
Change-Id: Id46224fcc44b06c91cbcd6c74a55c95e1de65ec6
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The file is no longer used by any code. Remove it.
Change-Id: I73f06cac11201dc37218d352ab995cf4f012c36a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Part of this checks whether tolum_base and cbmem_top are the same - however,
cbmem_top hasn't been initialised at the point where this call occurs.
Change the ordering to fix that.
Signed-off-by: Matthew Garrett <mjg59@google.com>
Change-Id: Ib89e0513bdc35c3751a9d4c2a2789a2836046789
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reset GPI Interrupt status and enable registers from ramstage instead of
bootblock so that it applies to devices in field.
BUG=b:130593883
BRANCH=octopus
TEST=Ensure that the Interrupt status & enable registers are reset
during the boot up when the system is brought out of G3, S5 & S3. Ensure
that the system boots fine to ChromeOS.
Change-Id: Ib11b580ceb23bd1fe789f549b667a8ced2d859a1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32534
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A hook for romstage is already existing but not for ramstage.
It's very useful for debugging as it allows to run code
for testing purposes by the mainboard. Also, it allows to
run configuration code or configure FSP options, which
don't have a devicetree option.
Change-Id: I9edc543943c5cbc696fc6c615cb77ef68294c980
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Remove the bridge enable step of accessing D14F0x64. This method for
enabling the bridge appears to be last present in the SB700 device.
Beginning in the SB800 (and all FCH, SoC devices), the enable is in
PMxEC[0]. Since the bridge is enabled in bootblock to allow port 80h,
there is no need to maintain it in ramstage.
Correct the device used for misc. configuration of the LPC bridge.
The #defined value removed is 14.0 but the settings are in 14.3.
TEST=Boot Grunt, check console and dmesg for errors and warnings
BUG=b:131862871
Change-Id: I078be974dc3c78c94cb7c0832518f21bac029ff2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Relocate the function to the more appropriate file.
Change-Id: I92a3e8d0461ae228f6c01567db159e2458de5f6b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This patch enables -Wtype-limits for the whole repository, which
disallows checking for a condition that must be always true or always
false based on type width (e.g. checking whether an unsigned variable is
negative or whether a 32-bit integer is larger than 4G). This helps
avoid easy to make and hard to find (because they often only affect
error paths) mistakes like
size_t size = fmap_read_area(...);
if (size < 0)
die("If only the compiler could've told me to use ssize_t instead");
Change-Id: I19edabfd092d09dad720e3fc47b44838163bfe25
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32536
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch fixes up all code that would throw a -Wtype-limits warning.
This sometimes involves eliminating unnecessary checks, adding a few odd
but harmless casts or just pragma'ing out the warning for a whole file
-- I tried to find the path of least resistance. I think the overall
benefit of the warning outweighs the occasional weirdness.
Change-Id: Iacd37eb1fad388d9db7267ceccb03e6dcf1ad0d2
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32537
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
I can't claim that I really understand what this code does, but it looks
like there are platforms that use code from lib/spd_bin.c without
enabling CONFIG_GENERIC_SPD_BIN. Some functions in that file contain
references to CONFIG_DIMM_MAX, so that option probably shouldn't depend
on CONFIG_GENERIC_SPD_BIN.
Change-Id: I041c52b6bd255e9a9920e5a101165ba5fc5fa6f3
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32548
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove the Librem 13v3 as a separate board; instead build a
single firmware image for the 13 v2/v3 boards.
Clean up Kconfig options:
- remove entries for 13v3 board
- fold entries into a single line where possible
- remove redundant MAINBOARD_VERSION option (will default to 1.0)
- remove unused microcode length/location (only needed for FSP CAR)
Test: build/boot Librem 13 v2/v3 boards with same image
Change-Id: Ic09b8ec5c576f4c4c48ef30ee3f60a4c2c286cd3
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The {read,write}_index functions expect a 32 bit value, as
do the bitwise operations.
Found-by: Coverity Scan #1229584
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Idc2bc46c899d5a4e8b089644dca076a88d97dd7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Make use of:
* southbridge/intel/common/rcba.h
* southbridge/intel/common/pmbase.c
* defines in pch.h
Get rid of dependency to DEFAULT_RCBA.
Tested on Lenovo T520 (Intel Sandy Bridge).
Still boots to OS, no errors visible in dmesg.
Change-Id: I879fce6a5bb80499e1986e618a1422a7aaa3a0c0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32066
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Run CPU at the highest freqency (1989MHz) to speed up the boot time.
BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui
Change-Id: I703ffcb99367f87e6792a72485f5634e0505e5ac
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32466
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When we increase voltages, it takes 200us for voltages to stablize.
BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui
Change-Id: I5f32035693b6084dbe763411c612ae5d1f7c9e48
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Updated GPP_A8 to be a GPI and SCI source, to support both wake and
notifications.
BUG=b:128941098
BRANCH=none
TEST=Compiles, simulated pen eject with PCH_INT_L signal. Both evtest
and waking from s0ix confirm this works. The output of /proc/interrupts
confirms the correct interrupt is triggered.
Change-Id: I080fb3cbfb3e2f55209ca31824b00ca820d70f78
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Lijian Zhao