Commit Graph

17248 Commits

Author SHA1 Message Date
Aaron Durbin f7dca0a275 arch/power8/tables: remove confusion over write_tables()
Apparently the memo was missed about the write_tables()
signature. Fix the confusion.

Change-Id: I63924be47d3507d2d7ed006a553414f4ac60d2f9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14420
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-21 16:07:30 +02:00
Furquan Shaikh 581c42807d soc/intel/apollolake: Set default memory type to uncacheable
Set the default memory type in MTRRCap register to 0. This ensures
that even if the MTRR Enable bit is set in MTRRCap register, the
default memory type is still uncacheable.

Change-Id: I63e7993f8b65dabbab60e7c1bb8d6d89ef4da9ee
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/14428
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-04-21 08:24:33 +02:00
Kyösti Mälkki defbdcf3e5 AGESA vendorcode: Fix type mismatch
Fix is required to compile AGESA ramstage without raminit.

Change-Id: I783883fa7a12e8a647aa432535bb990a47257e9b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14416
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
2016-04-21 07:39:13 +02:00
Stefan Reinauer e0383d2ce8 xcompile: support being called from payloads/external/.../.../
Change-Id: Icc1361fdd3a8369c4b442ce5b8807c549519c93a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14387
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-21 07:34:33 +02:00
Stefan Reinauer 479e31e090 imgtec/pistachio: Fix memlayout ASSERT with new binutils
With binutils 2.26 our memlayout ASSERT for mirrored SRAM regions
gets confused due to the lack of parentheses grouping the expressions.

This fixes the following issue:

    LINK       cbfs/fallback/bootblock.debug
    mipsel-elf-ld.bfd: bootblock and gram_bootblock do not match!
    mipsel-elf-ld.bfd: romstage and kseg0_romstage do not match!

Change-Id: Ib406e229b8a552d9ffc4538b55ee0269bfed62a8
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14440
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-04-21 07:16:06 +02:00
Noah Glovsky cc93ce79b1 mainboard/apple: add license headers
Change-Id: Id9487212411e5c237d26eb4e5663135f7d0720d1
Signed-off-by: Noah Glovsky <noah.glovsky@watershedschool.org>
Reviewed-on: https://review.coreboot.org/14425
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-21 00:07:45 +02:00
Noah Glovsky abe40e0664 mainboard/amd: add license headers
Change-Id: Ida8e81c88b2016d90cc8305edfb199143f859ec2
Signed-off-by: Noah Glovsky <noah.glovsky@watershedschool.org>
Reviewed-on: https://review.coreboot.org/14422
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-21 00:07:05 +02:00
Stef van Os cccef34155 intel/fsp_broadwell_de: fix SPD CBFS file type
File type for SPD in this soc is defined as CBFS_TYPE_RAW in Makefile,
but CBFS_TYPE_SPD in code.

Causes DDR SPD not to be loaded on memory down.

Tested on Prodrive Technologies Broadwell-D 1548 module:
http://prodrive-technologies.com/amc-ix5-intel-broadwell-de-platform/

Change-Id: I44525b4742b3f93d33f0c5bd9ed642c6fb06f23f
Signed-off-by: Stef van Os <stef.van.os@prodrive-technologies.com>
Reviewed-on: https://review.coreboot.org/14415
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: York Yang <york.yang@intel.com>
2016-04-20 23:37:29 +02:00
Bora Guvendik 57abb998a9 soc/intel/apollolake: add definitions for direct IRQ
Change-Id: Ife26f5cf6a06a1a5bf965bbeed7a740a990e8f7f
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/14399
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-20 19:12:17 +02:00
Zhao, Lijian d8d42c2f5f mainboard/amenia: add the inital files for amenia board
Add amenia board files

Change-Id: I6731a348b4c0550d3b9381adb5fb83719f90a5da
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/14352
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-20 18:51:18 +02:00
Jagadish Krishnamoorthy d68a13a602 soc/intel/apollolake: configure interrupt trigger mode
Provide trigger option to configure APIC, sci, smi, nmi interrupts.

Change-Id: I1b553fb4ed1b43aba62346f5b758f8d082606510
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/14353
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-20 18:50:24 +02:00
Andrey Petrov 60c64325cc vboot: Compile loader in postcar as well
Change-Id: Ide3202fca75c77ccebf17d61d93945ba7834a13b
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14398
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-20 18:47:11 +02:00
Iru Cai 736aa74faf add nvramcui as a secondary payload
Change-Id: Ie38a358ebd2d040ce32b3eeaeb664c568d4dc51e
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/14378
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2016-04-20 18:42:52 +02:00
Iru Cai e44b407b00 nvramcui: Update Makefile
* use crossgcc to build nvramcui
* build libpayload dependency

Change-Id: Ife3054aeb03b4da0568ad47f96c633460d6c07ae
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/14377
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-20 18:41:37 +02:00
Kyösti Mälkki ae29635876 AGESA vendorcode: Suppress maybe-uninitialized warnings
Compiling libagesa with -O2 would throws error on these.

Change-Id: I04afa42f0ac76677f859ca72f9df2e128762ad3c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14413
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-20 15:33:25 +02:00
Kyösti Mälkki 4dcbdb0ab9 AGESA vendorcode: Fix logic error
We have not really hit this error, due the test on AGESA_UNSUPPORTED
above.

Change-Id: I6e7d136a1bb46138cc347225bc4c82cfeaff385d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14394
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-20 15:31:46 +02:00
Kyösti Mälkki 318e2ac974 AMD CIMX: Drop unused code
We never define B1_IMAGE or B2_IMAGE. These are about building
CIMx as separate binary modules, while coreboot builds these into
same romstage or ramstage module.

Change-Id: I9cfa3f0bff8332aff4b661d56d0e7b340a992992
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14393
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
2016-04-20 15:31:18 +02:00
Alexander Couzens 0793afe913 mb/lenovo/x220: disable ME
The ME hangs, the lspci shows no memory and the linux kernel
tries to request irq 0 twice. After suspend-resume the linux
kernel warns about double used irq.

genirq: Flags mismatch irq 0. 00000080 (mei_me) vs. 00015a00 (timer)
mei_me 0000:00:16.0: request_threaded_irq failed: irq = 0.
dpm_run_callback(): pci_pm_resume+0x0/0xa0 returns -16
PM: Device 0000:00:16.0 failed to resume async: error -16

Change-Id: I56ef66388e58dddcfb858294ba274621c55fbef6
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/14309
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-04-20 00:26:06 +02:00
Martin Roth a53958098e crossgcc/Makefile.inc: Update jenkins-build-toolchain
Because the builders have the coreboot cross-compilers in their path,
the XGCCPATH variable needs to be set after building the new toolchain
before it will be used.

- Add $DEST/bin to $PATH if $DEST is set, add the default location
for toolchain builds otherwise.  Because the jenkins build image puts
the tools in the path, we ca
- Add KEEP_SOURCES option to help speed up compilation (Slightly).
- Log .xcompile for verification that the right toolchain was used.
- Verify that test-toolchain passes.

Change-Id: I7c270dab94be7e8f801d527169767018a24986e4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14231
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-20 00:24:47 +02:00
Martin Roth 7fae59b049 MAINTAINERS: Add maintainer for Pineview & x4x chipsets & boards
Change-Id: I3c34f6e69b3760a10e67bdc41c8ef0e629beb881
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14129
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-19 19:25:59 +02:00
Stefan Reinauer f4609f9abf drivers/ricoh: Switch to src/drivers/[X]/[Y]/ scheme
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make
them pluggable.

Change-Id: I3cf32ec58ba40db11fae3dda6dcb2375002e7cb4
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14052
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19 18:38:29 +02:00
Stefan Reinauer 56f19818dd drivers/generic: Switch to src/drivers/[X]/[Y]/ scheme
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make
them pluggable.

Change-Id: Ide0d48405d85ea2e889916f778e1556287651707
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14057
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19 18:38:06 +02:00
Stefan Reinauer fa45b52b09 drivers/aspeed: Switch to src/drivers/[X]/[Y]/ scheme
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make
them pluggable.

Change-Id: I8cf021ea5baff05eb5f84cc014612084afe3f858
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14053
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19 18:37:29 +02:00
Stefan Reinauer 0aeece7689 drivers/ati: Switch to src/drivers/[X]/[Y]/ scheme
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make
them pluggable.

Change-Id: Iba43630208be02603f4e0de5f62047bb3d23863a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14054
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19 18:37:20 +02:00
Stefan Reinauer 1211590ca3 drivers/emulation: Switch to src/drivers/[X]/[Y]/ scheme
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make
them pluggable.

Change-Id: I6e30a7be510c66fb1aa88314861d95f8ebe80377
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14056
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19 18:37:08 +02:00
Stefan Reinauer 1f83dd8fb6 drivers/i2c: Switch to src/drivers/[X]/[Y]/ scheme
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make
them pluggable.

Change-Id: Ia210e6832c18270043c0cb21b4881d9c802f3b2b
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14058
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19 18:36:54 +02:00
Stefan Reinauer c1e9d6b761 drivers/ics: Switch to src/drivers/[X]/[Y]/ scheme
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make
them pluggable.

Change-Id: I40373768595a085bba9a5c934794e128f396828b
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14059
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19 18:36:43 +02:00
Stefan Reinauer cb7041ff6b drivers/aspeed: Switch to src/drivers/[X]/[Y]/ scheme
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make
them pluggable.

Change-Id: I7a053ac1d8ecc3e443e91daeb406bae0b8c13323
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14060
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19 18:36:17 +02:00
Stefan Reinauer 27bcd6c9e8 drivers/sil: Switch to src/drivers/[X]/[Y]/ scheme
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make
them pluggable.

Change-Id: Ifc32b251677f8b75ffca224c0c900e9c34c756b9
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14051
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19 18:36:05 +02:00
Stefan Reinauer 431aa6dd1f drivers/xgi: Switch to src/drivers/[X]/[Y]/ scheme
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make
them pluggable.

Change-Id: I2cd6c1f1712e77ff98a9557519fb8efeeb400a69
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14049
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19 18:35:52 +02:00
Stefan Reinauer efb866f519 drivers/parade: Switch to src/drivers/[X]/[Y]/ scheme
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make
them pluggable.

Change-Id: I1313797d60925cc0627987936199e62073c264d7
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14061
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19 18:35:12 +02:00
Stefan Reinauer 7c85168c45 drivers/ti: Switch to src/drivers/[X]/[Y]/ scheme
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make
them pluggable.

Change-Id: Iac737e15db512eac96cd16fe14983b66a03876bb
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14050
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19 18:34:36 +02:00
Stefan Reinauer 86ddd732bd kbuild: Allow drivers to fit src/drivers/[X]/[Y]/ scheme
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make
them pluggable.

Also, fix up the following driver subdirectories by switching
to the src/drivers/[X]/[Y]/ scheme as these are hard requirements
for the main change:

* drivers/intel
* drivers/pc80
* drivers/dec

Change-Id: I455d3089a317181d5b99bf658df759ec728a5f6b
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14047
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19 18:34:18 +02:00
Martin Roth 3812597c66 Makefile.inc: Stop running git repeatedly for each build
Currently, the coreboot makefiles repeatedly run git to try to set
the KERNELVERSION variable and to fetch the submodules.  This happens
three times for every build.  By exporting a variable, we can catch
this on recursive makes and not run each of these steps again.

Change-Id: I85ab867b40e80c36bd94d48510ffe3252c6cf93f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14392
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-04-19 18:24:10 +02:00
Stefan Reinauer 88e83e580d crossgcc: Move temp file handling into cleanup function
Move code to handle leaving temp files around into cleanup.

Change-Id: Ief346d7973f693ec06c8bef6492cf1330858d9e1
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14346
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-04-19 01:38:06 +02:00
Stefan Reinauer 7844912f37 crossgcc: Fix out of bounds array access for nds32le
Patch from Segher Boessenkool <segher@kernel.crashing.org>

Change-Id: Ia91e0d6e50399da38afd8cdc0b92c82e4efa0a08
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14380
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-18 21:42:00 +02:00
Stefan Reinauer b194a43397 More compatible use of mktemp
This is taken from FILO and slightly enhanced.

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Change-Id: Ieadd9db3f1013ec1cd9f5a1dc44e17587617f1d1
Original-Change-Id: I961a7ddcd39657c9463806d7b82757eff0a4ac57
Original-Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Original-Reviewed-on: http://review.coreboot.org/190
Reviewed-on: https://review.coreboot.org/14386
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-18 15:59:22 +02:00
Martin Roth 41f0e0fd4d libpayload: disable EHCI & XHCI in defconfig-mips
drivers/usb/xhci.c and drivers/usb/ehci.c both require arch/barrier.h.

barrier.h is present for x86, arm, and arm64, but not for mips. This
is generating a build error after enabling USB by default on libpayload.

I believe that this slipped through the buiders due to them not getting
cleaned fully.  It was caught in the coverity scan and when setting up
a new build server.

Change-Id: Idd89409a048009c087ce2a787d96a1efd089157f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14391
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-04-18 14:24:21 +02:00
Furquan Shaikh 043976065b soc/intel/apollolake: Do not re-save BIST result
BIST result is already stored by arch/x86/bootblock_ctr0.S in
mm0. Also, eax does not contain BIST result by the time control
reaches bootblock_pre_c_entry. bootblock_crt0.S saves timestamp in mm2
which was being overwritten here. Thus, remove the saving of BIST
result from SoC code.

Change-Id: I65444689cf104c59c84574019f5daf82aab10bc7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/14381
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-04-18 05:20:25 +02:00
Martin Roth ee862ffc44 vendorcode/intel: Remove temporary Broadwell DE Kconfig symbol
This symbol was added to fix a Kconfig lint error after the
Broadwell DE vendorcode was added.  Now that the chipset's in
the codebase, it's no longer needed.

Change-Id: Iedb166129c9265cc2cfcc406d98bde92c1a82d2f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14384
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: York Yang <york.yang@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2016-04-18 01:37:04 +02:00
York Yang fbec6b160e MAINTAINERS: Add Intel Broadwell-DE SOC and Camelback Mountain CRB
Add Intel Broadwell-DE SOC and Camelback Mountain CRB to the list

Change-Id: I3f0c3ae8b38ecf3c3676fe497ade8b74ba94485d
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: https://review.coreboot.org/14382
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-17 23:26:59 +02:00
Werner Zeh bfe5726571 broadwell_de_fsp: Select HAVE_INTEL_FIRMWARE
By selecting this switch in Kconfig one can build complete rom image
including descriptor and ME/TXE.

Change-Id: I7307695008df9a61baba1eb024f1f48be62c53c8
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/14376
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-04-17 14:22:53 +02:00
Martin Roth b55bc7c9f3 mainboard/google/gru: Add license header to memlayout.ld
I missed this license header, and it's causing a build breakage.

Change-Id: If472e5c081bd282f0b482af629d6ec2314a2c329
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14388
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
2016-04-16 03:13:00 +02:00
Ben Gardner 26ac4db383 intel/fsp_baytrail: Eliminate warning about missing set_resources
In northcluster.c, the set_resources member of struct device_operations
is set to NULL.  That causes this message on the console:

   PCI: 00:00.0 missing set_resources

Eliminate that warning by setting set_resources=DEVICE_NOOP.

Change-Id: I4c6c07fd40b180ca44fe67c4a4d07318df10c40f
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/14366
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-04-16 02:04:41 +02:00
Edward O'Callaghan 5de5522685 vendorcode/amd/agesa: Fix tautological compare
An unsigned enum expression is always strictly positive;
Comparison with '>= 0' is a tautology, hence remove it.

Change-Id: I910d672f8a27d278c2a2fe1e4f39fc61f2c5dbc5
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: https://review.coreboot.org/8207
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2016-04-16 02:03:53 +02:00
Patrick Georgi 91d94b0907 google/gru: Incorporate feedback to #14279
To avoid diverging too much on an actively developed code base, keep
the changes to a separate commit that can be downstreamed more easily:

- removed unused includes
- gave kevin board a "Kevin" part number
- marked RW_LEGACY as CBFS region (to follow up upstream changes)
- moved romstage entry point to SoC code (instead of encouraging
  per-board copy pasta)

Change-Id: Ief0c8db3c4af96fe2be2e2397d8874ad06fb6f1f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14362
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-16 02:01:51 +02:00
huang lin a6dbfb5808 google/gru: Add a stub rk3399 mainboard
Most things still need to be filled in, but this will allow
us to build boards which use this SOC.

[pg: separated out from the combined commit that added both SoC and
board. Added board_info.txt that will be added downstream, too.]

Change-Id: I7facce7b98a5d19fb77746b1aee67fff74da8150
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 27dfc39efe95025be2271e2e00e9df93b7907840
Original-Change-Id: I6f2407ff578dcd3d0daed86dd03d8f5f4edcac53
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/332385
Reviewed-on: https://review.coreboot.org/14279
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-16 02:01:25 +02:00
Derek Waldner 3b42119237 util/superiotool: Add initial support for Exar XR28V384.
Datasheet
https://www.exar.com/content/document.ashx?id=21368

Add support for Exar chip used on a custom board
that was designed to connect to the Olive Hill Plus
development platform. The register dump was verified
on the Olive Hill Plus platform.

Change-Id: Ibd3e13eefb706bd99b6e5b38634f6855b39848ab
Signed-off-by: Derek Waldner <derek.waldner.os@gmail.com>
Reviewed-on: https://review.coreboot.org/14367
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-16 02:00:38 +02:00
Martin Roth 433e8d272d intel/apollolake: Fix whitespace issues
Change-Id: Ia5bcd19d994e23375d7e6d2050113c809ae57296
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14368
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-04-16 01:52:43 +02:00
Patrick Georgi 59493717ad northbridge/amd/{lx,gx2}: remove immediate accesses of 0
gcc doesn't like these because they're undefined behavior, so use
zeroptr instead. For the loop that just does a number of writes (0..4),
use zeroptr + i.

Checked the disassembly (AMD_RUMBA and PCENGINES_ALIX2D) to not contain
ud2 anymore and to look reasonable where zeroptr was used.

Change-Id: I4a58220ec9a10c465909ca4ecbe5366d0a8cc0df
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14345
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2016-04-16 01:50:55 +02:00