Asserting GPIO PERIPHERAL_EN8 will send a signal to EC to trigger a HW
reset for SoC and H1.
BUG=b:80501386
BRANCH=none
TEST=emerge-kukui coreboot; manually verified the do_board_reset() on
Kukui P1
Change-Id: I9afad84af2031a766bc08fc76c8b5f55588c453a
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/31118
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Separate WDT reset function from WDT driver, then we can use the common
WDT driver and have a board-specific reset function on different boards.
In Kukui, we plan to use GPIO HW reset, instead of WDT reset. Add config
"MISSING_BOARD_RESET" in Kukui to pass the build for now.
BUG=b:80501386
BRANCH=none
TEST=emerge-elm coreboot; emerge-kukui coreboot;
Change-Id: Ica07fe3a027cd7e9eb6d10202c3ef3ed7bea00c2
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/31121
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Version 2 IFD will have flmstr5 as EC region access control, consider it
during descriptor lock/unlock process.
BUG=N/A
TEST=Build coreboot with CONFIG_LOCK_MANAGEMENT_ENGINE set, and check
flmstr5 value by hexdump the SPI image at offset FMBA+0x90.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I970064dcf6114a15f054ab7c44349841deb99dc8
Reviewed-on: https://review.coreboot.org/c/31111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Cannonlake and Icelake have same read/write region permission settings
with skylake and kabylake, so add it here as well.
BUG=b:123199222
TEST=Turn on CONFIG_LOCK_MANAGEMENT_ENGINE and build image, check the
setting matches 0x0D for read and 0x04 for write.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I71d8b815c7dff7dcbcff2bf77c85ebf80b8df6d2
Reviewed-on: https://review.coreboot.org/c/31104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This board has almost the same schematics as [xt]60 so this should work.
See also commit 7971582e with Change-Id
Iff6dac5a5f61af49456bc6312e7a376def02ab00.
Change-Id: I8dc9b122eb64b5c1dcd0dbc99ac41aa0f8dd9766
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch removes stale ASL entries added in past due to chromeos
requirement.
BUG=115755982
TEST=Build and boot ICL platform without any problem.
Change-Id: I18b57822ce3198fb96aae977f0b552ff2d4a14ee
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31117
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
4.9 was still marked as "upcoming" and 4.10 was missing altogether,
leading to a sphinx warning.
Change-Id: I008d546715b7841eb9f325a6f698380dd4c1a7c2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/31126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The SoC has an Image Processing Unit which is located on PCI 00:03.0.
There is a corresponding parameter for FSP which handles
enabling/disabling of this functionality (IpuEn). Add this device to
the disable_dev() function of the chip so that if this device is
disabled in devicetree the matching FSP parameter will be disabled as
well. As this parameter is only valid for Apollo Lake, use the config
switch CONFIG_SOC_INTEL_GLK to disable this code if compiled not for
Apollo Lake. As this issue is regarding a missing structure member,
this check needs to be done on preprocessor level and not at runtime.
Test=Verified this function on mc_apl2.
Change-Id: I75444bf483de32ba641f76ca50e9744fdce2e726
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
If the VTd feature is enabled, there will be up to two fixed resources
which are set up by the FSP. Add these resources to the list of system
resources so that the PCI enumerator will know them.
Change-Id: If96fc1c93746e3c7f510e5b3095ea3090e1b8807
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30991
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Generate DMAR table if VTd feature is enabled.
Test=Booted into Linux on mc_apl2 and verified the DMAR table contents.
In addition turned off Vtd and verified that no DMAR table is generated
at all.
Change-Id: Ie3683a2f3578c141c691b2268e32f27ba2e772fa
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
In preparation of generating DMAR tables, provide the hook in SoC scope
for the systemagent to write ACPI tables. The complete functionality is
SoC-specific. Therefore the entry hook is defined as a weak function which
can be overridden by SoC code. If the SoC does not have support for
generating DMAR tables this hook will do no harm.
Change-Id: I1333ae2b79f1a855e6f3bb39bf534da170ddc9e1
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This is spotted using ./util/lint/kconfig_lint
To work around the issue, rename the prefix from `CONFIG_` to `CONF_`.
Change-Id: Ia31aed366bf768ab167ed5f8595bee8234aac46b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Select FSP_M_XIP if MAINBOARD_USES_FSP2_0, since all SkyKabylake
boards require FSP-M XIP when FSP 2.0 is used, and since not
having it selected results in a non-booting image.
Also, put select FSP_T_XIP if FSP_CAR in proper alphabetical order.
Change-Id: I6d3986eda18297b12490cefb236f5de5faca6550
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
In some cases (e.g. Arm architecture variants), include paths are stuck
into <stage>-generic-ccopts rather than CPPFLAGS_<stage> (in fact, the
whole redundancy between these two is kinda stupid and we should
probably eliminate the latter, but I don't want to get into that right
now). This patch makes sure those paths are also correctly translated
when invoking $(MAKE) for vboot.
Change-Id: I37f09b88e555567590664e0e6fac23c34fd887df
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Working:
- USB (Partially. Check "Not working")
- PCIe
- PCIe graphics
- All SATA ports
- Native memory init
- On-board audio (back and front)
- S3 (Sleep and wake)
Not working:
- Fan control
- USB (If the keyboard has a USB Hub or if the keyboard
is connected through 2 or more hubs then it doesn't
initialize in time. A simple reboot allows the
keyboard to be used in SeaBIOS and the bootloader)
Untested:
- PS/2
- On board graphics
Change-Id: I4ed2077248a8d7123c728c790d9b81fe37956ed2
Signed-off-by: Abhinav Hardikar <realdevmaster64@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30767
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These pins should not have pull downs configured in standby state as that
can cause contention on the termination circuitry and lead to incorrect
behavior as per Doc# 572688 Gemini Lake Processor GPIOTermination
Configuration.
BUG=b:79982669
TEST=Checked that code compiles with changes.
Change-Id: If3cadc000ec6fc56019ee3f57e556dc819d5e0a5
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/c/30823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
ELAN touchpad supports up to 400KHz, so we need to limit its CLK
frequency to 400HKz.
BUG=b:123376618
BRANCH=octopus
TEST=built and verified touchpad I2C clk frequency gets be lower than 400KHz
Change-Id: If7a43fe20c7e5abdf23c8c36e34c072c371563bf
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/31085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
While branded as thinkcentre a58 this board can also be found as
"L-IG41M".
Change-Id: I06ed424138c46c6b2f29f15c7ea5c3648b26a8d3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Current Melfas touchscreen driver cannot unregister ifself when
connecting without Melfas touchscreen or connecting with other devices.
And Melfas touchscreen FW can use I2C and HID over I2C driver, so
switch to using HID over I2C driver.
BUG=b:122710830
BRANCH=master
TEST=Verify touchscreen on sarien works with this change.
Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Change-Id: If04a2904a0f72a6c8363ab2c9865926c71cb5186
Reviewed-on: https://review.coreboot.org/c/31062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
MASK_STATUS disables interrupt status generation for the entire GPIO
controller when any debounce register is configured. This causes
problems when the kernel is loading drivers because we could lose
interrupts for previously loaded devices.
sb_program_gpios is also not setup to wait when configuring
PAD_DEBOUNCE, so there is a potential that we could lose the interrupt
status enable bit for other registers. By disabling MASK_STATUS we avoid
that problem.
BUG=b:113880780
BRANCH=none
TEST=Ran a reboot stress test that concluded that we are no longer
losing TPM interrupts while booting.
Change-Id: Ife1db3b1449f205092509595cbc3eca511bff57a
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Also make soc_get_tss_table public and weak instead of static
in intelblock so it can be overridden in denverton.
Change-Id: Id9c7da474a81417a5cebd875023f7cd3d5a77796
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/25430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Guckian
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Intel RTC common code driver need to turn on RTC itself.After the
change, cannonlake and icelake platform will have RTC enabled.
BUG=b:123372643
TEST=build and boot up on sarien platform, check .config to see
CONFIG_RTC is set.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I0c8c5cf9e6f7f338b1f2f784c04254649d257536
Reviewed-on: https://review.coreboot.org/c/31112
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit dc666f5 (soc/intel/cannonlake: Change in SaGv options) added a
conditional preprocessor directive, but its condition was incorrect
because SOC_INTEL_CANNONLAKE is selected for CNL, CFL and WHL. Thus, an
explicit check for !SOC_INTEL_COFFEELAKE is required.
While we are at it, clean up the comment above a bit.
BUG=b:123184474
Change-Id: I8a6959bb615fb5668cbfe54339747d135bd5a005
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31095
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is spotted using "./util/lint/kconfig_lint"
While at it, do the check in C and not the preprocessor.
Change-Id: Icfda267936a23d9d14832116d67571f42f685906
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Upper 128bytes of CMOS and RCBA are already enabled at bootblock.
Tested on 945g-MA. Resuming from suspend is working fine
Change-Id: I3f34380b0e700cf60688ad58465f9cb0aeda0928
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31107
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Boots again to payload not found on qemu.
Change-Id: Ie107eb882cbaac5a5a06c1ff990e7b9364377640
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/c/30554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This reverts commit 48c24ce5ee.
Reason for revert: Commit broke bincfg, and sym_table as a global
variable is less bad than passing it around in function calls.
Change-Id: Ib8d64a1dc201d17a4e278ab0114958b6807a45ac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This board does not have PMH7.
Change-Id: I382958f012e5f4445efc76c7f36bbdf460c29be4
Signed-off-by: James Ye <jye836@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31065
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
F81866 detection tested with the iBASE SI-613:
superiotool r4.9-420-g034e5e6
Found Fintek F81866 (vid=0x3419, id=0x1010) at 0x4e
F8196* detection is based on chip IDs provided by iBASE, but untested.
Change-Id: I7210e1523a188a8593cd03547bb0c95cd3e7aa39
Signed-off-by: Kyle Stevenson <kstevenson@comqi.com>
Reviewed-on: https://review.coreboot.org/c/31052
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Port the existing denverton tables to intelblock
- Add C-States table for denverton
Note: Removed code is functionally identical to corresponding
common code.
Tested-on: scaleway/tagada
Change-Id: Iee061a258a7b1cbf0a69bcfbf36ec2c623e84399
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/25428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
New emmc DLL values for Ampton
BUG=b:122307153
TEST=Boot to OS on 5 systems
Change-Id: Iadd58d254f4bb384f483c2c3e5615f7569d5211c
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/31048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
By default this board is configured to not power up after an
EC reset. However in the case of a cr50 firmware update that
will reset the EC it will end up powered off. In order to have
it stay powered up configure the board to power up. This will
get reset to the configured default when it boots again.
BUG=b:121380403
TEST=update cr50 firmware and reboot to ensure system boots and
does not end up powered off.
Change-Id: I85beae24b1bc56bb0813f1fd1305218f04b0c1c8
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31058
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to allow the mainboard to configure the system before a
cr50 initiated update reset add a weak function that the mainboard
can override if necessary.
This will allow a board that would otherwise be configured to
stay off after an EC reset to instead power up after the reset and
not end up in a shut down state after a cr50 update.
BUG=b:121380403
TEST=update cr50 firmware on sarien and reboot
Change-Id: I11f9e8c9bfe810f69b4eaa2c633252c25004cbd0
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31057
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Export the SOC level function to set the After G3 state so it
can be changed by the mainboard. The setting will be restored
by a normal boot but in some circumstances coreboot wants to
ensure that it will be powered up again after a reset.
BUG=b:121380403
TEST=update cr50 firmware on sarien and reboot and ensure the
host does not power off after the cr50 initiated reset.
Change-Id: I6cd572ac91229584b9907f87bb4b340963203c32
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31056
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Disabling CpuRatio UPD for FSP will ensure it does not force a
hard reset to set the CPU Flex Ratio at boot. This is important
in a recovery mode boot where the SOC will lose power and need
to set the flex ratio again.
Disabling SaGv makes recovery mode training faster and mirrors
the setting that was done on Skylake.
BUG=b:123305400
TEST=reliably enter recovery mode on sarien
Change-Id: Ie9664493a980af9acce82faff81f4c4b1355be73
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Increase BIOS region(SI_BIOS) from 16MB to 28MB to make more spaces for
upcoming payloads.
BUG=b:121169122
TEST=Build and boot up fine into OS on sarien and arcada platform.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I4b03e20a485cb819b468c00e68f1539e92731237
Reviewed-on: https://review.coreboot.org/c/31054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
It was observed system suspend/resume failure while running
RunInDozingStress. Apply correct GLK usb clock gating register
value to mitigate the failure.
BRANCH=octopus
BUG=b:120526309
TEST=Verified GLK clock gating register value after booting
to kernel.
Change-Id: I50fb16f5ab0e28e79f71c7f0f8e75ac8791c0747
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add support Synaptics touch pad for Aleena/Kasumi.
BUG=b:122549449
BRANCH=master
TEST= Check if synaptics touch pad working in ChromeOS.
Change-Id: Icab1b312f1943b27037ef458044ce9e7172919ee
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/31064
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hide "Add gigabit ethernet firmware" option for boards that do not
use GbE firmware in GbE section.
The option is now hidden by default and can be reenabled on a
per-board basis by selecting MAINBOARD_USES_IFD_GBE_REGION in the
mainboards Kconfig.
The following boards seem to use this:
mb/roda/rv11
mb/ocp/wedge100s
mb/ocp/monolake
mb/lenovo/x230
mb/lenovo/x220
mb/lenovo/x201
mb/lenovo/x200
mb/lenovo/t530
mb/lenovo/t520
mb/lenovo/t430s
mb/lenovo/t430
mb/lenovo/t420s
mb/lenovo/t420
mb/lenovo/t400
mb/kontron/ktqm77
mb/intel/saddlebrook
mb/intel/kblrvp
mb/intel/dg43gt
mb/intel/dcp847ske
mb/intel/coffeelake_rvp
mb/intel/camelbackmountain_fsp
mb/hp/revolve_810_g1
mb/hp/folio_9470m
mb/hp/compaq_8200_elite_sff
mb/hp/8770w
mb/hp/8470p
mb/hp/8460p
mb/hp/2760p
mb/hp/2570p
mb/google/sarien
mb/facebook/watson
mb/compulab/intense_pc
mb/asus/maximus_iv_gene-z
The boards were identified by looking at devicetree.cb, but this
list is possibly still incomplete.
Change-Id: Ibfb07902ad93fe5ff2bd4f869abcf6579f7b5a79
Signed-off-by: Jan Tatje <jan@jnt.io>
Reviewed-on: https://review.coreboot.org/c/30790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The iGPU always needs access to its stolen memory. For proper IOMMU
support, we have to make the OS aware of that.
Directly below TOLUD lies the data stolen memory (BDSM) followed by
the GTT stolen memory (BGSM), the iGPU needs access to both.
Change-Id: I391d0a5f1ea14bc90fbacabce41dddfa12b5bb0d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tristan Shieh