As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Updated Authors file is in a separate commit.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ia0a07df6ca1fdaa2837ce8839057057cbd44d157
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Updated Authors file is in a separate commit.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I1acea8c975d14904b7e486dc57a1a67480a6ee6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Rename the freeranges array to better match what they represent, i.e.
ranges that are used by the current running program and CAR region that
is not unallocated.
Skip adding the CAR region if cache-as-RAM is not active.
Change-Id: I78ee5536d890f30450a5ad2a753c948b02634d6d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36110
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Skip calling vbt_get() if FSP is not supposed to run GOP.
Change-Id: I6b8cd3646ffcd6df39229d4e36b315dfb7a8c859
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
* Add cbfsoption --ibb to mark files as IBB
* Will be used by "Legacy FIT TXT" boot
Change-Id: I83313f035e7fb7e1eb484b323862522e28cb73d4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
scan_usb_bus() and root_dev_scan_bus() had the very same implementation.
So rename the latter to scan_static_bus() and use that for both cases.
Change-Id: If0aba9c690b23e3716f2d47ff7a8c3e8f6d82679
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31901
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Auto-discoverable PCI devices do not require field .enable_dev
of chip_operations to be set. They are matched with PCI drivers
by the use of PCI vendor and device ID fields.
The name given for the chip_operations struct must match the
pathname the way it is present in the devicetree.cb files. If
there was no match, util/sconfig would currently choose to
use the empty weak declaration it creates in static.c file.
Change-Id: I684a087a1f8ee4e1a5fd83450cd371fcfdbb6847
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Allow to set a lower temperature limit, as the currently hard-coded
25C may be to low for a given temperature sensor. Also enable smoo-
thing, currently hard-coded to the maximum interval of 35s, and set
the hysteresis value.
Change-Id: I5fde1cf909e8fbbaf8a345790b00c58a73c19ef8
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
We accidentally converted an `int` return value to an `unsigned`,
making it impossible to check for errors with `< 0`. Fix that by
using an `int` variable.
Change-Id: I5433c27e334bc177913e138df83118b128c674b7
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The existing Kconfig code made SMBIOS_PROVIDED_BY_MOBO depend
on VENDOR_LENOVO. Thus, it couldn't be selected by boards from
other vendors. So we add another Kconfig that selects it
here.
NB. It's still unclear how the two drivers in this directory
are related (at24rf08c and lenovo_serial). From the code, it
doesn't look like the latter belongs here.
Change-Id: Iaa5c5a584f2a5e2426352ec6aa681f99a55efa49
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The simple PCI config accessors are always available
under names pci_s_[read|write]_configX.
Change-Id: Ic1b67695b7f72e4f1fa29e2d56698276b15024e1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In FSP-S, the driver constructs its pointer to UPD using the offset
in the header. Similarly, use the header's cfg_region_size for
allocating memory and copying the default configuration.
Add sanity checks for unexpedted configuration and UPD header
conditions.
TEST=Verify OK on Mandolin, verify a mock error condition
BUG=b:140648081
Change-Id: I20fad0e27a2ad537898b6d01e5241e1508da690c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
As code already used CBMEM hooks to switch from CAR to CBMEM
it was never necessary to have the structure declared inside
_car_relocatable_data.
Switch to use car_[get|set]_ptr is mostly for consistency, but
should also enable use of usbdebug with FSP1.0 romstage.
Change-Id: I636251085d84e52a71a1d5d27d795bb94a07422d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The documentation for StackBase and StackSize in FSPM_ARCH_UPD is
confusing. Previously the region was shared for heap and stack,
starting with FSP2.1 only for heap (or 'temporary RAM') for HOBs.
Moving the allocation outside DCACHE_BSP_STACK_SIZE allows use of
stack guards and reduces amount of reserved CAR for bootblock and
verstage, as the new allocation in .bss is only taken in romstage.
BUG=b:140268415
Change-Id: I4cffcc73a89cb97ab7759dd373196ce9753a6307
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Currently SPI vendor IDs are magic numbers in spi_flash.c. These definitions
are needed for AMD's fch_spi. So add the definitions to spi_generic.h and use
it at spi_flash.c
BUG=b:136595978
TEST=Build test of several platforms that don't use stoneyridge. Build and boot
grunt (using stoneyridge new fch_spi).
Change-Id: Ie39485d8c092151db8c9d88afaf02e19c507c93f
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Summary:
Added a framework to search VPD in romstage before memory is
avilable. vpd_cbmem.c and vpd_premem.c are added for
code specific for premem environment and for environment that
cbmem can be used.
Since global variable is forbidden in romstage. A CAR_GLOBAL
variable is defined in vpd.c. This variable holds VPD binary
blobs' base address and size from memory mapped flash.
The overall flow is:
* The CAR variable g_vpd_blob is initialized if it was not,
either at romstage (before FSP-M execution in case of FSP UPD
customization), or at ramstage.
* At ramstage, during CBMEM_INIT, the VPD binary blob contents
are copied into CBMEM.
* At vpd_find() which may be called at romstage or at ramstage,
it sets storage for a local struct vpd_blob variable.
* The variable gets contents duplicated from g_vpd_blob, if
vpd_find() is called at romstage.
* The variable gets contents obtained from CBMEM, if vpd_find()
is called at ramstage.
Added a call vpd_get_bool(). Given a key/value pair in VPD
binary blob, and name of a bool type variable, set the variable
value if there is a match.
Several checks are in place:
* The key/value length needs to be correct.
* The key name needs to match.
* THe value is either '1' or '0'.
Test Plan:
* Build an OCP MonoLake coreboot image, flash and run.
Tags:
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Iebdba59419a555147fc40391cf17cc6879d9e1b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Advertise the register spacing used by the BMC as set by the Kconfig.
Tested on OCP Monolake.
Change-Id: Ib926d30f6a0e78fbf613a6f71f765c5f51eee77d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
This provides stack guards with checking and common
entry into postcar.
The code in cpu/intel/car/romstage.c is candidate
for becoming architectural so function prototype
is moved to <arch/romstage.h>.
Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This Device ID is specific to CML, since it is obtained by reading ISH
configuration RO register.
In order to export ISH to kernel PCI device tree, this number must be
included in list of devices supported.
Change-Id: I6d245f1b3f0d0cfec77c31033eb20f147fd3d870
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34687
Reviewed-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Variable length arrays were a feature added in C99 that allows the
length of an array to be determined at runtime. Eg.
int sum(size_t n) {
int arr[n];
...
}
This adds a small amount of runtime overhead, but is also very
dangerous, since it allows use of an unlimited amount of stack memory,
potentially leading to stack overflow. This is only worsened in
coreboot, which often has very little stack space to begin with. Citing
concerns like this, all instances of VLA's were recently removed from the
Linux kernel. In the immortal words of Linus Torvalds [0],
AND USING VLA'S IS ACTIVELY STUPID! It generates much more code, and
much _slower_ code (and more fragile code), than just using a fixed
key size would have done. [...] Anyway, some of these are definitely
easy to just fix, and using VLA's is actively bad not just for
security worries, but simply because VLA's are a really horribly bad
idea in general in the kernel.
This patch follows suit and zaps all VLA's in coreboot. Some of the
existing VLA's are accidental ones, and all but one can be replaced with
small fixed-size buffers. The single tricky exception is in the SPI
controller interface, which will require a rewrite of old drivers
to remove [1].
[0] https://lkml.org/lkml/2018/3/7/621
[1] https://ticket.coreboot.org/issues/217
Change-Id: I7d9d1ddadbf1cee5f695165bbe3f0effb7bd32b9
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
When entry to romstage is via cpu/intel/car/romstage.c
BIST has not been passed down the path for sometime.
Change-Id: I345975c53014902269cee21fc393331d33a84dce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The default is 1 (byte) spacing.
Tested on Mono Lake with 4 (32-bit) spacing
Change-Id: I47412c32e6db8f58b4fde8150adcbce349ca18a7
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
As most platforms will share the subset of enabling
both low RAM WB and high ROM WP MTRRs, provide them
with a single function.
Add possibility for the platform to skip these if
required.
Change-Id: Id1f8b7682035e654231f6133a42909a36e3e15a1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34809
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are benefits in placing the postcar_frame structure
in .bss and returning control to romstage_main().
Change-Id: I0418a2abc74f749203c587b2763c5f8a5960e4f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change adds support for allowing devices to provide a
"compatible" property string that can be used when _HID is set to
PRP00001. This is used to allow Linux kernel drivers to match the
device to appropriate driver based on the OF-style compatible
string.
Reference:
https://www.kernel.org/doc/Documentation/acpi/enumeration.txt
BUG=b:129162037
TEST=Verified that atmel touchscreen gets enumerated correctly on
kohaku using PRP0001 and compatible string.
Change-Id: I8a306854c67ab2f056ea8774df46599ef0c55761
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
It is easier to track CAR_GLOBAL_MIGRATION which is
the approach to be deprecated with the next release.
This change enforces new policy; POSTCAR_STAGE=y is
not allowed together with CAR_GLOBAL_MIGRATION=y.
Change-Id: I0dbad6a14e68bf566ac0f151dc8ea259e5ae2250
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Almost all platforms force it on. Make it enabled by
default but under user control to optionally disable it.
Change-Id: I6b0f19c8bfd6ffed93023d57a1d28ca6acc06835
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
The <inttypes.h> header currently does nothing but include the
definitions from <stdint.h>, so let's #include that directly instead.
Change-Id: I9d83ad37d0d7300a093001596ce3f0b3830c5701
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Martin Roth