Following the same reasoning as commit
ee905a8 vendorcode/amd/agesa/fam15tn: Build as a static library
Since AGESA is stage-independent, we can build it just once, and use
the resulting static library in both rom and ram stages.
Change-Id: I8b78c462f4963fbb3a40d739196529fffedccb4c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5441
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Up until now, we were building AGESA by specifying each AGESA source
file and adding it to the list of romstage and ramstage source files.
As a result, we were compiling each AGESA source twice, despite the
fact that it does not depend on the stage we're in.
Since AGESA is stage-independent, we can build it just once, and use
the resulting static library in both rom and ram stages.
We still keep the practice of specifying every single AGESA directory
as an include dir and adding the AGESA CFLAGS to our global CFLAGS;
this is needed due to the way AGESA builds.
Change-Id: I9b23264129d1c08cb67cabc31d15a68d43ed7624
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5430
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
The ROM address range is set up in the LPC PCI device, register 0x6c.
Coreboot already sets that up correctly in the bootblock, however
AGESA overrides that to 0xffffff00, which will always map the ROM from
0xff000000. This may conflict with other devices which are assigned
address space in that range.
If a device is assigned a range between 0xff000000 and the real ROM
base, accesses to that device will be diverted to the system ROM,
regardless of how other BARs are set up. Since we already need to set
up the ROM address range in the bootblock, before calling AGESA, just
remove the override from AGESA.
Note that not all AGESA versions override this mapping.
Change-Id: I592e5d087ed830c9604a04a356912c7654ce56d2
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5467
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
A comparison with a two's complement in gcccar.inc has dubious
GAS/AT&T notation. Clang miss-parses 0x-1 as an invalid hexadecimal
number.
Change-Id: I88baa5c2513f062ff309df05916a3832b9bd9bb1
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5277
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
It is inappropriate for chipset code to be redefining
types -- especially NULL to a non-pointer type. There's
only one non-straight forward change. A condition
being checked was '!ptr_type == NULL' (0 as int). That
check is actually 'ptr_type != NULL'.
Change-Id: Iab5733e5a573baba6fec94e0c955ba4fad72c836
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5088
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The AGESA resumes the GPP ports in the romstage using FchInitResetGpp(),
which does FchGppPortInitS3Phase() for S3 resume. The PreInitGppLink()
looks into CMOS to figure out what ports to just force to Gen1 or
Gen2 PCIe. Then boot continues and in the ramstage the rest of GPP
init is executed. There is a problem that nobody sets properly the
PortDetected flags in the S3 path. As the consequence FchGppDynamicPowerSaving()
thinks the GPP port is not enabled and shut downs it.
The best fix would be also to remove the CMOS dependency which
might be some left over, because AGESA does not use CMOS much for
anything else. There could be also some way how to pass the GPP state
structure from romstage to ramstage possibly via hudson/resume.c
but I don't know how to do that. Similar problem is that the "late"
stage of init again "forgets" the PortDetected state.
This fix fixes the resume issue on Asus F2A85-M. With this patch applied
both GPP ports (used as PCIe x1 and internal ethernet) are working again
after resume.
Change-Id: Idaf609043abb09441c6790504d66d23e0637588f
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/4671
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The bug is hard to find. We were adding the feature of fan control. We
met some strange things which could not be explained. Like, sometimes
adding printk let the error disappear. Then we traced the code by hardware
debug tool (HDT). It turned out the data in stack was overwritten.
The values of AccessWidthxx are
{ AccessWidth8 = 1,
AccessWidth16,
AccessWidth32,}
For the case of AccessWidth8, we only need to access the index/data
once. But ReadECmsg and WriteECmsg did the loop twice, 1 more time
than they are supposed to do. The data in stack next to "Value" would
be overwritten.
For all the cases, the code should be
OpFlag = OpFlag & 0x7f;
switch (OpFlag) {
case 1: /* AccessWidth8 */
OpFlag = 0;break;
case 2: /* AccessWidth16 */
OpFlag = 1;break;
case 3: /* AccessWidth32 */
OpFlag = 3;break;
case 4: /* AccessWidth64 */
OpFlag = 7;break;
default:
error;
}
Actually, the caller only takes AccessWidth8 as the parameter. We can ignore other
cases for now.
That is an AGESA bug. AMD's AGESA team own this code. They have given the
response that they are going to update this in next release. I presume let them
decide the proper way to fix that. Before that, I change the code as little
as possible to make it run without crash.
Change-Id: I566f74c242ce93f4569eedf69ca07d2fb7fb368d
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/4297
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
The platform initialization (PI) code v1.0.0.7 for Kabini has some
enhancements like ECC DIMM support, new CPU microcode rev 0700010B, FCH
bug fix (RTC) and so on.
Use the name Kabini instead of Kerala everywhere.
Note, the former PI code was indeed version v1.0.0.0 instead of v0.0.1.0
as used in `AGESA_VERSION_STRING`.
Change-Id: I186de1aef222cd35ea69efa93967a3ffb8da7248
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3935
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Northbridge code includes these headers, so they all need to
have the same name to allow different combinations of northbridge
and southbridge. This changes the sb900 names to match sb700 &
sb800, and points agesa/family12 and amd/torpedo to the new file
names.
Change-Id: I7a654ce9ae591a636a56177f64fb8cb953b4b04f
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Reviewed-on: http://review.coreboot.org/3825
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
src/southbridge/amd/agesa/hudson/Kconfig config default value,
mainboard Kconfig config value for specific mainboard.
bit 1,0 - pin 0
bit 3,2 - pin 1
bit 5,4 - pin 2
bit 7,6 - pin 3
Change-Id: I54a87cf734685515a3e1850838ca7d94387172ce
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3879
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Copied from a similar commit for Family 10h AGESA [1]
Remove the fourth argument in the comments. Luckily the compiler,
at least gcc, warns about a wrong number of arguments, and therefore
no incorrect code resulted from the wrong documentation.
[1] 07e0f1b AMD AGESA: Fix argument list for `PCIE_DDI_DATA_INITIALIZER` in comments
[2] fc47bfa Revert "AMD f14 vendorcode: Fix warning"
Change-Id: I3806e368a823e4a40d22e99b91bf3598d9ed2f15
Signed-off-by: Bruce Griffith <bruce.griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3840
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin@se-eng.com>
This is the same patch as an earlier one applied to family 15 [1].
Static analysis often flags case statements that do not include
a terminating "break;" statement. Eclipse's CODAN is an example
of this. This changelist modifies amdlib.c to terminate
case statements with "break;".
[1] e44a89f amd/agesa/f15/Lib/amdlib.c: Add missing breaks ...
Change-Id: Ibd1ae6f2b52fde07de3d978d174975f4d93647ab
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3839
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin@se-eng.com>
Add CONST modifiers to read-only pass-by-reference function
parameters in AGESA. This allows the use of "const" modifiers
on the declaration of lookup tables that are pass-by-reference.
These will be used to identify tables that are copied onto the
HEAP but don't need to be.
This same change was made for AMD Trinity APUs (Family15tn) [1].
[1] 283ba78 AGESA: Add "const" modifier to function parameters
Change-Id: I2bdd9fc5e027e938de9df0f923b95da934bb48dc
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: Bruce Griffith <bruce.griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3837
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This changelist was cherry-picked from merged community code
for Parmer [1] and the paths modified so that the Parmer
modification is applied against Olive Hill.
[1] 0086162 AMD SATA: Correct _them implement_ ... in comments
Change-Id: I9849e9a75dacfde15331c4200d72343a59036f14
Signed-off-by: Bruce Griffith <bruce.griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3841
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Static analysis often flags case statements that do not include
a terminating "break;" statement. Eclipse's CODAN is an example
of this. This changelist modifies amdlib.c to terminate
case statements with "break;".
Change-Id: I3d43acaf64e2e2d9717421cb547fec35e582cf8b
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3539
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This change is mostly type casts to eliminate compile time
warnings. These specific changes are mostly cherry-picked from
AMD Family 14 code and, as such, contain artifacts copied over
from F14. For example, there are a number of UINT64 casts that
are commented out rather than removed. This is to maintain
consistency between AGESA versions. Ultimately, this is in
preparation for turning on warnings as errors for AMD Family 15
server parts.
Change-Id: Ic73d0b6ebab18d97015a9dd1130aff4e5e432fb7
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3525
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
fam15 vendorcode (src/vendorcode/amd/agesa/f15tn) was licensed under the
AMD software license agreement. Change this license to 3-clause BSD.
Change-Id: I7cab09bb58ef7cd24602628e2278672d577214a2
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3414
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Add CONST modifiers to read-only pass-by-reference function
parameters in AGESA. This allows the use of "const" modifiers
on the declaration of lookup tables that are pass-by-reference.
These will be used to identify tables that are copied onto the
HEAP but don't need to be.
Change-Id: Ie1187a427804fddf47b935a110ad23931a3447a9
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3393
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Fix Warning:
cpuFeatureLeveling.c:265, GNU Compiler 4 (gcc), Priority: Normal
cast to pointer from integer of different size [-Wint-to-pointer-cast]
with an intermediate cast to (intptr_t)
Change-Id: I3bfd2ea1e797632316675338789dabef8f73ba64
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/3126
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This fixes 3 warnings in the Proc/Common directory:
AmdS3Save.c:250, GNU Compiler 4 (gcc), Priority: Normal
AmdS3LateRestore.c:123, GNU Compiler 4 (gcc), Priority: Normal
cast from pointer to integer of different size [-Wpointer-to-int-cast]
Fixed with a second cast to (intptr_t)
AmdInitReset.c:153, GNU Compiler 4 (gcc), Priority: Normal
statement with no effect [-Wunused-value]
Fixed by commenting the line out as it is in the other families code.
Change-Id: Ib35ec466671712af01568b7c2a18ee138fe883c0
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/3125
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The following command was used to correct all occurences of this typo.
$ git grep -l "them implem" | xargs sed -i 's/them implem/then implem/'
Change-Id: Iebd4635867d67861aaf4d4d64ca8a67e87833f38
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3145
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
When looking into possible reasons for a proposed revert [1], I noticed
that the comments use four arguments for `PCIE_DDI_DATA_INITIALIZER`,
but the actual definition only uses three.
$ git grep -A1 PCIE_DDI_DATA_INITIALIZER # manually squeeze whitespace in output
[…]
--
src/vendorcode/amd/agesa/f10/AGESA.h:#define PCIE_DDI_DATA_INITIALIZER(mConnectorType, mAuxIndex, mHpdIndex ) \
src/vendorcode/amd/agesa/f10/AGESA.h-{mConnectorType, mAuxIndex, mHpdIndex}
--
src/vendorcode/amd/agesa/f10/AGESA.h: * PCIE_DDI_DATA_INITIALIZER (ConnectorType
src/vendorcode/amd/agesa/f10/AGESA.h- * },
--
src/vendorcode/amd/agesa/f10/AGESA.h: * PCIE_DDI_DATA_INITIALIZER (ConnectorType
src/vendorcode/amd/agesa/f10/AGESA.h- * }
--
[…]
So remove the fourth argument in the comments. Luckily the compiler,
at least gcc, warns about a wrong number of arguments, and therefore
no incorrect code resulted from the wrong documentation.
[1] http://review.coreboot.org/#/c/3077/
Change-Id: I3e5a02c66a23af1eb2d86be8dbc7aaa3e5cea05e
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3080
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Spell RAID correctly in comments. Found with the following command.
$ git grep -i riad
Change-Id: I68e8476d885a88df589d25f88cc158d71eb04e07
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3081
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Change-Id: I4aba6cc490ab24c6db345c0c5a64a6a9985ed0ab
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/2864
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
AGESA code has wrong definition of CR0_PE bit (1 instead of 0).
PE [Protected Mode Enable] is 0 bit in CR0 register
(If PE=1, system is in protected mode, else system is in real mode)
Bit 1 is MP [Monitor co-processor]
(Controls interaction of WAIT/FWAIT instructions with TS flag in CR0)
System uses CR0_PE define, but I didn't expect any consequences because of this bug.
Change-Id: I54d9a8c0ee3af0a2e0267777036f227a9e05f3e1
Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/2591
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
_RDMSR instruction loads the contents of a 64-bit model specific register (MSR)
specified in the ECX register into registers EDX:EAX.
The EDX register is loaded with the high-order 32 bits of the MSR
and the EAX register is loaded with the low-order 32 bits.
EDX:EAX = MSR[ECX]
So bit 49 will be contained in EDX register.
Buggy code instead of bit 49 (CombineCr0Cd) sets bit [49-32=17] (PfcStrideDis).
PfcStrideDis bit disables stride prefetch generation. This leads to memory
bandwidth loss.
_________
Supermicro H8QGI board
After applying this change i observed huge memory bandwidth increase in tests
that runs on small amount of cores. But unfortunately it doesn't affect
overall bandwidth results on 4P system with 48 cores.
So i think that in this system leading limiting factor is
AMD HT-ASSIST feature (Probe filter).
But right now it is not working. System stucks in Linux boot. I have done
some experiments and figured out that stuck happens when system have cores in
compute unit (CU) other than CU with BSC (boot strap core).
CU is two cores (primary and seconary) that shares some things (L2 cache, FPU ...)
So with probe filter i can boot Linux with one (BSC)
or two (BSC + secondary core in its CU) cores.
And with this configuration i can see memory bandwidth on 1 core (or two cores)
close to original bios.
Change-Id: I5a95f5b753d600c70d3c93d36fecc687610c61cd
Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/2588
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
In the file `COPYING` in the coreboot repository and upstream [1]
just one space is used.
The following command was used to convert all files.
$ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/'
[1] http://www.gnu.org/licenses/gpl-2.0.txt
Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2490
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Add brackets around initializer in #define for
PCIE_DDI_DATA_INITIALIZER to fix the warning:
PlatformGnbPcie.c:89, GNU Compiler 4 (gcc), Priority: Normal
missing braces around initializer [-Wmissing-braces]
This warning happens for Inagua and South Station
Change-Id: I7d8f742dd8335b704b0493aa6e9eaebc3cc50b1e
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2495
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add needed prototypes to .h files.
Remove unused variables and fix types in printk statements.
Add #IFNDEFs around #DEFINEs to keep them from being defined twice.
Fix a whole bunch of casts.
Fix undefined pre-increment behaviour in a couple of macros. These now
match the macros in the F14 tree.
Change a value of 0xFF that was getting truncated when being assigned
to a 4-bit bitfield to a value of 0x0f.
This was tested with the torpedo build.
This fixes roughly 132 of the 561 warnings in the coreboot build
so I'm not going to list them all.
Here is a sample of the warnings fixed:
In file included from src/cpu/amd/agesa/family12/model_12_init.c:35:0:
src/include/cpu/amd/amdfam12.h:52:5: warning: redundant redeclaration of 'get_initial_apicid' [-Wredundant-decls]
In file included from src/cpu/amd/agesa/family12/model_12_init.c:34:0:
src/include/cpu/amd/multicore.h:48:5: note: previous declaration of 'get_initial_apicid' was here
src/northbridge/amd/agesa/family12/northbridge.c:50:10: warning: no previous prototype for 'get_node_pci' [-Wmissing-prototypes]
src/northbridge/amd/agesa/family12/northbridge.c: In function 'get_hw_mem_hole_info':
src/northbridge/amd/agesa/family12/northbridge.c:302:13: warning: unused variable 'i' [-Wunused-variable]
src/northbridge/amd/agesa/family12/northbridge.c: In function 'domain_set_resources':
src/northbridge/amd/agesa/family12/northbridge.c:587:5: warning: format '%lx' expects argument of type 'long unsigned int', but argument 3 has type 'device_t' [-Wformat]
src/northbridge/amd/agesa/family12/northbridge.c:587:5: warning: format '%lx' expects argument of type 'long unsigned int', but argument 3 has type 'device_t' [-Wformat]
src/northbridge/amd/agesa/family12/northbridge.c:716:1: warning: format '%x' expects argument of type 'unsigned int', but argument 3 has type 'long unsigned int' [-Wformat]
In file included from src/mainboard/amd/torpedo/agesawrapper.h:31:0,
from src/northbridge/amd/agesa/family12/northbridge.c:38:
src/vendorcode/amd/agesa/f12/AGESA.h:1282:0: warning: "TOP_MEM" redefined [enabled by default]
In file included from src/northbridge/amd/agesa/family12/northbridge.c:34:0:
src/include/cpu/amd/mtrr.h:31:0: note: this is the location of the previous definition
In file included from src/mainboard/amd/torpedo/agesawrapper.h:31:0,
from src/northbridge/amd/agesa/family12/northbridge.c:38:
src/vendorcode/amd/agesa/f12/AGESA.h:1283:0: warning: "TOP_MEM2" redefined [enabled by default]
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetNumberOfComplexes':
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:99:19: warning: operation on 'ComplexList' may be undefined [-Wsequence-point]
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetLengthOfPcieEnginesList':
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:126:20: warning: operation on 'PciePortList' may be undefined [-Wsequence-point]
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetLengthOfDdiEnginesList':
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:153:19: warning: operation on 'DdiLinkList' may be undefined [-Wsequence-point]
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetComplexDescriptorOfSocket':
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:225:17: warning: operation on 'ComplexList' may be undefined [-Wsequence-point]
src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePhyServices.c:246:1: warning: no previous prototype for 'PcieFmForceDccRecalibrationCallback' [-Wmissing-prototypes]
In file included from src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexConfig.c:58:0:
src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/LlanoComplexData.h:120:5: warning: large integer implicitly truncated to unsigned type [-Woverflow]
And fixed a boatload of these types of warning:
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c: In function 'HeapGetBaseAddress':
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:687:17: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:694:19: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:701:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:702:23: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:705:23: warning: assignment makes integer from pointer without a cast [enabled by default]
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:709:21: warning: assignment makes integer from pointer without a cast [enabled by default]
Change-Id: I97fa0b8edb453eb582e4402c66482ae9f0a8f764
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2348
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Add a prototype to a .h file
Remove an unused file (GppHp.c) from the build by deleting it from the
makefile. I left the file since this is vendorcode. This is the code
for PCIe hotplug.
Inside GppHp.c, make functions not called from outside static.
This obviously isn't important since the file isn't used, but for
the sake of the cleanup I thought I'd go ahead with it...
This was tested with the torpedo build.
This fixes these warnings:
src/vendorcode/amd/cimx/sb900/Dispatcher.c: In function 'LocateImage':
src/vendorcode/amd/cimx/sb900/Dispatcher.c:193:38: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
src/vendorcode/amd/cimx/sb900/Usb.c:740:1: warning: no previous prototype for 'XhciA12Fix' [-Wmissing-prototypes]
src/vendorcode/amd/cimx/sb900/GppHp.c:65:1: warning: no previous prototype for 'sbGppHotPlugSmiProcess' [-Wmissing-prototypes]
src/vendorcode/amd/cimx/sb900/GppHp.c: In function 'sbGppHotPlugSmiProcess':
src/vendorcode/amd/cimx/sb900/GppHp.c:76:5: warning: implicit declaration of function 'SbStall' [-Wimplicit-function-declaration]
src/vendorcode/amd/cimx/sb900/GppHp.c: At top level:
src/vendorcode/amd/cimx/sb900/GppHp.c:101:1: warning: no previous prototype for 'sbGppHotUnplugSmiProcess' [-Wmissing-prototypes]
src/vendorcode/amd/cimx/sb900/GppHp.c:134:1: warning: no previous prototype for 'sbGppHotplugSmiCallback' [-Wmissing-prototypes]
src/vendorcode/amd/cimx/sb900/GppHp.c: In function 'sbGppHotplugSmiCallback':
src/vendorcode/amd/cimx/sb900/GppHp.c:158:5: warning: implicit declaration of function 'outPort80' [-Wimplicit-function-declaration]
Change-Id: I5a1a20eeb81e1f4d59e3e3192f081e11d8506f56
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2349
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Added casts and a couple of #ifdefs to fix the warnings in the
vendorcode/amd/agesa/f14 codebase. This will allow us to re-enable
'all warnings being treated as errors' in boards such as Persimmon
that are using this code. That change will follow.
These are the warnings that are fixed by this patch:
src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c: In function 'CopyHeapToTempRamAtPost':
src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c:219:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c: In function 'CopyHeapToMainRamAtPost':
src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c:372:30: warning: comparison between pointer and integer [enabled by default]
src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c:381:33: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c: In function 'ApUtilSetupIdtForHlt':
src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c:863:19: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c:872:18: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
src/vendorcode/amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c: In function 'LoadMicrocode':
src/vendorcode/amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c:211:28: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c: In function 'HeapManagerInit':
src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:167:52: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:183:14: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c: In function 'HeapGetBaseAddress':
src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:669:17: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:676:19: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:683:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:684:23: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:687:23: warning: assignment makes integer from pointer without a cast [enabled by default]
src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:691:21: warning: assignment makes integer from pointer without a cast [enabled by default]
src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:696:3: warning: return makes pointer from integer without a cast [enabled by default]
In file included from src/mainboard/amd/persimmon/agesawrapper.h:30:0,
from src/northbridge/amd/agesa/family14/northbridge.c:36:
src/vendorcode/amd/agesa/f14/AGESA.h:1132:0: warning: "TOP_MEM" redefined [enabled by default]
In file included from src/northbridge/amd/agesa/family14/northbridge.c:34:0:
src/include/cpu/amd/mtrr.h:31:0: note: this is the location of the previous definition
In file included from src/mainboard/amd/persimmon/agesawrapper.h:30:0,
from src/northbridge/amd/agesa/family14/northbridge.c:36:
src/vendorcode/amd/agesa/f14/AGESA.h:1133:0: warning: "TOP_MEM2" redefined [enabled by default]
In file included from src/northbridge/amd/agesa/family14/northbridge.c:34:0:
src/include/cpu/amd/mtrr.h:34:0: note: this is the location of the previous definition
Verified on persimmon.
Change-Id: I1671b191c72dfc1d63ada41126ae3418bc8f86ae
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2293
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Steven Sherk <steven.sherk@se-eng.com>
Enable 'all warnings being treated as errors' in thatcher and parmer.
Fixed the following warnings on parmer / thatcher:
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:
In function 'GetGlobalCpuFeatureListAddress':
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:291:14:
warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:
In function 'SaveDeviceContext':
src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:245:18:
warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:309:16:
warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c:
In function 'GetPstateGatherDataAddressAtPost':
src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c:235:10:
warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c:
In function 'MemNInitNBDataTN':
src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c:353:32:
warning: assignment from incompatible pointer type [enabled by default]
src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c:363:23:
warning: assignment from incompatible pointer type [enabled by default]
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:
In function 'GetGlobalCpuFeatureListAddress':
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:291:14:
warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:
In function 'SaveDeviceContext':
src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:245:18:
warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:309:16:
warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
In file included from src/northbridge/amd/agesa/family15tn/northbridge.c:37:0:
src/vendorcode/amd/agesa/f15tn/AGESA.h:1547:0:
warning: "TOP_MEM" redefined [enabled by default]
src/include/cpu/amd/mtrr.h:31:0:
note: this is the location of the previous definition
src/vendorcode/amd/agesa/f15tn/AGESA.h:1548:0:
warning: "TOP_MEM2" redefined [enabled by default]
src/include/cpu/amd/mtrr.h:34:0:
note: this is the location of the previous definition
In file included from src/northbridge/amd/agesa/family15tn/northbridge.c:41:0:
src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h:378:0:
warning: "LOCAL_APIC_ADDR" redefined [enabled by default]
src/include/cpu/x86/lapic_def.h:9:0: note:
this is the location of the previous definition
In file included from src/mainboard/amd/parmer/BiosCallOuts.h:24:0,
from src/mainboard/amd/parmer/mainboard.c:28:
src/vendorcode/amd/agesa/f15tn/AGESA.h:1547:0:
warning: "TOP_MEM" redefined [enabled by default]
src/include/cpu/amd/mtrr.h:31:0:
note: this is the location of the previous definition
src/vendorcode/amd/agesa/f15tn/AGESA.h:1548:0:
warning: "TOP_MEM2" redefined [enabled by default]
src/include/cpu/amd/mtrr.h:34:0: note:
this is the location of the previous definition
Change-Id: Iecea28232f1761401cf09f7d2a77d3fbac2f5801
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2171
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
In the AGESA routine GfxInitSview() called in the S3save path,
the IO Space bit was getting cleared from the command register.
This kept seabios from initializing the video bios. If the vbios
was loaded by coreboot, this routine was skipped, allowing seabios
to initialize vbios as well. I have modified the routine to save
and restore the command register instead of clearing the IO Space
bit.
Change-Id: I756b0606adbc47da96780308c911852e39f547c7
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2172
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
The Number of Ports register says that it should be set to the maximum
number of ports supported by the silicon. AGESA was setting this to be
the number of enabled ports. If port 1 was the only port with a drive,
this value got set to 0, indicating 1 port. This causes SeaBIOS to only
look at port 0 and quit, never finding the drive on port 1.
Dave Frodin: I also verified that this patch allows a SATA drive plugged
into port 2 to be detected without a device in port 1.
Change-Id: I5d49e351864449520e3957bbb07edf0f3ec2fd47
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2165
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
ACPI code:
The ACPI code is not currently being compiled in by default, but
assuming that it will be at some point, I'm fixing the loop that
waits for the IMC to respond after sending it a command. The
loop now exits after 500ms, similar to the function in agesa.
Agesa Code:
a 16 bit variable will always be less than 100000. Change to
be a 32 bit variable.
Change-Id: I9430ef900a22d056871b744f3b1511abdfea516e
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/2119
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Success return value in DMI functions GetDmiInfoMain(..) and GetType4Type7Info(...) of AGESA vendorcode is "Flag = TRUE".
This results in a failure of init late function:
"agesawrapper_amdinitlate failed: 1"
It happens because TRUE = 1 = AGESA_UNSUPPORTED.
Replacing TRUE with AGESA_SUCCESS (= 0) fixes this problem.
Only family f15tn does not have such bug.
This patch just replaces TRUE with AGESA_SUCCESS, but maybe all DMI functions should be copied from Trinity family?
Tested on Supermicro H8QGI board with 4 AMD Opteron 6234 processors (f15).
Change-Id: I51bf91333c088a825b92d4a44d1ebe4380c8026c
Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2070
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
Add configuration for AMD's IMC ROM and fan registers for cimx/sb800
platforms.
- Allows user to add the IMC rom to the build and to configure the
location of the "signature" between the allowed positions.
- Allows for no fan control, manual setup of SB800 Fan registers, or
setup of the IMC fan configuration registers.
- Register configuration is done through devicetree.cb. No files need
to be added for new platform configuration.
- Initial setup is for Persimmon, but may be extended to any cimx/sb800
platform.
Change-Id: Ib06408d794988cbb29eed6adbeeadea8b2629bae
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1977
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Current ExecuteFinalHltInstruction function doesn't work well.
(at least in configuration
Supermicro board with Orochi AMD Opteron processors (model OS6234WKTCGGU))
System reboots when trying to halt core 2,4,6,8 or 10
(OS6234WKTCGGU is 12 core processor)
Based on this information, i think that code doesn't really work with
f15 compute unit (CU) system.
Replacing ExecuteFinalHltInstruction function with
analogous function from f15tn family code fix this problem.
Both functions written from the same cahalt.asm file, but f15tn version
seems more completed
Change-Id: I3942abcdf21f1b86a44c01cc477714e44a40b9cf
Signed-off-by: Kostr <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/1569
Tested-by: build bot (Jenkins)
Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
src/vendorcode/amd/agesa/f15/Porting.h has some conflicted typedef with
src/include/cpu/amd/common/cbtypes.h. These conflicted defines can lead to errors.
Change-Id: Idad0794018bf0bd0e4e52a5aa062a12766d56c8e
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/1592
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Something about HD audio was scrubbed. Take it back.
Change-Id: I0be96fd103f3ebd4e8c7ef09a184b71aa34ee3fd
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1427
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
The default return value should be AGESA_SUCCESS, which is zero. If it was set as TRUE,
the AGESA wrapper would think it was AGESA_UNSUPPORTED. That would make no sense. And it
would produce ASSERT warning in AGESA wrapper.
On my parmer board, with Engine sample processor, it can not create the correct DMI table.
Routine initlate will return AGESS_ERROR.
------Serial message---------
ASSERTION FAILED: file 'src/mainboard/amd/parmer/agesawrapper.c', line 427
DmiTable:100123c3, AcpiPstatein: 10010126, AcpiSrat:0,AcpiSlit:0, Mce:100111ba, Cmc:1001127c,Alib:1001ccd4, AcpiIvrs:0 in agesawrapper_amdinitlate
agesawrapper_amdinitlate failed: 5
-----------------------------
I believe the processor with acceptable name string will create the right DMI.
Change-Id: Ie86955cf9affffc964a7c9f4a2c63077ef2030de
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1350
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Remove all the repeated sections of code in cbtypes.h and place it
in a common location. Add include dir in vendor code's Makefile.
Change-Id: Ida92c2a7a88e9520b84b0dcbbf37cd5c9f63f798
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Reviewed-on: http://review.coreboot.org/912
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
For legacy free AMD systems, the #define LEGACY_FREE cannot
currently be overridden. This patch allows the platform_cfg.h
to override that. (I know we want to get away from that, but
for now...)
Also allow BIOS_SIZE to be overridden on SB700 cimx based
platforms.
Change-Id: I570115248bcbc686062bfb66acb56208240b847a
Signed-off-by: Martin L Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1018
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Change source file modes from 755 to 644
The following files have been grepped for changes:
*.c
*.h
*Kconfig*
*Makefile*
Change-Id: I275f42ac7c4df894380d0492bca65c16a057376c
Signed-off-by: Alec Ari <neotheuser@ymail.com>
Reviewed-on: http://review.coreboot.org/1023
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Change the ExecuteFinalHltInstruction to assembly code. so we can make
sure the code can run stackless.
Change-Id: I783ced6cf7c5bc29c12a37aef29077e610d8957d
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/622
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
