Commit Graph

26151 Commits

Author SHA1 Message Date
Richard Spiegel dd9b1d1dd5 soc/amd/stoneyridge/romstage.c: Move STAPM code to SOC specific
STAPM programming was created inside function OemCustomizeInitEarly().
It should be SOC specific, and called by agesawrapper just before the
call to OemCustomizeInitEarly().

BUG=b:116196626
TEST=build and boot grunt

Change-Id: I8a2e51abda11a9d60a9057b38f2a484e1c8c9047
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28705
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-24 16:57:37 +00:00
Pratik Prajapati e072247e6e skylake,kabylake: Add support to set eMMC tuning param from dev tree
Add support to set eMMC tuning params from the device tree so that it
can be configured per board.

BUG=b:112718426,b:112690628
BRANCH=none
TEST=Build nocturne image and checked values passed in dev tree is set
by FSP.

Change-Id: Ic71934dce9a1c380a057e579ca3fda41983b9385
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/28274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-09-22 00:41:45 +00:00
Justin TerAvest a5fbd140d0 mb/google/octopus: Create ampton variant
This commit creates an ampton variant for Octopus. The initial settings
are copied from Bip, but the following changes are made to support
hardware differences:

  * GPIO_66 is not connected (LTE).
  * GPIO_67 is not connected (LTE).
  * Updated comment for GPIO_134 (EC_AP_INT_ODL), but not configured yet.
  * GPIO_143 is not connected.
  * GPIO_144, GPIO_145 mapped to PEN_EJECT are not connected.
  * EN_PP3300_TOUCHSCREEN moved from GPIO_213 to GPIO_146.
  * GPIO_213 is not connected.
  * GPIO_214 is not connected.

BUG=b:111498206
TEST=None

Change-Id: I7d6cf19c906df19115b1101e3d91c62f5f3f61e3
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/28663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-21 20:35:24 +00:00
Lijian Zhao e391cbff7f mb/intel/coffeelake_rvp: Add whiskey lake rvp
Add new mainboard variant of whiskey lake rvp, which is primary
validation platform for whiskey lake silicon, support socket DDR4 memory
module.

BUG=N/A
TEST=Build and flash, confirm boot up into kernel on whiskey lake rvp
platform.

Change-Id: I4a5e8a9ec76d5e55e55ef9bf968825c17fbe9816
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/27628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-21 15:14:24 +00:00
marxwang 5b5656565b mb/google/poppy/variants/rammus: Disable command TriState for rammus
This patch sets the MRC UPD "CmdTriStateDis" to disable TriState for
the rammus boards. Rammus is LPDDR3 design without RTT for CMD/CTRL.

BUG=none
TEST=Run memtester app and also webgl fishtank on the LPDDR3 kabylake
     boards and also check the margin data is proper in FSP.

Change-Id: Iee115f49ba5b36dc5b0425e9da02b58cd19b2236
Signed-off-by: Marx Wang <marx.wang@intel.com>
Reviewed-on: https://review.coreboot.org/28568
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-21 14:30:52 +00:00
Lijian Zhao eaca95eaf4 mb/intel/coffeelake_rvp: Correct LPDDR4 to DDR4 in mainboard info
There's only DDR4 or LPDDR3 support for coffelake processor line,
details can be found out on EDS #570805.

BUG=N/A
TEST=N/A

Change-Id: I8ba6b6861b15b40b01237f87c8d55394f7fd6706
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-21 14:29:47 +00:00
Lijian Zhao b7d2a6fbf5 mb/intel/coffeelake_rvp: GPIO support for whiskey board
Add gpio programming difference for whiskeylake rvp platform.

BUG=N/A
TEST=N/A

Change-Id: I35a0384f828fd3219e0c3adb4830f5bdab800e32
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28367
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-21 14:15:01 +00:00
Elyes HAOUAS 951d9f6f96 soc/intel/denverton_ns/csme_ie_kt.c: Don't use device_t
Use of device_t is deprecated.

Change-Id: I9dde92314af8ef87a5acb550f0fb25b8ce875174
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-21 14:14:33 +00:00
Frans Hendriks 83e7324969 soc/intel/braswell/ramstage.c: Add SoC stepping D-1 support
No support for SoC D-1 stepping is available.

According to Intel doc #332095-015 stepping C-0 has revision
id 0x21 and D-1 revision ID 0x35.

Also correct the RID_C_STEPPING_START value for C-0.

BUG=none
TEST=Built, Intel Cherry Hill Rev F.

Change-Id: I29268f797f68aa4e3b6203e098485e0bd4a44fc4
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/27471
Reviewed-by: Wim Vervoorn
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-21 14:14:10 +00:00
Elyes HAOUAS dc03528355 sb/intel/bd82x6x: Don't use device_t
Use of device_t is deprecated.

Change-Id: I4909ebffc978f537bbf6269d9e27dbaca43daa10
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-21 14:13:02 +00:00
Elyes HAOUAS 756a0bd2fe soc/intel/quark/uart.c: Don't use device_t
Use of device_t is deprecated.

Change-Id: Ia50aa96901b979b947fd4d269b077814c06f60c6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28677
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-21 14:12:42 +00:00
Elyes HAOUAS a92b73f389 arch/{mips,power8}/include/arch: Don't use device_t
Use of device_t is deprecated.

Change-Id: I8790bc333caa367ef46bf80b5fecc3e90ef89ca0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-09-21 14:12:18 +00:00
Elyes HAOUAS 3d0af855d0 include/device/pnp.h: Don't use device_t
Use of device_t is deprecated.

Change-Id: I9364c9681dd89f09480368a997f6d1f04cde1488
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-21 14:11:54 +00:00
Tom Hiller 3a7e7c1998 Documentation: fix sphinx warnings
Fix warning from list in table cells for nri_registers.md

Change-Id: I2b77ad266d1c5f693536e161f96f3db19832989c
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/28354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-09-21 14:08:47 +00:00
Elyes HAOUAS 62bafca159 nb/via/vx900: Get rid of device_t
Use of device_t is deprecated.

Change-Id: I70dcefd5bc9864931f66bece1f044f806f5d7ae0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-09-21 14:06:25 +00:00
Elyes HAOUAS 0f416d6874 soc/intel/skylake: Don't use device_t
Use of device_t is deprecated.

Change-Id: Ifd1471a9cd76d2cea72262ed81b7071f31f7b375
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-21 14:05:22 +00:00
Elyes HAOUAS 4658a98a63 soc/broadwell: Don't use device_t
Use of device_t is deprecated.

Change-Id: Ifdf3d1870500812a417eaa5e93fcc168629c094f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-21 14:05:04 +00:00
Elyes HAOUAS e2d76a15d1 arch/riscv/include/arch: Don't use device_t
Use of device_t is deprecated.

Change-Id: If52de0d87b02419090b29a7cf1952905d3f975f6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28691
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-21 14:04:31 +00:00
Arthur Heymans 27d3f71f1d soc/intel/skylake: Include some microcode blobs
This included the microcode for some CPUID's found in
soc/intel/skylake/bootblock/report_platform.c (others are likely pre-release
SKU's)

The amount of FIT entries needed is currently 7 so setting
CPU_INTEL_NUM_FIT_ENTRIES is set to a safe 10 will be able to fit them all.

Change-Id: I3ba504a07b2697fe55ff8f28a934f761ae05a4ec
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-09-21 09:47:28 +00:00
Tristan Shieh 1f64e6aa85 google/kukui: Set up EC_IN_RW GPIO for ChromeOS
Set up EC_IN_RW GPIO to boot depthcharge. Without this patch,
depthcharge will fail to tell if the EC firmware is RW.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui and see in logs, that depthcharge detects
     EC_IN_RW GPIO.

Change-Id: Icb39d663f65b72e0ad54059c9590d9693106ee25
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/28670
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-21 07:08:36 +00:00
Nick Vaccaro d1d3e62f92 mb/google/poppy/variant/nocturne: set DMIC1 to NC
Change GPP_D17 and GPP_D18 to no connects as DMIC was moved
to DMIC0.

BUG=b:113744731,b:111106010
TEST=none

Change-Id: I8ef42627e542182707c81389af9da33a114bc184
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/28689
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-21 07:08:19 +00:00
Martin Roth 4ae44fce56 mainboard/google/kahlee: allow oem.bin file to update smbios
Grunt variants need a way to customize the mainboard vendor based on the
platform.  For future boards, this can probably be done via CBI, but
grunt doesn't support that method.

BUG=b:79874904
TEST=Build, boot, see updated mainboard vendor

Change-Id: I997dc39c7f36f70cf4320ef335831245889eb475
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/28651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@google.com>
2018-09-21 07:07:52 +00:00
Sumeet Pawnikar 06c14d0962 mb/google/octopus/variants/fleex: Update DPTF parameters
Update Power Limit1 and Power Limit2 values along with stepsize.
Correct the charger effect for Temperature sensor2.

BUG=b:112448519
BRANCH=None
TEST=Build coreboot for Octopus board.

Change-Id: I01e0a94fe694537d9eebe3b92c11d0c83137d716
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/28530
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-21 07:07:03 +00:00
praveen hodagatta pranesh 338c8002d2 soc/intel/cannonlake: Correct ITSS port id.
According to cannon lake PCH BIOS specification document #570374
target port id for interrupt and timer subsystem(ITSS) is C4 instead of C2.

BUG=None
TEST=None

Change-Id: I9f8783c682d2c4c4a86e1c9cf4b9c27a18fdf494
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/28698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Kin Wai Ng <nelsonaquik@gmail.com>
2018-09-21 02:21:40 +00:00
Arthur Heymans c423d7d8f1 mb/lenovo/{T500, R400, W500}: Unify variants under T400
A negative side-effect is that those boards disappear from the board-status
output, but this is an issue on all variants.

Change-Id: Ic80804dc1f7d9c6f83ceee3db667019532c31d4c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28626
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-20 17:22:21 +00:00
Lijian Zhao 63da206146 soc/intel/cannonlake: Remove const for spd_smbus_address
Remove const define for spd_smbus_address, the value can be updated
depends on platform configuration.

TEST=Build and Run on Whiskey Lake rvp platform.
Found-by: Converity Scan #1395725

Change-Id: Ib933ed872e9f85087bb3cd76a1f1e29cca75cd54
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28664
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-20 17:20:13 +00:00
Richard Spiegel 985a4fc96c soc/amd/stoneyridge/romstage.c: Remove obsolete comment
When preparing transition of AGESA calls to romstage, I placed a comment
indicating the place to move a particular call. Now that the AGESA call
has been moved to romstage, the comment became obsolete.

BUG=b:116095766
TEST=none.

Change-Id: I2811657385ab088747e32d4c66b99fdd01e7315e
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-09-20 17:18:02 +00:00
Mike Banon 6af5d81209 src/vendorcode/amd/agesa: Improve formatting of some f12 and f14 microcodes
It is much more convenient to view these files if there are 8 values per line,
not 1 value which results in a very long file. The contents remain the same:
these microcodes are still the latest publicly available at the time of writing.

Change-Id: I3e5296a5b5e895702a60aca1ded7418bb345263d
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-on: https://review.coreboot.org/28391
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-20 17:17:33 +00:00
Mike Banon 843b994163 src/vendorcode/amd/agesa/f12: Update microcode to version 0x3000027 2011-09-13
This microcode update for CPU ID 0x300F10 should improve the system stability.
It is a part of microcode_amd.bin officially released by AMD at linux-firmware:
it starts at 0x217C offset, and size is 0x03C0 as specified priorly at 0x2178.

    Old version:    0x300000F [2010-04-10]
            replaced by
    New version:    0x3000027 [2011-09-13]

Change-Id: I9650fab377d957904318ebb393323c2509cfea26
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-on: https://review.coreboot.org/28378
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-20 17:16:15 +00:00
Karthikeyan Ramasubramanian e209b96e53 mb/google/zoombini: Use Chrome EC BOARDID definition
The board_id() definition is the duplicate of chrome EC board_id
definition. Remove the duplicate definition and select
EC_GOOGLE_CHROMEEC_BOARDID Kconfig item.

BUG=b:114001972,b:114677884,b:114677887

Change-Id: Id8b7027d653649e8e5791e455652c4e893a746c2
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org>
Tested-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org>
Reviewed-on: https://review.coreboot.org/28609
Reviewed-by: Jett Rink <jettrink@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-20 17:15:53 +00:00
Karthikeyan Ramasubramanian c80ff8437d ec/google/chromeec: Update google_chromeec_get_board_version prototype
The helper function to get the board version from EC returns 0 on
failure. But 0 is also a valid board version. Update the helper function
to return -1 on failure and update the use-cases.

BUG=b:114001972,b:114677884,b:114677887

Change-Id: I93e8dbce2ff26e76504b132055985f53cbf07d31
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Tested-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/28576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@google.com>
2018-09-20 17:15:26 +00:00
Puthikorn Voravootivat 2beadeec35 mb/google/poppy/variants/nocturne: Update DPTF settings
Update DPTF settings based on recommendation from thermal team.

BUG=b:112550414
BRANCH=None
TEST=Manually tested by thermal team.

Change-Id: I26f09392a3293ce4b3481f2be341a667d606bc10
Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-on: https://review.coreboot.org/28666
Reviewed-by: Todd Broch <tbroch@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-20 17:13:11 +00:00
Wisley Chen 7e56626b0a mb/google/octopus: Enable DRAM_PART_NUM_IN_CBI feature for meep
Enable DRAM_PART_NUM_IN_CBI feature to get DRAM part number from CBI
and set DRAM_PART_IN_CBI_BOARD_ID_MIN to 1 for EVT.

BUG=b:115965629
TEST=verified it in meep proto board which rework ram id.

Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I962b099d5b9fbe0ca29708be1e9c6ed60b10d363
Reviewed-on: https://review.coreboot.org/28658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-09-20 17:11:47 +00:00
Piotr Król 063e1567d8 nb/amd/pi/00730F01: use MMIO and performance counters from AGESA
This patch contain minimal set of changes to initial IVRS implementation
to make it work reliably. Code in this patch was tested with Xen 4.8 and
Debian 4.14.y - this software stack survived 100x reboots without any
hang on PC Engines apu2c4. Previously using IVRS provided by AGESA lead
to 29/100 hangs.

MMIO base shall not be hard coded since this value depends on platform
design.

Performance counters were selected experimentally, since lack of
them cause 4.14.y panic:
[    1.064229] AMD-Vi: IOMMU performance counters supported
[    1.069579] BUG: unable to handle kernel paging request at ffffaffc4065c000
[    1.073554] IP: iommu_go_to_state+0xf8a/0x1260
[    1.073554] PGD 12a11f067 P4D 12a11f067 PUD 12a120067 PMD 129b69067 PTE 0
[    1.073554] Oops: 0000 [#1] SMP NOPTI
[    1.073554] Modules linked in:
[    1.073554] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 4.14.50 #13
[    1.073554] Hardware name: PC Engines apu2/apu2, BIOS 4.8-1174-gf12b3046f0-d2
[    1.073554] task: ffff8d5d69b9f040 task.stack: ffffaffc40648000
[    1.073554] RIP: 0010:iommu_go_to_state+0xf8a/0x1260
[    1.073554] RSP: 0018:ffffaffc4064be28 EFLAGS: 00010282
[    1.073554] RAX: ffffaffc40658000 RBX: ffff8d5d69bae000 RCX: ffffffff99e57b88
[    1.073554] RDX: 0000000000000000 RSI: 0000000000000092 RDI: 0000000000000246
[    1.073554] RBP: 0000000000000040 R08: 0000000000000001 R09: 0000000000000170
[    1.073554] R10: 0000000000000000 R11: ffffffff9a435e2d R12: 0000000000000000
[    1.073554] R13: ffffffff9a29a830 R14: 0000000000000000 R15: 0000000000000000
[    1.073554] FS:  0000000000000000(0000) GS:ffff8d5d6ec80000(0000) knlGS:00000
[    1.073554] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[    1.073554] CR2: ffffaffc4065c000 CR3: 000000010fa0a000 CR4: 00000000000406e0
[    1.073554] Call Trace:
[    1.073554]  ? set_debug_rodata+0x11/0x11
[    1.073554]  amd_iommu_init+0x11/0x89
[    1.073554]  pci_iommu_init+0x16/0x3f
[    1.073554]  ? e820__memblock_setup+0x60/0x60
[    1.073554]  do_one_initcall+0x51/0x190
[    1.073554]  ? set_debug_rodata+0x11/0x11
[    1.073554]  kernel_init_freeable+0x16b/0x1ec
[    1.073554]  ? rest_init+0xb0/0xb0
[    1.073554]  kernel_init+0xa/0xf7
[    1.073554]  ret_from_fork+0x22/0x40
[    1.073554] Code: d2 31 f6 48 89 df e8 d8 15 02 ff 85 c0 75 d1 48 8b 44 24 2
[    1.073554] RIP: iommu_go_to_state+0xf8a/0x1260 RSP: ffffaffc4064be28
[    1.073554] CR2: ffffaffc4065c000
[    1.073554] ---[ end trace 44588f98aa7c7c0b ]---
[    1.255973] Kernel panic - not syncing: Attempted to kill init! exitcode=0x09
[    1.255973]
[    1.259934] ---[ end Kernel panic - not syncing: Attempted to kill init! exi9

Possible future improvements:
- compare device entries with values returned by AGESA
- enable EFRSup (this is enabled in AGESA)
- try various IVHD flags (there is difference between initial
implementation and AGESA)

Change-Id: I7e3a3d21f295ae96962d7718b9568fc4b67eb23d
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-on: https://review.coreboot.org/27602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-09-20 15:12:18 +00:00
Werner Zeh 1a22d3bc7e soc/intel/fsp_broadwell_de: Add fixed VT-d MMIO range to the resources
FSP initializes the VT-d feature on Broadwell-DE and assigns an address
space to the MMIO range. coreboot's resource allocator needs to be aware
of this fixed resource as otherwise the address can be assigned to a
different PCI device. In this case addresses are overlapped and the VT-d
range is not accessible any more.

To deal with it the right way add a fixed MMIO resource to the resources
list if VT-d BAR is enabled.

TEST=Booted into Linux and checked coreboot log for resource assignment.

Change-Id: I626ac17420eadc0b49031e850f0f40b3b221a098
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/28672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-20 12:38:49 +00:00
Werner Zeh ca0c8e75f9 fsp_broadwell_de: Move DMAR table generation to corresponding VT-d device
The DMAR table generation depends on the VT-d feature which is
implemented in its own PCI device located in PCI:00:05.0 for
Broadwell-DE. Add a new PCI driver for this device and move
DMAR table generation to this device driver.

Change-Id: I103257c73f5e745e996a441a2535b885270bc204
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/28671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-20 12:38:02 +00:00
Evgeny Zinoviev 5a0b252ded mb/lenovo: Add libgfxinit support on Lenovo T520
Change-Id: I4fcdb7467f1911af722f4c24ce64807079a91340
Signed-off-by: Evgeny Zinoviev <me@ch1p.com>
Reviewed-on: https://review.coreboot.org/28620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-20 10:14:00 +00:00
Nico Huber 5ef3460d49 sb/intel/common/firmware: Ensure warning is put late
Change-Id: I400de0a622c2b45ea5ef1f1446f4f489ac397c32
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28673
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-20 10:13:25 +00:00
Marshall Dawson 638bd13a65 amd/stoneyridge: Sync PSP base to MSR
According to AMD, there exists an undocumented MSR which must be
written with the PSP's base address.  Read the value from the PSP's
config space and sync each core's copy of the MSR to match.

BUG=b:76167350
TEST=boot Grunt and verify "rdrand: disabled" goes away from dmesg

Change-Id: I30027d3b0a6fbd540375e96001beb9c25bf3a678
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28608
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-19 16:30:04 +00:00
Elyes HAOUAS 892af1801f arch/arm/include/armv7/arch: Remove dead code
Change-Id: Id3199d130825a5f796108ae45ce965325511ce8b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-09-19 10:35:09 +00:00
Elyes HAOUAS d34a785b49 src/device/device.c: Don't use device_t in ramstage
Use of device_t has been abandoned in ramstage.

Change-Id: I3d1bdefd00c91a98116ede5dc03c3ce253d1f0ed
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-09-19 10:35:01 +00:00
Arthur Heymans 2e3c880739 mb/asrock/g41c-gs: Link separate gpio.c files
With the addition of new boards using macros to set per board settings in the
same gpio.c file is getting too complicated so link separate files.

Change-Id: I3ab05f1af6ba0a04dd827816b3bcaa506a3f6aff
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-09-18 23:13:44 +00:00
Richard Spiegel 3a618dd214 mb/google/kahlee/variants/careena/devicetree.cb: Set STAPM values
AMD has tested careena, and for the time being is recommending a scalar
of 68%, power limit of 7.8 W and time constant of 2500. Using new STAPM
configuration code, set the desired values.

BUG=b:111561217
TEST=none, code was tested with grunt.

Change-Id: I42671ab0e66b21dc4f8c8c326c1fa33328b1390e
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-09-18 21:42:46 +00:00
Martin Roth c3f5293da7 mainboard/google/kahlee: Set EMMC reset pin to output low
While the pin was set to a pull-down, with the external pull-up, this
wasn't enough to keep the pin low.  Set to output low to drive to 0V.

TEST=Boot grunt, verify EMMC_BRIDGE_RST is 0V.
BUG=b:115661061

Change-Id: Ife014b8a879274df5d892c1de386976808de1df0
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/28649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-09-18 21:15:45 +00:00
Martin Roth 6b3038efc0 mainboard/google/kahlee: Don't set global subsystem IDs
These values override the default subsystem IDs, and aren't needed.

BUG=b:113253260
TEST=Boot grunt

Change-Id: I3c56534b094ede8d8200b72f4433a891d0094064
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/28652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-09-18 21:15:33 +00:00
Patrick Georgi fcc2950a60 util/lint: Ignore "visible if" statement in Kconfig files
They allow reducing the visible set of options to remove clutter.

Change-Id: I18c953c7feae23c0752392a2bf8f49783c17310e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-18 15:00:44 +00:00
Michał Żygowski 54fcb7862d mainboard/pcengines: select ADD_SEABIOS_SERCON_PORT_FILE
PC Engines boards are interfaced mainly via serial console.
Enable SeaBIOS serial console for these boards by default
when SeaBIOS selected as payload.

Change-Id: I9e65dd1e28859028c8c46f28a5442de8c59d4893
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/27824
Tested-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-09-18 14:48:33 +00:00
Elyes HAOUAS 4a13126393 soc/intel/common/block: Don't use device_t in ramstage
Use of device_t has been abandoned in ramstage.

Change-Id: If2d643eafea854563f56a7f867b7b492b6d09a19
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28631
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-18 10:49:06 +00:00
Elyes HAOUAS e1e455bc96 sb/amd/sr5650/sr5650.h: Get rid of device_t
Use of device_t has been abandoned in ramstage.

Change-Id: Ib4dbb607cfd1e02d45efe141b498d6505574d6e6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-09-18 10:38:01 +00:00
Elyes HAOUAS 27667a2c0b soc/cavium/cn81xx: Don't use device_t in ramstage
Use of device_t has been abandoned in ramstage.

Change-Id: Ifa54624664c06c606fb4e083bae98b4accc61be0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-09-18 10:37:32 +00:00