poppy schematics have undergone change after review, update
DQS and DQ Byte mappings based on the new schematics.
BUG=chrome-os-partner:61856
BRANCH=None
TEST= Build and boot all the poppy proto SKUs to OS.
Change-Id: Ie4532035f37c25540abb26122234f6e3346ede69
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18133
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
SBI calls, as it turned out, were never right.
They did not set the stack correctly on traps.
They were not correctly setting the MIP instead of the SIP
(although this was not really well documented).
On Harvey, we were trying to avoid using them,
and due to a bug in SPIKE, our avoidance worked.
Once SPIKE was fixed, our avoidance broke.
This set of changes is tested and working with Harvey
which, for the first time, is making SBI calls.
It's not pretty and we're going to want to rework
trap_util.S in coming days.
Change-Id: Ibef530adcc58d33e2c44ff758e0b7d2acbdc5e99
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/18097
Tested-by: build bot (Jenkins)
The values of highest_rank_count were undefined on DDR2 systems.
Explcitly define these values on DDR2 platforms.
Found-by: Coverity Scan #1347338
Change-Id: Iad7bb00db97b2816fcc44fb5941bd14373451da2
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18078
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
This code allows people to override the usb2 eye pattern
UPD settings for boards.
BUG=chrome-os-partner:61031
BRANCH=None
TEST=Usb2 function ok and make sure fsp upd is overridden
Change-Id: I5fab620a29aba196edf1f24ffe6a1695de1e523e
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/18060
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These updated header files contain USB tuning parameters as well as
some general cleanup of unused parameters in the UPD Headers. This
patch along with the upcoming FSP 1.3.0 release will allow for USB
tuning on apollolake platforms.
CQ-DEPEND=CL:*315403
BUG=chrome-os-partner:61031
Change-Id: Id7cce1ea83057630d508523ada18c5425804535e
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/18046
Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Baytrail SoC has a bug where in some cases the DisplayPort can hang
leading to a non-working display (it just stays black). To avoid this
hang, a patch was introduced in 02/2016
(1c3b1112fa - fsp_baytrail: Fix a possible hanging DisplayPort)
but per default not switched on so that each
mainboard can decide if it wants to use this patch or not.
Recently a new case of this bug was reported by Benoit Sansoni
(benoit.sansoni@kontron.com) and he requested to enable this fix per
default as it costs him a lot of time to find the cause and even the
already available fix in coreboot. To avoid this effort for someone
else in the future we can enable this fix per default as no negative
side effects are known and it is now tested at Siemens and at
Kontron on different mainboards with success.
As the goal is to enable this code permanently the config switch is not
longer needed and is removed.
Change-Id: I15bd682218d0dc887945cc91ee3e5488945a6355
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/18109
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
The comparison value was obviously wrong here. One too many 'f'
characters.
Found-by: Coverity Scan #1229588 & 1229604
Change-Id: Iedd4f956d846f1c8661390b346c7397346def86b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18100
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
After we set the GET_TIME bit, the rtc time can't be read immediately. We
should wait up to 31.25 us, about one cycle of 32khz. Otherwise reading
RTC time will return a old time.
BUG=chrome-os-partner:61078
BRANCH=veyron
TEST=Build and Boot
Original-Change-Id: I6ec07fc6c4d6d8b27b12031423b86b8ab15da6f6
Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/423272
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Change-Id: I9806b624d6e968e51d52aab8c052ae3fa77f247d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b4b708e29fbae0d8f5a2cece79711aa6b1887727
Original-Change-Id: I8c168c14437bb932a59ac0e91a01062df0cf11dc
Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/427522
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18127
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The commit 0ba3b2593b0c ("gru: Tuning USB 2.0 PHY to increase
compatibility") bypass ODT to set the max driver strength for
the Type-C otg-port, it works well on otg-port when connected
with USB2.0 devices.
Unfortunately, because the Type-C otg-port and host-port are
consisted in one USB2 PHY, so bypass ODT will have an effect
on both host-port and otg-port. I have tested the host-port
eye-diagram, the result shows that if we bypass ODT, the host-
port eye-diagram height will become to high, more than 500mv,
this may cause USB 2.0 high-speed enumeration failure.
This patch bypass ODT for host-port separately, and then we
can reduce the host-port driver strength without affecting
the otg-port driver strength.
BRANCH=gru
BUG=chrome-os-partner:60727
TEST=Boot system, run 'lsusb' command and check if the usb camera
and usb bluetooth are on usb 2.0 hub or usb 1.1 hub. If they are
on usb 1.1 hub, the issue happens. If not, try to run camera app
and then close camera app, repeat until find that the usb camera
is on the usb 1.1 hub.
Change-Id: Ib693e2a6f2113c06692a7bfee22d85b67ee3b165
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5ea7660b7b05080b76fc5ca5af3fa18552a03491
Original-Change-Id: Ia1f12182929673c5726df9f77f0903469b5c957a
Original-Signed-off-by: William wu <wulf@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/425739
Original-Commit-Ready: Douglas Anderson <dianders@chromium.org>
Original-Tested-by: Douglas Anderson <dianders@chromium.org>
Original-Tested-by: Inno Park <ih.yoo.park@samsung.com>
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://review.coreboot.org/18126
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Currently we just disabled ohci interrupts when calling ohci_shutdown,
Which would not actually shutdown the ohci controller, for example it
may still written the increased HccaFrameNumber to Hcca buffer.
Perform a soft reset to ohci controller as the linux kernel ohci-hcd
driver does.
BUG=chrome-os-partner:60996
BRANCH=None
TEST=Checked on gru, no more "BUG: Bad page state" error in kernel.
Change-Id: I128ab6ba455ac5383a4d48be0bc12b8bb4533464
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4749fc82fdd1b74ca3f2ed3fdf0ef53a5e161087
Original-Change-Id: I3f192aea627ba2fa69533bc0a4270466ca18f2a7
Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/426338
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://review.coreboot.org/18125
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
BUG=chrome-os-partner:56947
TEST=Verifed country code can be parsed from VPD in depthcharge.
BRANCH=None
Change-Id: I2fbbd4a784c50538331747e1ef78c33c6b8a679b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: acea6e2a200e8bd78fd458255ac7fad307406989
Original-Change-Id: I4616fefc6a377d7830397cdadb493927358e25cc
Original-Signed-off-by: Kan Yan <kyan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/425819
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/18124
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This driver to configure the clock generator is not used.
Change-Id: I156a42dfc336ff45acdcb6d8618bbd12671b66a7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18104
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Cosmetic changes to rename car_stage.S to car_stage_fsp20.S,
so that it is associated with FSP driver version that is being used.
Tested on Kabylake Rvp11.
Change-Id: I869df6eb746e3982e5912c272255eab6cb008838
Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com>
Reviewed-on: https://review.coreboot.org/18083
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
To support intel wifi SAR configuration, it is required coreboot
to publish two ACPI objects (WRDS and EWRD) to supply SAR limit
data sets. VPD entry "wifi_sar" is required to supply the raw SAR
limit data.
BUG=chrome-os-partner:60821
TEST=Enable USE_SAR, boot reef to OS, create the VPD entry, reboot,
check the SSDT dump and verify WRDS and EWRD structures.
Change-Id: I6be345735292d0ca46f2f7e7ea61924990d338a8
Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Reviewed-on: https://review.coreboot.org/17959
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Current fw does not create ACPI device for
OS to recognize ELAN touchscreen.
List the touch screen in the devicetree so that
the correct ACPI device are created.
BUG=chrome-os-partner:61803
BRANCH=reef
TEST=emerge-pyro coreboot
Change-Id: I9015fa63ef3aba74b682da3608a05ee49c4947c5
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/18086
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This updates the configuration for ARM CrOS devices (nyans and veyrons)
by using the CHROMEOS Kconfig option, thus reducing the number of
options to select. It also brings proper serial console support.
Change-Id: Iffc84c44a1d339c5bb575fbaffc40bc2d56bb6cf
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/17928
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
cbfstool ... add ... -c precompression assumes the input file to be
created by cbfs-compression-tool's compress command and uses that to add
the file with correct metadata.
When adding the locale_*.bin files to Chrome OS images, this provides a
nice speedup (since we can parallelize the precompression and avoid
compressing everything twice) while creating a bit-identical file.
Change-Id: Iadd106672c505909528b55e2cd43c914b95b6c6d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/18102
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
cbfs-compression-tool provides a way to benchmark the compression
algorithms as used by cbfstool (and coreboot) and allows to
pre-compress data for later consumption by cbfstool (once it supports
the format).
For an impression, the benchmark's results on my machine:
measuring 'none'
compressing 10485760 bytes to 10485760 took 0 seconds
measuring 'LZMA'
compressing 10485760 bytes to 1736 took 2 seconds
measuring 'LZ4'
compressing 10485760 bytes to 41880 took 0 seconds
And a possible use for external compression, parallel and non-parallel
(60MB in 53 files compressed to 650KB on a machine with 40 threads):
$ time (ls -1 *.* |xargs -n 1 -P $(nproc) -I '{}' cbfs-compression-tool compress '{}' out/'{}' LZMA)
real 0m0.786s
user 0m11.440s
sys 0m0.044s
$ time (ls -1 *.* |xargs -n 1 -P 1 -I '{}' cbfs-compression-tool compress '{}' out/'{}' LZMA)
real 0m10.444s
user 0m10.280s
sys 0m0.064s
Change-Id: I40be087e85d09a895b1ed277270350ab65a4d6d4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/18099
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This speeds up the lzma encoder approximately four-fold.
Change-Id: Ibf896098799693ddd0f8a6c74bda2e518ecea869
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/18098
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
mvmap2315_reset() is called from locations where we're checking for NULL
pointers. Because coverity can't tell from the code that the functions
are not returning, it's showing errors of accessing pointers after
we've determined that they're invalid.
Mark it as noreturn, and add a loop in case the reset isn't on the
next instruction. This probably isn't needed, but shouldn't hurt.
Found-by: Coverity Scan #1362809
Change-Id: If93084629d5c2c8dc232558f2559b78b1ca5de7c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18103
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Other chips dump tco_status here if it wasn't handled, which makes
sense.
tco_sts can't be zero here, because the call would have already returned
if it were. Also, dump_tco_status wouldn't print anything if tco_sts
were zero.
This will still only print the debug information if DEBUG_SMI is
enabled in Kconfig, so in general, this change won't have much of an
effect on anything.
Found-by: Coverity Scan #1229598
Change-Id: Id2c69a16817ba18dfa051f514138fbc04a2f7bee
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18101
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Updated to arm-trusted-firmware TOT:
236c27d2 (Merge pull request #805 from Xilinx/zynqmp/addr_space_size)
183 commits between Sep 20, 2016 and January 10, 2017
- Also add associated change to src/soc/rockship/rk3399 Makefile.inc
that is required to build the M0 Firmware.
Change-Id: I49695f3287a742cd1fb603b890d124f60788f88f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18024
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This should always have been an and, not an or.
The only way this would happen is if no GPIOs were getting configured,
so we shouldn't ever have a NULL here, but if we did, GPIOs would
be randomly configured, which would have 'interesting' results.
Found-by: Coverity Scan #1229633 & 1229632
Change-Id: If123372658383f84279738e1186425beba3208ca
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18095
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
On Chrome OS devices that use TPM2 parts the platform hierarchy
is disabled by the boot loader, depthcharge. Since the bootloader
isn't involved in resuming a suspended machine there's no equivalent
action in coreboot to disable the platform hierarchy. Therefore, to
ensure consistent state in resume the platform hierarchy in the TPM2
needs to be disabled as well. For systems that resume using the
firmware the platform hierarchy is disabled when utilizing
TPM2 devices.
BUG=chrome-os-partner:61097
BRANCH=reef
TEST=Suspend and resume. Confirmed 'stop trunksd; tpmc getvf; start
trunksd' shows that phEnable is 0.
Change-Id: I060252f338c8fd68389273224ee58caa99881de8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/18096
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The orphaned Tab_TrefT_k causes a failure to build due to
an unused variable warning on GCC 6. Remove this variable.
Change-Id: Ida680a6a3bc2b135755dd582da8c6edb8956b6ff
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18094
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Die if cbmem_add can't allocate memory for the hob pointer. This
shouldn't ever happen, but it's a reasonable check.
- fsp_broadwell_de already had a check, but it returned to someplace
inside the FSP. Just die instead.
Change-Id: Ieef8d6ab81aab0ec3d52b729e34566bb34ee0623
Found-by: Coverity Scan #1291162
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18092
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Build issues were somehow overlooked in commit
ed840023a84915ece4bc63edffef979926107d55:
1. hexstrtobin is not defined (needs the lib.h);
2. coreboot default compiler doesn't like variable initialization
within for loop.
BUG=chrome-os-partner:60821
TEST=Build and boot lars and reef
Change-Id: Ie52c1f93eee7d739b8aaf59604875f179dff60d0
Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Reviewed-on: https://review.coreboot.org/18076
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
An unintended sign extension warning was thrown by Coverity.
Explicitly state the length of the constant multiplier.
Found-by: Coverity Scan #1347342
Change-Id: Icd42eec13be04fc5fd2ffc85320cbadafc852148
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18077
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Logic inside mct_EnableDimmEccEn_D uses an unintialized variable as
a register address under certain conditions. Refactor mct_EnableDimmEccEn_D
to use the explicit address of the register in all cases.
Found-by: Coverity Scan #1347337
Change-Id: I6bc50d0524ea255aa97c7071ec4813f6a3e9c2b8
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18079
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The FSP 2.0 change broke the logic for determining whether or not
to execute the GOP binary. Modify the FSP 2.0 code to do the right
thing and check for display_init_required() before passing VBT into
FSP and the GOP binary.
BUG=chrome-os-partner:61726
TEST=disable developer mode and ensure FSP does not run GOP
Change-Id: I7fc8055b6664e0cf231a8de34367406eb049dfe1
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18084
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Malloced resources were not freed in failure branches during
S3 parameter save. Clean up Coverity warnings by freeing
resources in failure branches.
Found-by: Coverity Scan #1347344
Change-Id: I5f119874e52ef2090ca1579db170a49a2a6a0a2a
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18074
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The existing DRAM clock speed to configuration value logic contained
an error resulting in a theoretical out of bounds read. While this
would not be hit on real hardware, it was prudent to clean up the
logic to avoid the associated Coverity warning.
Found-by: Coverity Scan #1347353
Change-Id: Ic3de3074f51d52be112a2d6f2d68e35dc881dd2e
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18073
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The existing code inadvertently calculated the maximum read
latency for nonexistent channel 2 instead of for channels
0 and 1 as intended. Fix the calls to the maximum read latency
training function.
Found-by: Coverity Scan #1347354
Change-Id: If34b204ac73cd20859102cc3b2f40bc99c2ce471
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18072
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Fix SPI flash ops regressions after commit:
c2973d1 spi: Get rid of SPI_ATOMIC_SEQUENCING
When spi_flash_cmd() is called with argument response==NULL,
only send out command without reading back the response.
Change-Id: I28a94f208b4a1983d45d69d46db41391e267891d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18082
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The critical delay delta was incorrectly specified as an
unsigned short. Use a signed short instead.
Found-by: Coverity Scan #1347355
Change-Id: I37d769afb8c8af85a0375ae459e9d4ab0adcca74
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18071
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
The existing logic to set up CsMux45 used an incorrect mask
and comparison value due to a copy + paste editing error.
Use the correct mask and comparison value for the last two
values.
Found-by: Coverity Scan #1347385
Change-Id: Ic08a52977df90b9952e434e71cd12dbc6d7e1443
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18070
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The existing code waiting for northbridge P-state transitions
contained a logical error preventing correct operation. Fix
the logical error and force coreboot to wait for the P-state
transitions per the BKDG.
Found-by: Coverity Scan #1347388
Change-Id: I35f498c836db1439734abe684354c18c8e160368
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18069
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
The code to set the igd frequencies is written with the mobile version
of the 945 chipset in mind and seems to cause cause strange igd
related problems on the desktop versions.
Some possible problems are:
* on 800MHz fsb CPUs the igd sometimes has artifacts on the screen;
* on 800MHz fsb CPU memtest results vary a lot;
* since a commit 45e11aa0a5 "Add/Combine Broadwell Chromebooks using
variant board scheme" that does not affect this northbridge, the
display shows garbage as soon as Linux (4.8) modesets the display.
A fix is to hardcode the core display and render clocks to their
maximum, potentially also improving graphical performance.
Vendor bios on all boards in coreboot with this northbridge have the
same value in this PCI config address.
TESTED on P5GC-MX (display works fine again in Linux) and
user reports of it making GA-945GCM-S2L run more stable.
Change-Id: I8b046edbc952631d9b79023e3d385160ff682c24
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17981
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
On AMD DDR3 platforms, the upper DQMask was incorrectly
calculated, leading to undefined behaviour and possible
DRAM training faults. Use the correct calculation for
the upper DQMask.
Found-by: Coverity Scan #1347394#1347393
Change-Id: If3190eb7c30f1f00d6fd8b751bc1761c9d119782
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18068
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The Lenovo T400 has a CPU socket that can fit quad cores.
Change-Id: I585775ac9510cc7d2c2d731531f536c1a56b81e8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18059
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Update to Chromium TOT with bcffec7f (reef: Cleanup battery code)
292 commits between Oct 28, 2016 and Jan 2, 2017
Change-Id: I6bc356b9e458bebaa5839375ff40dd7e0d6ccff1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18023
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Rizwan Qureshi