Commit Graph

28404 Commits

Author SHA1 Message Date
Philipp Bartsch e8fb3dfa6c Documentation/gfx/libgfxinit.md: Align line breaks
Remove word splitting '-' at line breaks, since they show up within the
lines of the rendered html.

Change-Id: Ifbd43628f60057a0666fe221de1fe85f0a29cd2d
Signed-off-by: Philipp Bartsch <phil@grmr.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32147
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-04 10:36:20 +00:00
Philipp Bartsch 81cd0b0aab Documentation: Fix invisible text
Encapsulate angled brackets in backticks '<filepath>' to make text
visible in html rendering.

Change-Id: I1ab926956c909aa3cd2fd92068ccb7b800dd1d4a
Signed-off-by: Philipp Bartsch <phil@grmr.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32146
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-04 10:36:03 +00:00
Philipp Bartsch 654d7b5e0b Documentation: Fix broken link
Change-Id: Idd08bc49fb7bf3770e03f747d97d90aacc12eada
Signed-off-by: Philipp Bartsch <phil@grmr.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-04 10:35:24 +00:00
Martin Roth 0828d03de2 soc/nvidia/tegra210: Increase bootblock size
There's an issue with the newest toolchain that is blowing the bootblock
size on Smaug when compiling for chromeos.  Increasing the bootblock
size by 2KB will take care of the issue for a while.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I58f7f1cedc8fc5b4c4287f5a120ed76140e1f7a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-04-04 10:34:51 +00:00
V Sowmya e8c655dd1b mb/intel/coffeelake_rvp: Configure FSP UPDs of DDI ports for cmlrvp
This patch configures FSP UPD values for HPD and DDC of DDI ports for
CMLRVP.

BUG=none
TEST= Tested that eDP works on CMLRVP.

Change-Id: If8c8480eaf2d63cec0b5598b5af3088c630dd78a
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32140
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-04 10:34:28 +00:00
Shelley Chen c10fed0743 mb/google/hatch: Add Kohaku board
Adding Kohaku as a variant of hatch.

BUG=b:129706980
BRANCH=NONE
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
     make sure HATCH_KOHAKU is built as well.

Change-Id: I5b451f421f6d353005e6b73eac180dcec2e8b0c0
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-04 10:34:14 +00:00
Shelley Chen c76409ca35 mb/google/hatch: Create kohaku variant
Creating Kohaku hatch variant.  Currently taking a copy of the hatch
variant.  Kohaku-specific changes to come in future CLs.

BUG=b:129706980
BRANCH=NONE
TEST=NONE

Change-Id: Ib4b8c2c8332910d992549e3aae8e6aff5234698b
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32160
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-04 10:34:09 +00:00
Joel Kitching e556f716e4 vboot: remove Kconfig option VBOOT_PHYSICAL_REC_SWITCH
This option is duplicated in depthcharge:
https://crrev.com/c/1545144

BUG=b:124141368, b:124192753, chromium:943150
TEST=make clean && make test-abuild
CQ-DEPEND=CL:1545144
BRANCH=none

Change-Id: I48e20ad21cdcb948a23387d3e5fcf142723b0c82
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-04 10:33:38 +00:00
Eric Lai b80ae90b6e mb/google/hatch: Enable Goodix Touch Screen
Enable Goodix touch screen.
Follow GT7375P_Datasheet_Rev.0.1

BUG=b:124460799
BRANCH=None
TEST=local build and tested with Goodix touch screen

Change-Id: Ib204e6b77b87ba6c775cf38e572476dd9eb37d1d
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32134
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-03 21:52:35 +00:00
Jacob Garber 3eebb16c05 util/arm_boot_tools/mksunxiboot: Correct format strings
%lx is the right format string for printing longs.

Found-by: Coverity Scan, CID 1229686, 1229687
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Ib7ab54dc039bdd60969c79f3c881d69fc68f0d2a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-03 16:57:19 +00:00
John Su 0a4dcee75f mb/google/sarien/variants/sarien: Update thermal configuration for DPTF
Follow thermal table for second tunning.

BUG=b:129509918
TEST=Built and tested on sarien system

Change-Id: I64844b84891dc3ab7abe9378cdca5dcf57b3e433
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2019-04-03 08:46:25 +00:00
Werner Zeh 622a28d22b util/kconfig: Fix missing library issue with ld 2.24 and newer
When invoking 'make menuconfig' with gcc 4.9.2 an error is thrown:

ld: build/util/kconfig/lxdialog/checklist.o: undefined reference
to symbol 'acs_map'

This happens with ld version 2.24 and newer when menuconfig is
executed for the first time after make clean. This does not happen
with ld 2.20 (part of gcc 4.4.7).

It can be fixed with the flag -ltinfo in HOST_LOADLIBES.

Change-Id: I6216bb4d276d4bf98aa4ec06457b809fdcd73235
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-03 05:29:16 +00:00
Matt DeVillier 74dec7f51d payloads/tianocore: Don't fail on resetting boot logo
If using a commit/branch which doesn't use a boot logo,
we don't want the build to fail unnecessarily

Test: build with upstream Tianocore commit hash,
avoid failure after successful compilation.

Change-Id: Ic41bacbb97926e9538f434aecc0f0eebc5f6326f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-02 16:32:48 +00:00
Balazs Vinarz 28def8b5a0 util/lint: list files with whitespace issues
Change-Id: I8ae13f62c6e2cd87278fefab8de5faf0d1bc0a90
Signed-off-by: Balazs Vinarz <vinibali1@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-02 14:58:12 +00:00
Julius Werner 6d9c131061 vboot: Change oprom checks to CONFIG_VBOOT, assert OPROM_MATTERS
Skipping display init on normal-mode boot is a vboot feature, not
specific to Chrome OS. Fix the code in display_init_required() and
pci_dev_init() to check CONFIG_VBOOT rather than CONFIG_CHROMEOS now
that the two aren't always the same anymore.

Also add a check to guarantee at compile time that
CONFIG_VBOOT_OPROM_MATTERS is enabled on all platforms that make a check
to this function (when CONFIG_VBOOT is also enabled). The whole display
skipping mechanism is based on the oprom_needed NVRAM flag, and skipping
display init without enabling the option to tell vboot that it needs to
pay attention to that flag would make the whole thing not work right.

Change-Id: I5d6421509bdcdaa61b78015af3fa6241fe75bb7f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-02 13:08:43 +00:00
Ran Bi b197808852 mediatek/mt8183: Fix RTC initialization flow
1. Fix RTC lpd settings. Rewrite powerkeys after lpd init
   to enable low power detect function.
2. Rearrange RTC initialization flow.
3. Add return status for rtc_init.
4. Add log if calling pwrap_write or pwrap_read fail.
5. Increase timeout time to resolve unexpected timeout.

BUG=b:127405695
BRANCH=none
TEST=Boots correctly on Kukui

Change-Id: I6f26edd6699c2f6d9af80c285b70742b44407136
Signed-off-by: Ran Bi <ran.bi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2019-04-02 10:25:42 +00:00
Frank Wu 274613303e mb/google/poppy/variants/nami: update sku_ids for Pantheon
The sku ids are updated for Pantheon.
Sync'ing the sku_ids list in the master sku sheet for Pantheon.

BUG=b:121207221
BRANCH=firmware-nami-10775.B
TEST=emerge-nami coreboot chromeos-bootimage

Change-Id: Ibf683ca8219b2980ea9d9c40b06db264d58440b0
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2019-04-02 10:25:12 +00:00
John Su eb7720e00a mb/google/hatch: Change GPIO_E1 setting
For HW require to change GPIO_E1.
Change GOIO_E1 setting from NF2(SATAGP1) to NF1(SATAPCIE1).

BUG=b:123730924
TEST=flash BIOS and make sure hatch boots up properly

Change-Id: I0f5569e13b17a2dc713be5031a63436e8f31f911
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32099
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-02 10:22:29 +00:00
Krishna Prasad Bhat c41b0e8ea3 mb/google/hatch: Re-configure GPP_A12 as GPO before entering sleep
GPP_A12 has a Native3 (SX_EXIT_HOLDOFF#) mode, which allows to delay
resuming to S0. If this pad is not locked and platform was not initially
designed for this functionality, malware could reconfigure this pads
setting under OS (switch to Native3), which would make platform not able
to resume until G3 is applied. To prevent misuse of this pad,
re-configure this pad before entering S3 and S5 to guarantee that the
pad configuration is correct.

BUG=b:128686027

Change-Id: I1e7979baa491acf2c56d223afb4618f0f6429e37
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-02 10:21:59 +00:00
Subrata Banik 51c8532c6b drivers/intel/fsp2_0: Use same stack with coreboot
This patch ensures to have same stack base for FSP and coreboot.

Feature added in FSP2.1
- Remove stack swapping from FSP.
- Stack will be shared between coreboot and FSP.

TEST=Build and boot FSP2.1 enable platform like dragonegg, iclrvp.
No car global variable corruption seen after enabling
this feature.

Change-Id: I673b4216d991d8ccad725c3931006a694184106c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32079
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-02 02:18:24 +00:00
Elyes HAOUAS 17fa9deef1 mb/aopen/dxplplusu: Remove redundant use of ACPI offset operator
Change-Id: I790303a1fab64dbbe749563325394b9be2c109ad
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-01 18:37:34 +00:00
Patrick Rudolph 9b545df90b util/spdtool: Add tool to extract SPD from BLOBs
Opens a binary file to extract DDR SPDs using known bits.
At the moment only DDR4 SPDs are supported.
Dumps the found SPDs into the current folder, as either
binary or hex encoded file.

Works with python2 and python3.

Change-Id: I26dd73d43b724ea6891bb5b6e96856c42db8577c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-04-01 08:03:29 +00:00
Jacob Garber b6d91753fc payloads/coreinfo: Free buffer before returning
This fixes a memory leak, which was partially resolved in
2d1e0eb (payloads/coreinfo: Free buffer before returning).

Found-by: Coverity Scan, CID 1373370 (RESOURCE_LEAK)
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I0efe94b9dfb27746828055427029c01c7f407ec2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32094
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-01 08:02:38 +00:00
Julius Werner 988ac294c7 assert: Make dead_code() work at link-time instead of compile-time
The dead_code() macro can be used to ensure that a certain code path is
compile-time eliminated (e.g. if you want to make sure it's never
executed for certain Kconfig combinations). Unfortunately, the current
implementation via __attribute__((error)) hits only at the GCC level.
This can catch code that can be compile-time eliminated based on state
within the same file, but it cannot be used in cases where a certain
library function is built but then garbage collected at link time.

This patch improves the macro by relying solely on the linker finding an
undefined reference. Unfortunately this makes the error message a little
less expressive (can no longer pass a custom string), but it is still
readable and one can add code comments next to the assertion to
elaborate further if necessary

Change-Id: I63399dc484e2150d8c027bc0256d9285e471f7cc
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32113
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-01 07:57:00 +00:00
Julius Werner 9993b6f0b5 vboot: Select CONFIG_VBOOT_OPROM_MATTERS in more cases
This patch enables CONFIG_VBOOT_OPROM_MATTERS in a few more cases where
I think(?) it should be. Haswell, Broadwell and Baytrail Chromebooks
have this enabled in their old depthcharge firmware branches -- we
presumably just forgot to move it over when vboot2 migrated the option
to coreboot. Braswell didn't, but it seems like this requirement was
added when it was migrated to FSP 1.1...? (Not very sure about that one,
but it does call load_vbt() right now which executes things based on
display_init_required().) Additionally, it seems to make sense to enable
it whenever the user explicitly selects VGA_ROM_RUN in menuconfig (like
one of the Intel defconfigs does).

Once we have all this, one could take a step back and ask whether this
option still makes sense at all anymore. It's enabled for almost all
devices (that work with vboot at all), it will presumably be enabled for
all future devices, and it seems that most devices that don't enable it
use libgfxinit, which as far as I can tell isn't gated on
display_init_required() but probably should be. Realistically, whatever
kind of display init a board needs to do (native or option ROM), it's
probably expensive enough that it's worth skipping on a normal mode
vboot boot, and we'd want to have this enabled by default on everything
except boards that actually don't have a display. So maybe we should
flip it around to CONFIG_VBOOT_OPROM_DOESNT_MATTER, but doing that would
probably lead to nobody ever selecting it at all.

Not sure what the best solution there is yet, but I think this patch
at least moves things in the more correct direction.

Change-Id: Id96a88296ddb9cfbb58ea67d93e1638d95570e2c
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-01 07:56:48 +00:00
Lijian Zhao cd429a8b0c mb/google/sarien: Enable Bluetooth RF kill
Add bluetooth Rfkill function to recover the Bluetooth controller in
cases where itself has entered a bad state and needs to be recovered.

Bug=b:129375810
TEST=Boot up into OS and dump SSDT table, check there's _DSD entry under
Bluetooth devices with GPIO in. Also confirm bluetooth itself is
functional.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I79a310a55d94d7d20d1705afc11fe47cbb81abc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-04-01 07:55:12 +00:00
Daniel Lim Wee Soong df2dbbc817 cpu/ti/am335x: Fix checkpatch warnings
Replace occurences of 'unsigned' with 'unsigned int' to fix

	WARNING: Prefer 'unsigned int' to bare use of 'unsigned'

Signed-off-by: Daniel Lim Wee Soong <weesoong.lim@gmail.com>
Change-Id: I94665e8fcb4719521d143774aa84f630b10ee68a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
2019-04-01 07:54:40 +00:00
Krishna Prasad Bhat 847289d49e mb/google/hatch: Unlock GPIO pads
GPP_A12 is being used as FPMCU_RST in hatch. This GPIO is being padlocked in
FSP and cannot used in kernel. Hence unlock the GPIO pads to export this pin
in kernel to be used as FPMCU_RST.

BUG=b:128686027
BRANCH=None
TEST=Read Pad Configuration Lock (PADCFGLOCK_GPP_A_0) register.
localhost /sys/class/gpio # iotools mmio_read32 0xfd6e0080
0x00000000
localhost /sys/class/gpio # echo 212 > export

Change-Id: Ie0439956e6c8e386435e535665ccaf2ab82adeb0
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32126
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-01 07:53:05 +00:00
Krishna Prasad Bhat dffa8d05e3 soc/intel/cannonlake: Add FSP UPD to unlock GPIO pads in devicetree
FSP has a UPD to unlock all GPIO pads. This parameter is disabled by
default. Add a chip parameter so that GPIO pads can be unlocked on mainboard
level in devicetree and therefore this feature can be used if needed.

BUG=b:128686027

Change-Id: Iad9e8a209dc3f8ca0c994e8c1da329918409a1d4
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-01 07:52:50 +00:00
Simon Newton 690d27faa7 mainboard/asus/p8h61-m_pro : Support TPM module
Select support in Kconfig and configure device in devicetree
Tested with ASUS addon TPM modules, v1.2 (ASUS TPM-L FW3.19 rev1.02H) and v2.0 (ASUS TPM-L R2.0 rev1.00) using SeaBIOS and Linux OS

Change-Id: Icdad9a41b61221b536f2ac695f44319f6b0599e7
Signed-off-by: Simon Newton <simon.newton@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-03-31 15:08:33 +00:00
Elyes HAOUAS eb789f0b79 src: Use include <reset.h> when appropriate
Change-Id: I3b852cae4ef84d257bf1e5486447583bdd16b441
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-29 20:00:20 +00:00
Elyes HAOUAS 28fa33ccbc arch/x86/smbios(type4): Write processor_upgrade field
Change-Id: I1bf5ac6c411720d349df8fd706015c6835758cd0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29529
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-29 18:58:06 +00:00
Lijian Zhao 009e6cbf84 soc/intel/cannonlake: Ignore GBE LTR
Ignore integrated GBE controller LTR setting to make it wake up from
s0ix with 10/100M cable attached.

BUG=b:122435844
TEST= Test on sarien platorm, after the changes sytem can wake by WOL,
and also checked SLP_S0 residency can increase with 10/100M cable
and battery connected.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Iec7dd197b8a456751f8e4dcb19e3e153f5888613
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-03-29 14:55:54 +00:00
Mike Hsieh 06d0705834 mb/google/arcada: Make bluetooth reset_gpio active low
Follow b:129375810 to set bluetooth reset_gpio as ACPI_GPIO_OUTPUT_ACTIVE_LOW

BUG=b:129375810
TEST=Verified BT function on Arcada DVT1 system.

Signed-off-by: Mike Hsieh <mike_hsieh@wistron.corp-partner.google.com>
Change-Id: I816eb2a76f642a2bb1702f38138bce7916334011
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-03-29 14:52:58 +00:00
Mike Hsieh 92f2853e53 mb/google/arcada: Make touchscreen IRQ level triggered
Touchscreen lost function after boot with stylus
touching the screen

BUG=b:128554235

Signed-off-by: Mike Hsieh <mike_hsieh@wistron.corp-partner.google.com>
Change-Id: I692fc6f245b7fade67862da4986a83d11a2cd51f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32100
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-29 14:52:50 +00:00
Maulik V Vaghela 9f11629495 mb/google/hatch: Deassert EN_PP3300_WWAN during sleep
Deassert EN_PP3300_WWAN to turn the WWAN module completely off when
entering S5. This is the same fix in commit eeb475c5c for coral board.

BUG=none
BRANCH=none
TEST=On hatch, Perform a quick system power cycle, verify that the modem
is powered cycle and the SIM with PIN lock enabled requests unlocking.

Change-Id: I3ec8ccb7618189b9e8586f5571a68d3309597ee7
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-29 06:36:39 +00:00
Jacob Garber e447aec904 lib/edid.c: Add missing break statement
This was flagged as CID 1229647 (MISSING_BREAK). It was
originally fixed in e211bd9, but then reverted in 1c8ee21.
Hopefully fix it for good now.

Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Ib25b07b633ed02c466391050df15eaf9c36a3199
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-03-29 06:35:55 +00:00
Jacob Garber 1855329fba lib/edid.c: Log an error if unable to find edid or header
Failure to find an edid or header is more serious than the spew
log level and should be an error.

Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I660218f8b5f5e7f0b01daef0739db79418941515
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32084
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-29 06:35:23 +00:00
Subrata Banik 6a9d2f9899 soc/intel/icelake: Fix chipset_power_state structure
This patch ports CB:30717 changes from CNL to ICL.

This structure is declared as a static CAR_GLOBAL in the common
PMC library code and in the SOC specific code.  Remove the SOC
specific version and instead get the chipset_power_state pointer
from the PMC library.

This fixes events that were recorded in chipset_power_state at
boot but were reading as all zero when it was time to parse the
structure when logging events to flash.

Change-Id: I1152d0e882e1acf475072d1553b74f9161e2f485
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32095
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-29 02:33:14 +00:00
Duncan Laurie 0f57a2bb97 ec/google/wilco: Add ACPI _BIX method for battery
I added a method to fill out the _BIX package structure but never
hooked it up to the expected _BIX method that the OS uses.

This change adds _BIX method and uses the existing method to fill
it out.  It also adds ^ before the _UID in _BIF to match _BIX as
the _UID is one level above the method.

Change-Id: I0de91369b6780fd9432990732c1078a73f6a3419
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-03-28 19:18:05 +00:00
Duncan Laurie 242c9d9f24 mb/google/sarien: Call EC romstage init function
When in romstage call into the EC init function so it can send a
progress code to the EC before memory training starts.

BUG=b:127875364
TEST=boot with FSP debug and ensure EC does not try to turn off the
system while it is still booting.

Change-Id: I5d99fb16bae250a82b652c530c13977e74c3378b
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-03-28 19:17:53 +00:00
Duncan Laurie 31354676d0 ec/google/wilco: Add a romstage init function to send progress code
When using FSP with debug enabled it takes too long to get to ramstage
and send the first progress code to the EC.  The same thing has been
reported to happen when 2x16GB memory is installed.

BUG=b:127875364
TEST=boot with FSP debug and ensure EC does not try to turn off the
system while it is still booting.

Change-Id: I5676354f5e53540273a9029411507f91864735a1
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-03-28 19:17:43 +00:00
Subrata Banik 13f5360724 drivers/intel/wifi: Add support for Harrison Peak (HrP) 9560 module
Add HrP 9560 module device ID (0x06F0) into device/pci_ids.h file.

TEST=HrP module is getting detected during PCI enumeration on CMLRVP

Change-Id: I8f6d89b1c6d03e2497f6b345a520323f45247d7e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32096
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-28 18:50:06 +00:00
Nitheesh Sekar 69cc491c3f Mistral: Enable USB in romstage
Enable USB support for mistral in romstage.

TEST=build & run

Change-Id: I5c2bbe16aa3601e014a2b77d192565402ed23794
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-28 10:36:29 +00:00
Vijayavardhan Vennapusa dd3cffdb0c qcs405: Add support for USB host mode
Add required changes for USB host mode for
USB disk enumeration.

TEST=build & run

Change-Id: I35ec549b49b9789389c80843f6103e7243d52aac
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Signed-off-by: Vijayavardhan Vennapusa <vvreddy@partner-android.googlesource.com>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-28 10:36:22 +00:00
Joel Kitching 1d94849e74 chromeos: remove remaining dev switch references
As part of chromium:942901, physical dev switch functionality
is being deprecated.

Remove remaining references as well as helper macros.

BUG=chromium:942901
TEST=Build locally
TEST=make clean && make test-abuild
BRANCH=none

Change-Id: Ib4eec083eb76d41b47685701f9394c684ddc6b37
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-03-28 06:43:21 +00:00
Karthikeyan Ramasubramanian f84c103825 soc/intel/apollolake: Add support to log XHCI wake events
Add support to identify and log the XHCI wake events for apollolake into
event logs.

BUG=b:123429132
BRANCH=None
TEST=Ensure that the system boots to ChromeOS. Ensure that the wake up
events due to USB are logged into the event logs.
6 | 2019-03-21 09:22:18 | S0ix Enter
7 | 2019-03-21 09:22:22 | S0ix Exit
8 | 2019-03-21 09:22:22 | Wake Source | PME - XHCI (USB 2.0 port) | 9
9 | 2019-03-21 09:22:22 | Wake Source | GPE # | 13
10 | 2019-03-21 09:23:20 | ACPI Enter | S3
11 | 2019-03-21 09:23:30 | Wake Source | PME - XHCI (USB 2.0 port) | 9
12 | 2019-03-21 09:23:30 | ACPI Wake | S3
13 | 2019-03-21 09:23:30 | Wake Source | GPE # | 13

Change-Id: I55b850646dda8acaa086a9012c2d8b611016f932
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32000
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-28 06:40:03 +00:00
Karthikeyan Ramasubramanian cc7cdb19b1 soc/intel/common: Move support to log XHCI wake events
The policy to identify and log the XHCI wake events is similar between
skylake and apollolake. Hence move the similar parts to a common
location.

BUG=b:123429132
BRANCH=None
TEST=Ensure that the system boots to ChromeOS. Ensure that the wake up
events due to USB are logged into the event logs.
6 | 2019-03-21 09:22:18 | S0ix Enter
7 | 2019-03-21 09:22:22 | S0ix Exit
8 | 2019-03-21 09:22:22 | Wake Source | PME - XHCI (USB 2.0 port) | 9
9 | 2019-03-21 09:22:22 | Wake Source | GPE # | 13
10 | 2019-03-21 09:23:20 | ACPI Enter | S3
11 | 2019-03-21 09:23:30 | Wake Source | PME - XHCI (USB 2.0 port) | 9
12 | 2019-03-21 09:23:30 | ACPI Wake | S3
13 | 2019-03-21 09:23:30 | Wake Source | GPE # | 13

Change-Id: Ia6643342e3292984e422ff3c3fcd4bc0d99f947e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-28 06:39:38 +00:00
Sumeet Pawnikar e2ac5b7a36 mb/google/hatch/variants: Add DPTF based Fan control
This adds DPTF based Fan speed control for CML based Hatch system.

BUG=None
BRANCH=None
TEST=Built and tested fan speed with different temperatures

Change-Id: I3c2a679dc67eecb17098ce0f0c9703c679473a2d
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-28 06:38:51 +00:00
Xiang Wang 9d4a169532 payload: Only display `FIT support` on ARM64 platforms
Change-Id: Ided1cc22173342fa751b84db5f08a5cf7408941d
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-03-28 06:38:02 +00:00