Commit Graph

19188 Commits

Author SHA1 Message Date
Lijian Zhao 28821dbb22 soc/intel/apollolake: Add pmc_ipc device support
A dedicated pmc_ipc DSDT entry is required for pmc_ipc kernel driver.
The ACPI mode entry includes resources for PMC_IPC1, SRAM, ACPI IO and
Punit Mailbox.

BRANCH=None
BUG=chrome-os-partner:57364
TEST=Boot up into OS successfully and check with dmesg to see the
driver has been loaded successfully without errors.

Change-Id: I3f60999ab90962c4ea0a444812e4a7dcce1da5b6
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/16649
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-28 22:01:01 +02:00
Lijian Zhao 9108680c1c soc/intel/apollolake: Use fixed resource for SRAM and IPC1
Intel telemetry support will require PMC IPC1 and SRAM devices to be
operated in ACPI mode. Then using fixed resources on BAR0, BAR1
and BAR2 (PMC only) for those two devices will help
the resource assignment in DSDT stage.

BUG=chrome-os-partner:57364
BRANCH=None
TEST=Boot up into Chrome OS successfully and check with dmesg to see
the driver has been loaded successfully without errors.

Change-Id: I8f0983a90728b9148a124ae3443ec29cd7b344ce
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/16648
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-28 21:56:26 +02:00
Matt DeVillier f9c41974cd northbridge/sandybridge/raminit_mrc.c: fix missing include
Compilation (w/o native raminit) fails due to missing include

Change-Id: Ic79a77006257b32e0181c88c4e24d7c1f5c5f7ce
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/16735
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-27 20:31:55 +02:00
Elyes HAOUAS a6b863a2bc mainboard/msi/ms9185/resourcemap.c: Use tabs for indents
Change-Id: I30b5830442da65ae3ddd35e8bca67795c34e9020
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16737
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-27 20:31:18 +02:00
Elyes HAOUAS 99a92ac722 mainboard/msi/ms9185/romstage: Use tabs for indents
Change-Id: I101462105da31654032ac7e6abd3f9423ad7a7ef
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16736
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-27 20:30:46 +02:00
Duncan Laurie 02fdb3e014 x86: acpi: Use GOOG ID for coreboot table
Use the GOOG ACPI ID until there is an official ID allocation
for coreboot.  Since I administer this range I allocated
0xCB00-0xCBFF for coreboot use.

Change-Id: I38ac0a0267e21f7282c89ef19e8bb72339f13846
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16724
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-27 16:39:30 +02:00
Elyes HAOUAS bf97ca42cd mainboard/msi/ms9185/mb_sysconf.h: Use tabs for indents
Change-Id: Ib2ab95b26c3bb1cbd58aafb1fafd1b285d6a5ba8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16738
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-27 16:37:37 +02:00
Arthur Heymans 333176e5d3 i945/gma.c: Generate fake VBT
This generates a fake VBT for the Intel i945 graphic device. i945
supports both the mobile chipset 945gm (calistoga) and the desktop
chipset 945gc (lakeport), which is why a VBT with a different id string
needs to be created for each target.

The VBT id string is obtained from the vbios blob in the following way:
"strings vbios.bin | grep VBT".

Change-Id: I8245b12b16a4426efbe1f584d4163fc257231a98
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16530
Tested-by: build bot (Jenkins)
Reviewed-by: Damien Zammit <damien@zamaudio.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-27 15:46:11 +02:00
Arthur Heymans d3284a6977 nb/intel/*/gma.c: remove spaces at the fake vbt generation
Padding the VBT id string is now done automatically.

Change-Id: I8f9baf7b1585026bc29b82d07e451aa11e284ffb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16740
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-27 15:44:44 +02:00
Arthur Heymans 2e77e0aa3f intel/gma/vbt.c: pad the ID string with spaces.
The VBT id string is 20 characters long.
If the string is shorter than 20 it needs spaces at the end.
This change is cosmetic as all strings were padded by hand.

Change-Id: Id6439f1d3dbd09319ee99ce9d15dbc3bcead1f53
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16739
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-27 15:43:11 +02:00
Aaron Durbin 91fa9d7696 mainboards,ec: provide common declaration for mainboard_ec_init()
Add a header file to provide common declarations that the
mainboards can use regarding EC init.

BUG=chrome-os-partner:56677

Change-Id: Iaa0b37eff4de644e969a18364713b90b7f27fa1c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16734
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins)
2016-09-26 23:53:12 +02:00
Aaron Durbin 59cf5028a8 mainboards/google/reef: use chromeec's ASL lid switch implementation
Defer to the lid switch implementation provided by the chromeec.

BUG=chrome-os-partner:56677

Change-Id: Ida451dc29c8cf55fb88015e48a9e0bca3740f645
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16733
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-09-26 23:52:53 +02:00
Aaron Durbin 05201d7783 ec/google/chromeec: provide optional ASL lid switch implementation
Instead of relying on the mainboards to provide their own LID0
ACPI device, provide the infrastructure so that the mainboards
can signal to the EC ASL code to provide the default lid switch
implementation.

BUG=chrome-os-partner:56677

Change-Id: Ie43b1c4f8522db1245f1f479bfdb685d3066121d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16732
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-09-26 23:52:41 +02:00
Aaron Durbin c64a6d63ed soc/intel/apollolake: provide power button ACPI device
Instead of having each mainboard provide the power button,
uncondtionally provide the power button ACPI device on behalf
of each mainboard.

BUG=chrome-os-partner:56677

Change-Id: I94c9e0353c8d829136f0d52a356286c6bedcddd5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16731
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-26 23:52:32 +02:00
Patrick Georgi fe222005b8 crossgcc: Add Dockerfile
The dockerfile allows building an image with the current tree's
crossgcc code.

Change-Id: I59cd85b0acdf8776e3e090742d7f5d89d1c154e7
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: https://review.coreboot.org/16636
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-26 21:47:52 +02:00
Martin Roth 8918968557 payloads/external/Memtest86Plus: Update stable to latest commit
This brings in two additional changes:
- Use OBJCOPY if available.
- Fix strstr() indent and rewrite to not call strlen() on each char.

Change-Id: Id13dfda28c545332fce8282e849f379bf50629b9
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16605
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-26 21:45:32 +02:00
Elyes HAOUAS b87a734771 mainboard/*/*/dsdt.asl: Use tabs for indents
Change-Id: Idef587d8261784e916e8d50f4336cbcfca39b9b0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16730
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-26 13:38:46 +02:00
Elyes HAOUAS 8da96e57c8 mainboard/*/*/mptable.c: Improve code formatting
Change-Id: I341293cd334d6d465636db7e81400230d61bc693
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16723
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-26 13:32:21 +02:00
Elyes HAOUAS f4df9d1156 mainboard/*/*/irq_tables.c: Use tabs for indents
Change-Id: Idc29373cb01f4304d22ae315812bd40f0aaa94c9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16729
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-26 13:22:39 +02:00
Elyes HAOUAS 57a3cd21f1 mainboard/lippert: Use tabs for indents
Change-Id: If16d55e4ba0702176dc61524915d215ea46c14ba
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16686
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-26 13:22:23 +02:00
Andrey Petrov c2586db790 intel/amenia: Remove Amenia mainboard
The mainboard is not being worked on anymore, not available outside of
Intel and thus has litle practical use. Remove mainboard code completely.

Change-Id: Ic2c7ea3810ee70afc01a42786f8ccba9313134e4
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/16725
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-24 04:24:54 +02:00
Elyes HAOUAS d4c89e40c0 mainboard/lippert/frontrunner-af: Use tabs for indents
Change-Id: Id8b60d32d5bdaaa6c693dcf5db992ed975cc2400
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16685
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-23 20:46:04 +02:00
Elyes HAOUAS 62d4b0062b mainboard/lippert/toucan-af: Use tabs for indents
Change-Id: Ibd1fa89b450d52691dfef5616712f03fd675f123
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16684
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-23 20:45:51 +02:00
Elyes HAOUAS e4cf954f52 mainboard/nvidia/l1_2pvv: Use tabs for indents
Change-Id: I4171e9bbf14c9aa65f698feabd78aa8fbf2a105f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16687
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-23 20:45:47 +02:00
Duncan Laurie 1d359b5512 soc/intel/apollolake: Initialize processor count in GNVS
Initialize the PCNT variable in GNVS so it is available to ACPI code
that expects to know the number of CPUs.

Change-Id: I7a6e003ac94218061bf98e8883ed2c62d856af8d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16693
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-22 23:03:05 +02:00
Martin Roth 0f671f6ee9 Build system: Remove IASL_WARNINGS_ARE_ERRORS option
All systems are building with IASL warnings as errors enabled.
Remove the option to disable it.

Remove the notification at the end of the build.

Change-Id: I5c6218c182fdf173b4026fd010d939a5fa36040e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16606
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-22 22:33:55 +02:00
Nico Huber 66c2c1a2d4 buildgcc: Build gnat by default if host compiler seems compatible
Change-Id: I2a13e188ddb0b7d64d3c0ec979a1a493bf160afc
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/16678
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-21 22:10:30 +02:00
Nico Huber 04a1f6a3bc buildgcc: Ask the user to install gnat if it's missing
Change-Id: Ib840eac29fc8cedfaef4847fd9700bd4a70300ba
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/16677
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-21 22:08:32 +02:00
Nico Huber 75797166ce buildgcc: Don't try to build gnat with a different version
Change-Id: I64a33d2cc4793e54a50fa439a4461c40d424b569
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/16676
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2016-09-21 22:07:59 +02:00
Nico Huber 156d87c024 buildgcc: Warn when building GCC with a different major version
GCC build instruction recommend to bootstrap a native compiler first.
Not sure, when that is really necessary. A major version change seems
reasonable.

Change-Id: I80a9ec25739b7d33a1d1c7b4b2140d19d89a99ae
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/16675
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-21 17:03:23 +02:00
Nico Huber aee7f46cd3 buildgcc: Add functions to test GCC versions
Just add some helpers that show parts (major, major.minor) of the GCC
version to be built (buildcc_*) and of the host compiler (hostcc_*).
They will be used in follow-up commits.

Change-Id: I37c12ad1a2d08645f40a9f0f0a479c8d7cc3e127
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/16674
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2016-09-21 17:03:09 +02:00
Nico Huber bd74d561ad buildgcc: Show excessive arguments and bail out
Also remove a dead line that checks for unknown options: We already let
`getopt` check that.

Change-Id: I0e829b266e192757d6e455ee4cc608315bb4b7be
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/16681
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-21 17:02:20 +02:00
Nico Huber 78df0bf46d buildgcc: Check exit status of `getopt`
We accidentally checked the status of `eval` instead.

Change-Id: I1ba258944184ed707ed1f176e528d8266656cb59
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/16680
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-21 17:02:05 +02:00
Nico Huber cc414dd47f buildgcc: Fix GNU getopt usage
Looks like this never worked correctly: There are three argument formats
to GNU getopt and none of them matches what we fed it. The missing
double dash before the `set` arguments proves that we always called it
with parameters that `getopt` did NOT parse.

Change-Id: Ib8343976ef31774b18567a9fc9745a9f58dd287a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/16679
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2016-09-21 17:01:54 +02:00
Nico Huber 152e78e794 buildgcc: Fix option arguments
As we support `getopt` versions that don't know long options, every
option arguments needs a short option.

Also add the long options `--urls` and `--nocolor` to the `getopt`
string.

Change-Id: I11c393c3d90c7a16cdda119594221c85f902ed40
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/16682
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2016-09-21 17:01:16 +02:00
Elyes HAOUAS b6a6bb5393 northbridge/amdk8: Improve code formatting
Change-Id: I1c2786dfb166904ff8b19a663c5e2e8156b7aedf
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16644
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2016-09-21 16:49:34 +02:00
Elyes HAOUAS e1606731b6 northbridge/amd/amdmct: Improve code formatting
Change-Id: If87718b6c91d79212a9b045f5fda32d69ac4caee
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16643
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-21 16:49:15 +02:00
Patrick Georgi 8aa20193a6 google/enguarde: Adapt to current tree
Some changes were made in upstream in the meantime that broke the build:
- CHROMEOS_VBNV_CMOS was renamed to VBOOT_VBNV_CMOS
- recovery_move_enabled() -> vboot_recovery_mode_enabled()
- chromeos.asl was replaced by an acpi generator

Change-Id: Icd4ed5111cce9db79e12efb0cb7e898bba725c20
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/16683
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-21 16:48:36 +02:00
Iru Cai 904538bcc1 inteltool: add --ahci for printing AHCI registers
According to datasheets for Intel ICH/PCH, it works for chipsets from
ICH7 to 9-series PCH, with PCI device address D31:F2.

Change-Id: If1ddd7208108bda949b5a94894a7bf9e8bfe1e5f
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/15106
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-21 14:16:55 +02:00
Matt DeVillier 1ba3432301 google/enguarde: Upstream Lenovo N21 Chromebook
Migrate google/enguarde (Lenovo N21 Chromebook) from Chromium tree to
upstream, using google/rambi as a reference.

original source:
branch firmware-enguarde-5216.201.B
commit cf1f57b [Enguarde: Adjust rx delay for norm.]

TEST=built and booted Linux on enguarde with full functionality

blobs required for working image:
VGA BIOS (vgabios.bin)
firmware descriptor (ifd.bin)
Intel ME firmware (me.bin)
MRC (mrc.elf)
external reference code (refcode.elf)

Change-Id: I3ccda29d1e095d8b1b36766cda913172f72233a7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/15444
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-21 13:59:55 +02:00
Elyes HAOUAS 776498ac7e southbridge/sis/sis966/aza.c: Improve code formatting
Change-Id: If5342a2b5bae18b70ea671522efd2691bc9872dc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16602
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-21 11:22:54 +02:00
Elyes HAOUAS a813160fbc northbridge/amd: Improve code formatting
Change-Id: I80a2753f22d5211c8be4e17e2338402286a2cadc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16645
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-21 11:04:45 +02:00
Shaunak Saha 6fcfd919f1 soc/apollolake: Correct the comment section in gpio.asl
This patch corrects the comment section in gpio.asl for
GPE method.

Change-Id: I45771a295ee1eda00b9699f42cddd120223ff7bf
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/16647
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21 10:59:40 +02:00
Duncan Laurie 401bd31b2d mainboard/google/reef: Enable cr50 TPM interrupt
Enable the cr50 TPM and interrupt as GPE0_DW1_28 for use during
verstage.  The interrupt is left in APIC mode as the GPE is
still latched when the GPIO is pulled low.

BUG=chrome-os-partner:53336

Change-Id: Ib0247653bdcbaccb645cd16b81d7ec3c38f669af
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16673
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21 10:47:02 +02:00
Duncan Laurie 94cc485338 drivers/i2c/tpm/cr50: Support interrupts for status
Support reading the ACPI GPE status (on x86) to determine when
the cr50 is ready to return response data or is done processing
written data.  If the interrupt is not defined by Kconfig then
it will continue to use the safe delay.

This was tested with reef hardware and a modified cr50 image
that generates interrupts at the intended points.

BUG=chrome-os-partner:53336

Change-Id: Ic8f805159650c45382cacac8840450a1f8b4d7a1
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16672
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21 10:46:51 +02:00
Duncan Laurie 2e79009503 soc/intel/apollolake: Add function to read and clear GPE status
Implement the generic acpi_get_gpe() function to read and clear
the GPE status for a specific GPE.

Tested by watching GPE status in a loop while generating interrupts
manually from the EC console.

BUG=chrome-os-partner:53336

Change-Id: I482ff52051a48441333b573f1cd0fa7f7579a6ab
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16671
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21 10:46:35 +02:00
Duncan Laurie a673d1cd2d soc/intel/apollolake: Initialize GPEs in bootblock
Initialize the GPEs from mainboard config in bootblock, so they
can be used in verstage to query latched interrupt status.

I still left it called in ramstage just to be sure that the
configuration was not overwritten in FSP stages.

Tested by reading and reporting GPE status in a loop in verstage
and manually triggering an interrupt on EC console.

BUG=chrome-os-partner:53336

Change-Id: Iacd0483e4b3229aca602bb5bb40586eedf35a6ea
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16670
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21 10:46:14 +02:00
Duncan Laurie 1f6e681355 x86: acpi: Add function for querying GPE status
Add a function that can be implemented by the SOC to read
and clear the status of a single GPE.  This can be used
during firmware to poll for interrupt status.

BUG=chrome-os-partner:53336

Change-Id: I551276f36ff0d2eb5b5ea13f019cdf4a3c749a09
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16669
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21 10:46:00 +02:00
Duncan Laurie f235a9b1b0 drivers/i2c/tpm/cr50: Improve data handling and function names
Unify the function names to be consistent throughout the driver
and improve the handling while waiting for data available and
data expected flags from the TPM.

BUG=chrome-os-partner:53336

Change-Id: Ie2dfb7ede1bcda0e77070df945c47c1428115907
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16668
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21 10:45:24 +02:00
Duncan Laurie d3920e71d6 drivers/i2c/tpm/cr50: Clean up locality functions
Clean up the mask and timeout handling in the locality functions
that were copied from the original driver.

BUG=chrome-os-partner:53336

Change-Id: Ifdcb3be0036b2c02bfbd1bcd326e9519d3726ee0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16667
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21 10:45:09 +02:00