GNUBoot/coreboot-kgpe-d16
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Author SHA1 Message Date
Marshall Buschman
eab1db192f ASRock/E350M1: Skip memory clear for boot time reduction 
Applying Scott's patches to e350m1, svn r6600:
Memory clear is not required for non-ECC boards.

Change-Id: Ia1a7c926611de72351434cbdc1795ed10bc56ed1
Signed-off-by: Scott Duplichan <scott@notabs.org>
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Reviewed-on: http://review.coreboot.org/20
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
 2011-06-12 19:27:34 +02:00
Sven Schnelle
0f9cd43514 X60/T60: fix return value of mainboard_io_trap_handler() 
The handler should return 1 if it handled the request. The current
code returns 0, which causes 'Unknown function' logs.

Change-Id: Ic296819a5f8c6f1f97b7d47148182226684882a0
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/29
Tested-by: build bot (Jenkins)
 2011-06-12 17:28:10 +02:00
Sven Schnelle
1b8068e244 H8 EC: add volume CMOS setting 
Change-Id: I5332c8fa52556db34dfb5e772bf544f0323e823d
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/12
Tested-by: build bot (Jenkins)
 2011-06-09 10:05:46 +02:00
Sven Schnelle
51e1bc3a7b T60/PMH7: move 'touchpad' option to pmh7 
This option is PMH7 specific, and should be moved there,
so all Notebook utilizing a PMH7 have this option.
For Thinkpads without Touchpad (like the X60), simply
don't add 'touchpad' to cmos.layout.

Change-Id: Icdd0093670d565f1b16e2483aa286f4d63ccc52a
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/6
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
 2011-06-07 22:43:14 +02:00
Sven Schnelle
f4dc1a73e4 SMM: add defines for APM_CNT register 
in the current code, the defines for the APM_CNT (0xb2) register
are duplicated in almost every place where it is used. define those
values in cpu/x86/smm.h, and only include this file.

And while at it, fixup whitespace.

Change-Id: Iae712aff53322acd51e89986c2abf4c794e25484
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/4
Tested-by: build bot (Jenkins)
 2011-06-07 22:01:29 +02:00
Sven Schnelle
b924eb45f1 T60: fix touchpad option 
Code used 'int' as return type, but the cmos option is only one
bit. get_option returned with the value in bit 0-7, but all remaining
bits were left unitialized by get_option(). fix this by using char
as type.

Change-Id: I60e609164277380f936f66c99ef9508fa6a6b67c
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/5
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
 2011-06-07 12:50:42 +02:00
Stefan Reinauer
44c1d3111b re-indent, so files conform to coding guidelines. 
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Change-Id: If840164fa0e2b6349ba920edf06386ba1fe08aab
Reviewed-on: http://review.coreboot.org/8
Tested-by: build bot (Jenkins)
Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
 2011-06-07 11:58:31 +02:00
Stefan Reinauer
fb38eb01ca WARNINGS_ARE_ERRORS is y per default, don't set it twice. 
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6637 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-06-04 16:30:27 +00:00
Peter Stuge
d1760c834a Port persimmon r6594 to e350m1: Cosmetic cleanup 
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6636 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-06-04 15:48:14 +00:00
Peter Stuge
f8e33e356f Port persimmon r6593 to e350m1: Remove unused Kconfig options 
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6635 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-06-04 15:47:56 +00:00
Peter Stuge
2334c8d2b7 Port persimmon r6592 to e350m1: Update GPP port configuration 
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6634 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-06-04 15:47:30 +00:00
Marshall Buschman
314f4a2077 Port persimmon r6591 to e350m1: ROM cache early 
Enable rom cache early to reduce boot time.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6633 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-06-04 15:47:05 +00:00
Marshall Buschman
1a7699f42a Port persimmon r6590 to e350m1: Work around memory allocation problem 
Fix memory allocation problem in amdInitLate. Disabled until further debug.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6632 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-06-04 15:46:50 +00:00
Marshall Buschman
bb2ca2bafd Port persimmon r6589 to e350m1: Strip down AGESA options 
Remove some non-essential agesa options to reduce boot time.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6631 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-06-04 15:46:32 +00:00
Marshall Buschman
af85315707 Port persimmon r6588 to e350m1: VGA framebuffer 
Declare legacy video frame buffer so that Windows generic VGA driver will work.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6630 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-06-04 15:46:13 +00:00
Marshall Buschman
adc89b033e Port persimmon r6587 to e350m1: RTC is not PIIX4 compatible 
Declare RTC as not PIIX4 compatible to match AMD hardware.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6629 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-06-04 15:45:46 +00:00
Marshall Buschman
ac4bef4907 Port persimmon r6586 to e350m1: FADT revision 
Make fadt revision match its length. Solves Windows 7 checked build assert.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6628 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-06-04 15:45:29 +00:00
Marshall Buschman
552ad9f75e Port persimmon r6584 and r6601 to e350m1: SPI prefetch early 
Enable SPI cacheline prefetch early to reduce boot time.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6627 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-06-04 15:45:12 +00:00
Marshall Buschman
fd460e620e Port persimmon r6583 to e350m1: pstate 0 early 
Switch processor cores to pstate 0 early to reduce boot time.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6626 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-06-04 15:44:54 +00:00
Marshall Buschman
b3ee0d6bd6 Port persimmon r6582 to e350m1: 33 MHz SPI read early 
Enable 33 MHz fast mode SPI read early to reduce boot time.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6625 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-06-04 15:44:31 +00:00
Peter Stuge
69e1bfcf34 Port persimmon r6578 and r6596 to e350m1: MMCONF base 
Remove multiple mmconf settings and just use kconfig setting.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-06-04 15:44:14 +00:00
Marshall Buschman
eb92b5ad64 Port persimmon r6574 to e350m1: MMCONF size 
Size mmconf according to CONFIG_MMCONF_BUS_NUMBER.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6623 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-06-04 15:43:56 +00:00
Marshall Buschman
5a403191cb Port persimmon r6573 to e350m1: VGA, PCI MMIO and SB800 legacy 
1) Use D18F1xF4 VGA Enable to simplify legacy video I/O support.
2) Extend PCI MMIO limit from dfffffff to fecfffff.
3) Add AMD recommended non-posted mapping for SB800 legacy devices.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6622 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-06-04 15:43:38 +00:00
Marshall Buschman
6d5ee2d80a Port persimmon r6572 to e350m1: I/O APIC ID 
1) Set I/O APIC ID according to BKDG recommendation
2) Correct I/O APIC ID reported by mptable

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6621 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-06-04 15:43:15 +00:00
Kerry She
3bf2708664 advansus/a785e-i mainboard enable warning as error 
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Kerry She <kerry.she@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6617 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-06-03 10:14:56 +00:00
Stefan Reinauer
9cb175632d AP_IN_SIPI_WAIT is already defined in the CPU Kconfig of those boards. 
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6611 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-23 22:43:43 +00:00
Scott Duplichan
fb93178f13 Correct amd persimmon romstage code for early SPI prefetch enable. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Scott Duplichan <scott@notabs.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6601 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-20 17:50:14 +00:00
Scott Duplichan
20aad25e6e Move the ACPI FACP table to the front of the RSDT list. This is done to work around a Windows XP or Server 2003 setup failure where an error message such as: "An unexpected error (805262864) occurred at line 1768 of d:\xpclient\base\boot\setup\arcdisp.c" occurs. This change updates AMD reference board projects, but could applied to others as well. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6600 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-20 00:06:09 +00:00
Marc Jones
44d3c3dade Remove multiple mmconf settings and just use kconfig setting. 
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6596 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 23:13:54 +00:00
Scott Duplichan
8c46263721 Cosmetic cleanup. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6594 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 22:10:15 +00:00
Scott Duplichan
5d878ad312 1) Remove unused kconfig options. 
2) Correct UMA graphics PCI device ID.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6593 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 22:09:09 +00:00
Scott Duplichan
a64ab46b62 Update gpp port configuration. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6592 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 22:07:56 +00:00
Scott Duplichan
769527e523 Enable rom cache early to reduce boot time. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6591 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 22:06:09 +00:00
Scott Duplichan
3c639e7df8 Fix memory allocation problem in amdInitLate. Disabled until further debug. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6590 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 22:05:00 +00:00
Scott Duplichan
0b886ae3c3 Remove some non-essential agesa options to reduce boot time. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6589 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 22:03:45 +00:00
Scott Duplichan
dbbbca3f33 Declare legacy video frame buffer so that Windows generic VGA driver will work. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 22:02:27 +00:00
Scott Duplichan
0ebefd27c8 Declare RTC as not PIIX4 compatible to match AMD hardware. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6587 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 22:00:23 +00:00
Scott Duplichan
254a6d6ea7 Make fadt revision match its length. Solves Windows 7 checked build assert. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6586 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:59:19 +00:00
Scott Duplichan
b7e068305c Enable SPI cacheline prefetch early to reduce boot time. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6585 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:56:03 +00:00
Scott Duplichan
2cc5f550c7 Enable SPI cacheline prefetch early to reduce boot time. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6584 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:54:04 +00:00
Scott Duplichan
d9a634c756 Switch processor cores to pstate 0 early to reduce boot time. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6583 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:51:31 +00:00
Scott Duplichan
e73fc20886 Enable 33 MHz fast mode SPI read early to reduce boot time. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6582 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:48:22 +00:00
Scott Duplichan
dc312cca53 Move mmconf base from e0000000 to f8000000 to avoid conflict with UMA BAR. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6578 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:26:04 +00:00
Scott Duplichan
444c49c68c Match DIMM SPD addressing to implemented slots. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6575 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:13:00 +00:00
Scott Duplichan
6719c23a47 Size mmconf according to CONFIG_MMCONF_BUS_NUMBER. 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6574 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:11:41 +00:00
Scott Duplichan
b0b4063d6a 1) Use D18F1xF4 VGA Enable to simplify legacy video I/O support. 
2) Extend PCI MMIO limit from dfffffff to fecfffff.
3) Add AMD recommended non-posted mapping for SB800 legacy devices.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6573 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:10:20 +00:00
Scott Duplichan
6f7375c24c 1) Set I/O APIC ID according to BKDG recommendation 
2) Correct I/O APIC ID reported by mptable

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6572 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-15 21:07:43 +00:00
Josef Kellermann
eb97e9688f siemens/sitemp_g1p1: Adapt read_option() to latest changes 
Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6569 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-13 06:25:16 +00:00
Patrick Georgi
ceccd8dd67 Remove uart_init() in Siemens sitemp-g1p1 
uart_init() was moved to common code in r6531, but I
missed that when integrating the new mainboard code.

Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6568 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-12 06:53:52 +00:00
Josef Kellermann
bfa7ee5b04 Add Siemens SITEMP-G1 board 
The code is loosely based on AMD dbm690t (and copied from there)
and adapted to match the Siemens SITEMP-G1 board.
It boots both Linux and Windows XP (and if it doesn't then complain
with me [Patrick] because in that case I must have messed it up when
integrating the patch)

Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6567 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2011-05-11 07:47:43 +00:00