Commit Graph

25465 Commits

Author SHA1 Message Date
John Su 50a7fca1d7 mb/google/poppy/variants/nami: Fix non-working thermal sensor QT2 PSV
Modify DPTF TRT parameters to solve thermal sensor QT2 PSV problem.

BUG=b:109941652
TEST=The thermal team verify OK

Change-Id: Id9d39d8282712a0341fea10f74c0e40bb1ac9d7c
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-22 16:51:49 +00:00
Furquan Shaikh d9bbbe3ca4 mb/google/octopus: Update GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
Move GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC under each variant config and
select it for bip and fleex only.

Functional change in this CL is that EC SW sync will be enabled for
phaser.

BUG=b:110523400

Change-Id: If6f37c6b2ee71130b9ed5b10ce92fb23fa1c39fc
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-22 16:24:54 +00:00
T Michael Turney ace395b96a sdm845: increase SRAM for bootblock
Bootblock has grown beyond 32K, grow to 40K

Change-Id: Iedc52151e223ebf4ff5b35a419b5378a6f1c661b
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/26760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-06-22 13:11:39 +00:00
T Michael Turney be073dacb0 libpayload: cheza - fix config for chromium chroot build
Add CONFIG_LP_CHROMEOS to configuration file

Change-Id: I528dee96cf5052b99b8f7573010d98fd80680688
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/26711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-22 13:11:06 +00:00
Matt DeVillier 1f6e3294f8 drivers/fsp1_1: fix VBT Loading by using GMA common function
Commit 77034fa [intel/common: compress VBT] compressed vbt.bin in
CBFS, but only changed the loader in soc/intel/common, forgetting
the separate one used by FSP 1.1.

As the soc/intel/common loader has now been rolled into the one in
drivers/intel/gma, replace the VBT loader used by FSP 1.1 with the GMA one.
Also, remove 2 now-unused header files.

Test: build/boot google/chell, observe display initialized prior
to OS load, no FSP warning in cbmem console due to invalid VBT signature.

Change-Id: Iba882ee4d9e83dcd88bdf7dd2f5591f66005a3fe
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-22 09:28:44 +00:00
Enrico Granata 95278a59bd mb/google/poppy/variants/nocturne: Hook up the SX9310 proximity sensor.
Change-Id: I7358ee34df873098a86d692cc8a909b0ec5023a8
Signed-off-by: Enrico Granata <egranata@chromium.org>
Reviewed-on: https://review.coreboot.org/27172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-22 09:21:19 +00:00
Enrico Granata 76a1f49f74 drivers/i2c: Add a driver for Semtech SX9310
This adds a new driver for the SX9310 proximity detector device.

The purpose of this is to enable the device's calibration information
to be stored in firmware, and then transferred over to the kernel
via ACPI.

This device has more than 10 individual configuration parameters,
so they would not fit in the generic driver's properties table.

Change-Id: Id8c434eec9fe2da731e142442503a12e88db2236
Signed-off-by: Enrico Granata <egranata@chromium.org>
Reviewed-on: https://review.coreboot.org/27173
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-22 09:21:02 +00:00
Arthur Heymans 9700e91b10 cbfstool/fit.c: Fix for older CPUs without total_size in mcu_header
Some older CPUs have a fixed size of 2048 bytes for microcode total size.

Change-Id: Ia50c087af41b0df14b607ce3c3b4eabc602e8738
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27090
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-22 09:20:22 +00:00
Subrata Banik d5018a8f78 soc/intel/cannonlake: Remove DMA support for PTT
Alternative buffer communication support for PTT is no longer
needed for CNL onwards and coreboot does not need to reserve additional
4KiB memory for PTT support.

Change-Id: I11993cef77fd5e879eedabc1ed344f91f8257c90
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/27176
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-22 01:58:33 +00:00
Subrata Banik f699c14c03 soc/intel/common/block/cpu: Add option to skip coreboot AP init
SoC users from IOTG team is looking forward for a solution to skip
coreboot AP initialization flow and make use of FSPS-UPD to
perform AP reset.

TEST=Assign use_fsp_mp_init=1 to ensure coreboot is not bringing APs
out of reset.

Change-Id: Ibc8cd411e802fb682436a933073922b2693ba994
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-22 01:58:17 +00:00
qeed b775a62bb9 inteltool: Add PCI IDs for the C220 PCH series
Adds missing PCI IDs to allow tool to dump the
C220 PCH (8 series) southbridge.

Intel Document 328904 is the datasheet for this PCH.

Change-Id: I07a8f2e9cb0ee8677c8fe2c51881147ed81c1a35
Signed-off-by: Quan Tran <qeed.quan@gmail.com>
Reviewed-on: https://review.coreboot.org/27168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-21 17:39:48 +00:00
Patrick Rudolph e66b10f3e1 tianocore: Fix RPM package name
The packge uuid-devel doesn't provide the required files,
but libuuid-devel does.

Change-Id: I61d537e4f1fca0d7172c129a75e13aa58452763f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/27136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-21 17:28:55 +00:00
Bora Guvendik 7fe9e8edea soc/intel/apollolake: unify definition for spi base address
Use SPI_BASE_ADDRESS instead of PRERAM_SPI_BASE_ADDRESS like
big core in order make common code implementation straightforward.

Change-Id: Ibcb013fc95de29234253e89c9ca100cc468d44f6
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/27097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-21 15:55:05 +00:00
Subrata Banik 90d3b2b0c0 soc/intel/common: Make infrastructure ready for Intel common stage files
Select all Kconfig belongs into Intel SoC Family basecode/stage files
and include required headers from include/intelbasecode/ files.

BUG=None
BRANCH=none
TEST=Code is compiling with cannonlake configurations and also booting
on cannonlake RVP.

Change-Id: Iac99b4346e8bf6e260b00be9fefede5ad7b3e778
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-21 15:54:48 +00:00
Arthur Heymans 2e464cf3b0 sb/intel/i82801xx: Use common RCBA MACROs
Change-Id: I61fb3b01ff15ba2da2ee938addfa630c282c9870
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-21 15:51:48 +00:00
Arthur Heymans 8d0e88db34 sb/intel/common/rcba_pirq.c: Use common RCBA acces MACROs
Change-Id: I2fe8d8388cb96e42af4f9be251a41cceeb2e4710
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27042
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21 15:51:38 +00:00
Arthur Heymans 1f2ae91074 sb/intel/common: Make RCBA manipulation MACROs common
No Change in BUILD_TIMELESS.

Change-Id: I634526269d45ebdc6c31cdc28d9ec846b397211d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-21 15:51:12 +00:00
Arthur Heymans 58a8953793 Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location"
In the end it does not look like RCBA register offsets are fully
compatible over southbridges.

This reverts commit d2d2aef6a3.

Is squashed with revert of "sb/intel/common: Fix conflicting OIC
register definition" 8aaa00401b.

Change-Id: Icbf4db8590e60573c8c11385835e0231cf8d63e6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-21 15:50:16 +00:00
Arthur Heymans 4dfb5f1055 util/abuild: Fix building when not in coreboot root dir
Change-Id: Ibe54096f275a05bda745ae2cc76c0109281c0c4b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-21 15:47:44 +00:00
Richard Spiegel 35282a0f1b soc/amd/stoneyridge/southbridge.c: Store PM related registers in cbmem
PM registers used for generating SWS values are being stored in a static
variable within southbridge.c. In order to have it available for any source
involved in building the platform, move the storage to cbmem, using id
CBMEM_ID_POWER_STATE. Also add a variable that informs from which state
the system is waking from, extracted from register ACPI_PM1_CNT_BLK. This
variable will later be useful in detecting failed S3 resume.

BUG=b:80119811
TEST=Add code to print SWS parameters and state it's waking from. Build
and boot grunt, suspend and resume, check output for valid values. Remove
the print code.

Change-Id: Ib27a743b7e7f8c94918caf7ba5efd473f4054986
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27109
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21 15:47:31 +00:00
Arthur Heymans cd7dfaf3b0 drivers/ati/ragexl: Remove dead code
Is unused in the tree.

Change-Id: I8a5308b6c7773d791d47832e620558394f1d727e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22132
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21 15:46:37 +00:00
ren kuo 26a4b9d063 google/lars,lili: Add SPD mapping for Hynix 8GB config
Upstreaming Chromium commit 0bc6c43:
Lili: Update Memory IDs

TEST=Build and boot up on lili board

Original-Change-Id: I6da1e97820b1bf2e751102384eed07236143fe2b
Original-Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/956782
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>

Change-Id: Icf6588582da3b4a7861bced539d51a914b011dc4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27135
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21 15:46:09 +00:00
Nico Huber bb10ec3d41 payloads/external/GRUB2: Use pkg-config over freetype-config
`freetype-config` is gone and was obsolete for a long time.

Change-Id: Id3058e55b1630f43225d3cd1ad91801c4085874f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/26822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-21 14:57:13 +00:00
Nico Rikken 28cdd4c8d3 mb/lenovo/t520: Add Dual Graphics CMOS support
Adds the CMOS option for Dual Graphics, as is present in more Lenovo models
already. Enabling this option ensures that the NVIDIA GPU is powered.

More PCI devices can be observed when activating this setting. It was verified
on a W520, also by loading a VGA option ROM and achieving a working Dual
Graphics system.

The CMOS default has been kept to 'Integrated Only', as the usage of Dual
Graphics requires an option ROM and drains the battery more quickly.

Change-Id: I41ccabd4554ca019684edd6f8b1c23679212c59f
Signed-off-by: Nico Rikken <nico@nicorikken.eu>
Reviewed-on: https://review.coreboot.org/26114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-06-21 09:45:34 +00:00
Nick Vaccaro 91b76f19f4 mb/google/poppy/variants/nocturne: add two new memory options
- add K4E6E304EC-EGCF and K4EBE304EC-EGCF to memory strapping table
- add SPD files for K4E6E304EC-EGCF and K4EBE304EC-EGCF

BUG=b:110277021
BRANCH=none
TEST=none

Change-Id: If1322311bd91842d6d32725822d91fd6d9e8077c
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-21 09:44:28 +00:00
Sathyanarayana Nujella 881ff66183 mb/google/poppy/variants/nocturne: Update Slave Addresses of Max98373 Amp's
When played Left Only Audio and Right Only Audio, we observed that Audio
got swapped. Left Data played on Right Speaker and Viceversa.

This patch fixes the above issue.

BUG=b:73635449
TEST=Play Left only & Right only Audio and cross check Audio.

Change-Id: Ie9c417ad0634a76fc8a4126ee75886603f1b3da0
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/27167
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21 09:43:37 +00:00
Cole Nelson 63b6fea5c9 soc/intel/{skl,kbl}: ensure C1E is disabled after S3 resume
C1E is disabled by the kernel driver intel_idle at boot.  This does not
address the S3 resume case, so we lose state and C1E is enabled after S3
resume.

Disable C1E for SKL and KBL.  This gives a coherent state before
and after S3 resume.

TEST='iotools rdmsr cpu 0x1fc'. Returns the same value after boot and S3
resume with bit [1] set to zero (0x20005d).

Change-Id: I1343f343bfac9b787f13c15b812c0a201dcccb38
Signed-off-by: Cole Nelson <colex.nelson@intel.com>
Reviewed-on: https://review.coreboot.org/27125
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21 09:43:19 +00:00
Kyösti Mälkki 4cdd2f8ce1 soc/amd/common: Always set GetBiosCallout
The entire StdHeader field is really supposed to
be forked from a template for each entry into the
AGESA API. Current code assumes only Callout would
be relevant, which is not quite the case.

Change-Id: I0cc66d01d62fa8dc6bb7c9f9fab6fa4753827554
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/27111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-06-21 09:42:27 +00:00
Nick Vaccaro de31587a3a mb/google/poppy/variants/nocturne: disable p-states
Set register speed_shift_enable=0 in devicetree to disable
p-states in coreboot as a temporary workaround for an SoC hang.

BUG=b:79666828
BRANCH=none
TEST="emerge-nocturne depthcharge coreboot chromeos-bootimage",
flash spi image onto nocturne, boot to kernel and verify device
stays alive and responsive for several minutes without locking up.

Change-Id: I71ed4c80c109b28ffa85d48338ce3a62396d272e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-21 09:41:29 +00:00
Tristan Shieh 97bdb9aa31 mediatek/mt8183: Remove DRAM_DMA section
DRAM_DMA section is used for the special SPI NOR controller on legacy
SOC. Remove it since no driver need it currently and we don't have the
special SPI NOR controller on mt8183.

BUG=b:80501386
BRANCH=none
TEST=Boots fine on Kukui

Change-Id: I6ba0757adbf4f1f8d2688e5ab1a36007e4e0d0fd
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-06-21 09:40:51 +00:00
Tristan Shieh 4c6dfbc2c1 mediatek/mt8183: Add watchdog timer support
Using common watchdog timer (WDT) code for reset. Set up watchdog timer
in mtk_wdt_init() to get reset status and disable auto-reboot. Link
common do_hard_reset() to support hard reset.

BUG=b:80501386
BRANCH=none
TEST=both mtk_wdt_init() and do_hard_reset() work on Kukui.

Change-Id: I4be3a133dbb8a64604133cefb0c5f02d01afd0d4
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27026
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21 09:40:06 +00:00
Tristan Shieh 53dabc29f2 mediatek: Move watchdog timer code to a common directory
Move watchdog timer (WDT) code which can be reused into a common
directory under soc/mediatek.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Elm

Change-Id: Icbeb04f775c3c0fdc18dd198df8591f5c4b6ddce
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27025
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21 09:39:48 +00:00
Tristan Shieh e96a6d26a6 mediatek: Share watchdog timer code among similar SOCs
Refactor watchdog timer (WDT) code which will be reused among similar
SOCs.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Elm

Change-Id: I745c2f204924d9eee1941c0f3e9b6ba45cfb1958
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27024
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21 09:39:40 +00:00
Caveh Jalali 1fdb76945a mb/google/poppy/variants/atlas: enable camera power and release reset
This is a temporary hack to test camera presence before we have full
camera support implemented.  Basically, we can now probe the camera
over i2c to verify that it's connected and the camera LED turns on.

BUG=b:80106316
BRANCH=none
TEST=camera LED comes on and camera can be probed over i2c.

Change-Id: Ibaabf6c6f6a1dabaddd2fc47c820e090ca5984a5
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/27128
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21 04:38:58 +00:00
Caveh Jalali 126ce5c28b mb/google/poppy/variants/atlas: enable touchscreen
This adds the necessary config to enable touchscreen sensor in linux.

BUG=b:110286344,b:110286345
BRANCH=none
TEST=verified touch functionality using eval board

Change-Id: I21efafda3f2ae1dcea19e44f8d66f6dfaac1bb12
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/27127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-21 04:38:46 +00:00
Caveh Jalali e750198528 mb/google/poppy/variants/atlas: support i2c-hid trackpad
We plan to use i2c-hid compatible trackpads on atlas, so this switches
the trackpad config to i2c-hid.

BUG=b:80662079
BRANCH=none
TEST=used trackpad to verify motion tracking

Change-Id: I2702e61a6aa96250c0c09ea4bd15d0c671eedadc
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/27126
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21 04:38:17 +00:00
Seunghwan Kim 5bf6347cf8 mb/google/poppy/variants/nautilus: Add SAR sensor device into devicetree.cb
This change defines SAR sensor device into devicetree.cb.
Since only LTE sku has SAR sensor, we will use GPP_B20 as a device_present_gpio.

BUG=None
BRANCH=poppy
TEST=Verified SAR sensor device is loaded by driver in Chrome OS

Change-Id: Ib4969e4b82d18b1b1a599de8226c2d7d4bda7915
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27149
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21 01:47:41 +00:00
Seunghwan Kim d4475fc6f9 mb/google/poppy/variants/nautilus: Clear GPP_D0 when entering S5
Nautilus 2nd SKU has a leakage voltage at GPP_D0 in S5 state. We need to set this to LOW when entering S5 for clear the leakage.

BUG=None
BRANCH=poppy
TEST=Verified the leakage is gone after update coreboot

Change-Id: I054e707b2bc2e63d6f99cd2fd8a57be20615f111
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-21 01:47:32 +00:00
Seunghwan Kim e5a9e60fc5 mb/google/poppy/variants/nautilus: Configure for 2nd nautilus SKU
For supporting new SKU, we need to override GPIO table and device configuration.
The board ID of 2nd SKU of nautilus is started from 9, so we would determine SKU with it.

BUG=b:80052672
BRANCH=poppy
TEST=emerge-nautilus coreboot

Change-Id: I7242f23f47010664cc29ea86a126e63c9dd62ccd
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27147
Reviewed-by: Enrico Granata <egranata@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21 01:25:58 +00:00
David Hendricks 7000f5a0c1 fsp_broadwell_de: Add uncore ASL in common location
This patch adds a file for uncore ASL code that is common among
Broadwell-DE mainboards but is currently copy + pasted in each of
their dsdt.asl files.

This is only for clean-up purposes. It is unclear if the code itself is
really necessary, but until we can do further investigation and testing
it will be left in.

Change-Id: I188e5e46dfa7c2ed3991fb97f2c1b5e062e2212d
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/27155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-20 19:37:21 +00:00
Kyösti Mälkki 371e7d95aa nb/intel/e7505: Leave ROM as un-cacheable in postcar
Collected timestamps indicate LZMA decompression of ramstage
is 4x slower when ROM is marked WP-cacheable, in contrast to
having ROM as US. A simple copy WP->WB with uncompressed
ramstage also appeared to be twice as slow as UC->WB copy.

It should be noted that if POSTCAR_STAGE was removed from build,
un-lzma takes 130 seconds instead of 45 milliseconds.

Change-Id: I2cf995395ef2d303ad0bc044dbfa160990a705d0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/27164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-20 19:00:07 +00:00
Kyösti Mälkki 4d991550b3 aopen/dxplplusu: Add romstage timestamps
Change-Id: Ic6e2a350a976a3fcb421d47a0bf5600df994edc2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/27163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-20 18:59:19 +00:00
Furquan Shaikh faad9684a9 mb/google/octopus: Configure EC_IN_RW correctly
This change fixes the following issues with EC_IN_RW signal:
1. EC_IN_RW is an input signal to the SoC. Configure it accordingly in
GPIO table for baseboard and bip.
2. GPIO_EC_IN_RW is passed in coreboot tables so that payload can
re-sample the GPIO at runtime.

BUG=b:110084012
TEST=Verified that EC_IN_RW signal is read correctly in depthcharge.

Change-Id: I1c5f5b4b914ced98e89a571dc398df5ba1fe8460
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-06-20 18:28:46 +00:00
wuxy d4d1ef8189 mb/google/octopus: Enable Synaptics touchpad device
This change adds Synaptics device to phaser project.

BUG=b:110236590
TEST=emerge-octopus coreboot chromeos-bootimage
     reflash the coreboot to DUT,make sure the Synaptics Touchpad can work.

Change-Id: Icc1e8c35a9de54ed04187fcf219a72a592d3bd81
Signed-off-by: Xingyu <wuxy@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27159
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-20 05:26:28 +00:00
Philipp Deppenwiese 0f0e4e6c66 payloads: Add LinuxBoot payload in u-root mode
* Add LinuxBoot support
* Add u-root mode
* Download kernel and u-root from upstream sources.
* Add customization options
* Clean kernel only if directory exists

Change-Id: I3a25ff6812e046acc688cbbb203cf262ad751659
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/23071
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-19 18:37:37 +00:00
Patrick Rudolph a892cde653 lib: Add FIT payload support
* Add support for parsing and booting FIT payloads.
* Build fit loader code from depthcharge.
* Fix coding style.
* Add Kconfig option to add compiletime support for FIT.
* Add support for initrd.
* Add default compat strings
* Apply optional devicetree fixups using dt_apply_fixups

Starting at this point the CBFS payload/ can be either SELF or FIT.

Tested on Cavium SoC: Parses and loads a Linux kernel 4.16.3.
Tested on Cavium SoC: Parses and loads a Linux kernel 4.15.0.
Tested on Cavium SoC: Parses and loads a Linux kernel 4.1.52.

Change-Id: I0f27b92a5e074966f893399eb401eb97d784850d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-06-19 18:10:05 +00:00
Patrick Rudolph 8c986ab263 Documentation: Add cavium SoC and mainboard
* Add documentation for CN81XX SoC
* Add documentation for CN81XX EVB SFF mainboard
* Add documentation for BDK
* Add documentation for BOOTROM and BOOTBLOCK behaviour
* Alphabetically sort vendors

Change-Id: Ibfcd42788e31f684baed658dc3c4dfe1b8e4f354
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-06-19 18:09:04 +00:00
Patrick Rudolph a45e9f8106 lib: Raw import FIT parser
Import from https://chromium.googlesource.com/chromiumos/platform/depthcharge

Coding style and coreboot integration will be done in a separate commit.

Change-Id: Iee56db328d7eeffb0eaf829841243b0b9195c199
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-06-19 14:28:31 +00:00
Patrick Rudolph 59b8f275c2 lib/prog_loaders: Move argument selection into selfload
Set the payload argument in selfload, as other (non self) payloads, are
going to set a different argument.

Change-Id: I994f604fc4501e0e3b00165819f796b1b8275d8c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25861
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-19 14:28:01 +00:00
Seunghwan Kim 635e512be3 mb/google/poppy/variants/nautilus: Correct USB OC pin configuration
Due to schematic, we need to correct USB OC pin configuration.
 - OC0 for Type-C Port 1
 - OC1 for Type-C Port 0
 - OC2 for Type-A Port
 - OC3 to NC

BUG=NONE
BRANCH=poppy
TEST=emerge-nautilus coreboot

Change-Id: Ic71baef646926cc6aadcc5dda7cb14f00e8d3687
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-18 16:49:30 +00:00