Commit Graph

26088 Commits

Author SHA1 Message Date
Jonathan Neuschäfer ee8780eb78 README: Convert to Markdown
Markdown allows easy conversion to HTML, so this change should make the
GitHub mirror look a little better.

Change-Id: I1a9fde648b8960c01b69fc682f0908c5243d2013
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-09-16 13:01:58 +00:00
Stefan Tauner 03626c0094 sb/intel/i82801dx/Kconfig: remove duplicate SOUTHBRIDGE_INTEL_COMMON
Change-Id: I968ea205e53543f3af68596d6861e25e808057df
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/28508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-09-16 11:10:36 +00:00
Nico Huber c48d883d8b drivers/intel/gma: Fix OpRegion Mailbox3 synchronization
Make XBCM `Serialized` (obvious), and check for the callee clearing the
request bit (we checked only the status for 0 which we potentially wrote
ourselves).

Change-Id: Ic92d525eda8d0a159fa5ddaacf230658d71c1578
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-09-16 10:49:03 +00:00
Hung-Te Lin b4be50c9ca acpi: Call acpi_gen_writeSTA by status from device tree
The device tree now supports 'hidden' and the status can be found in
`struct device.hidden`. A new acpi_device_status() will return the
expected setting of STA from a `struct device`.

BUG=b:72200466
BRANCH=eve
TEST=Builds and boots properly on device eve

Change-Id: I6dc62aff63cc3cb950739398a4dcac21836c9766
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/28567
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-16 08:37:42 +00:00
Hung-Te Lin 936dbe1d06 sconfig: Allow setting device status in device tree
For devices supporting both Linux and Windows, we may find some ACPI
devices that only need drivers in Linux and should not even be shown in
Windows Device Manager UI.

The new 'hidden' keyword in device tree 'device' statement allows
devices sharing same driver to call acpi_gen_writeSTA with different
values.

BUG=b:72200466
BRANCH=eve
TEST=Builds and boots properly on device eve

Change-Id: Iae881a294b122d3a581b456285d2992ab637fb8e
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/28566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-09-16 08:37:36 +00:00
Xiang Wang c1dc7932b5 riscv: don't write to mstatus.XS
XS is a read-only field of mstatus. Unable to be write. So remove this code.

Change-Id: I3ad6b0029900124ac7cce062e668a0ea5a8b2c0e
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/28357
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-16 08:36:10 +00:00
Tristan Shieh 8db79c1386 google/kukui: Configure EMMC
Set up EMMC gpios for payloads.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui

Change-Id: I1e7ee9bfe3a26ed04374e8c74243f48552a1d254
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/28546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-09-16 08:35:44 +00:00
Zhuohao Lee fa61f5aa55 mb/google/poppy/variants/rammus: fix S0ix entering issue
As we don't use the MIPI camera on Rammus, disable SA Imaging Unit and
CIO2 devices to avoid the system failed to enter S0ix.

BUG=b:114502527
BRANCH=master
TEST=On DUT, echo freeze > /sys/power/state
     1. check the S0ix status on EC console
     2. check the value of /sys/kernel/debug/pmc_core/slp_s0_residency_usec

Change-Id: I91629732db01ee534f0ddb67a2b358d725ef810e
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/28543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-16 08:35:29 +00:00
Hung-Te Lin f89c56a54d google/kukui: Notify EC that AP is in S0
We have a pin from AP to EC, called AP_IN_SLEEP_L (SRCLKENA0 on AP side,
pad R23) that is supposed to be high in S0, and low in S3 (and X/don't
care in S5).
This should be set as early as possible in bootblock.

BUG=b:113367227
TEST=make; boots and verified AP_IN_SLEEP_L GPIO is high.
BRANCH=None

Change-Id: Icd59fa366c162e7443b8932a851e65f110f551ab
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/28585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@google.com>
2018-09-16 08:35:12 +00:00
Lijian Zhao f349672966 mb/intel/coffelake_rvp: Implement mainboard memory information
Turn on SOC_INTEL_CANNONLAKE_MEMCFG_INT for coffeelake rvp platform
for easier collabration on newer platform. The setting in memory.c get
from board design itself.

BUG=N/A
TEST=Build and boot up with whiskey lake rvp platform.

Change-Id: I10f3af4bed511153cef4d6f3a93caea57cc4ae90
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28257
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-16 08:34:50 +00:00
Caveh Jalali 6f7db07102 mb/google/poppy: Set UPD CmdTriStateDis for Atlas
This patch sets the MRC UPD CmdTriStateDis for the atlas boards.
Atlas is a LPDDR3 design without RTT for CMD/CTRL.

The original change for
nocturne is I0f593761dcbd121e7e758421af178931b9d78295
mb/google/poppy: Set UPD CmdTriStateDis for Nocturne

BUG=b:111812662

Change-Id: I45b6dd22412c689c8db64f4650e9fa9e87dec2ec
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/28540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-09-16 08:34:34 +00:00
Paul Menzel f47682e586 mb/lenovo: Add Lenovo W500 as clone of Lenovo T400
At ECC 2017 user Bob reports, that an image built for the Lenovo T500
runs on the Lenovo W500 without any issues.

Change-Id: I17fd9725ab85ba2f0c99a70f40e35432265a81c1
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/22226
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-15 16:56:00 +00:00
Philipp Hug 4e7a47350d sifive/hifive-unleashed: enable CBMEM support
Change-Id: I3eacba9c1c20bbfa270dd7a9afabe48ed9092bcc
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28622
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-15 13:54:57 +00:00
Philipp Hug 7c5acd494a soc/sifive: move ram_resource to mainboard
ram_resource is board specific and should be moved there.

Change-Id: I50bd9aaaae39422e565d8bf205a6365c59299df0
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-09-15 13:39:11 +00:00
Ronald G. Minnich b159d5ba8f riscv: add documentation for stages and payloads
Change-Id: Iff522e309e9cf9a31c1c79c24047d83d7fd0b00a
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/28619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-15 12:52:32 +00:00
Richard Spiegel c75f2d8119 arch/x86/acpi_bert_storage.c: Fix coverity error CID 1395706
There are 8 possible BERT context errors, with table ctx_names being a
table to print their names. Thus the table is supposed to have 8 elements,
and indeed it has 8 lines... but some lines are missing commas, and when
compiling it becomes a 5 element table. Add the commas at the appropriate
places.

BUG=b:115719190
TEST=none.

Change-Id: I04a2c82a25fe5f334637053ef81fa6daffb5b9c5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2018-09-15 12:43:26 +00:00
Jonathan Neuschäfer ded91fffb8 arch/riscv: Configure delegation only if S-mode is supported
On the FU540 the bootblock runs on a core without lesser privilege
modes, so the medeleg/mideleg CSRs are not implemented on that core,
leading to a CPU exception when these CSRs are accessed.

Configure medeleg/mideleg only if the misa register indicates that
S-mode is implemented on the executing RISC-V core.

Change-Id: Idad97e42bac2ff438dd233a5d125f93594505d63
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25791
Reviewed-by: Xiang Wang <wxjstz@126.com>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-15 11:53:34 +00:00
Piotr Król 694d18a641 pcengines/apu2: enable IOMMU for all apu2 variants
IOMMU was tested on Xen 4.8 and Linux kernel 4.14.33. Following feature
set is enabled:
(XEN) AMD-Vi: Disabled HAP memory map sharing with IOMMU
(XEN) AMD-Vi: IOMMU Extended Features:
(XEN)  - Peripheral Page Service Request
(XEN)  - Guest Translation
(XEN)  - Invalidate All Command
(XEN)  - Guest APIC supported
(XEN)  - Performance Counters
(XEN) AMD-Vi: IOMMU 0 Enabled.

Change-Id: I6dbfae78849248f3532caa78974c8f2ce61a530d
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-on: https://review.coreboot.org/26116
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-15 11:36:01 +00:00
Timothy Pearson 9ef07d8623 nb/amd/pi/00730F01: Add initial native IVRS support
- Iteration over devices in add_ivrs_device_entries were simplified to
decrease complexity.
- Code was structured to satisfy checkpatch

Change-Id: I1ae789f75363435accd14a1b556e1570f43f94c4
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-on: https://review.coreboot.org/15164
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-15 11:35:51 +00:00
Kyösti Mälkki 03eb8a8515 nb/amd/pi/00730F01: Initialize IOMMU device
Change-Id: I12d3ed35770ee06626f884db23004652084c88c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15186
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-15 11:35:38 +00:00
Arthur Heymans 33fa95cd35 mb/asrock/g41c-gs: Add more buildin PCI devices to the devicetree
Change-Id: I9f7e7d70b850619e34a60fd8e7b16b44c728e9ca
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-09-15 10:31:33 +00:00
Nico Huber f26a7c7687 drivers/intel/gma: Do not rely on CBLV in OpRegion Mailbox3
CBLV is not kept up to date by Linux' i915. We should fix that too,
but it will likely take some years until we can always expect it to
work.

For now read the register values directly. To accomodate that we
are not the only one writing those, revise XBQC() to search for
the closest value in BRIG (instead of a lower equal one) and round
more accurately for better matches.

Change-Id: I4e2d8fa34e75463d4cf7242af3e2c67577cfa2a5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-09-14 20:20:22 +00:00
Jonathan Neuschäfer 6b0102db76 arch/x86/acpigen: Fix comment in _ROM method generator
Commit 24462e6507 ("x86/acpigen: Fix ACPI _ROM method") changed the code
to generate a serialized method, but didn't adjust the comment.

Change-Id: Ie7dbaff13d36f31e9d627609d0f74a4e9fa5a1e9
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-14 20:18:17 +00:00
Nico Huber 9ce59742b7 nb/intel/sandybridge: Don't add SMBIOS Table 17 entries on resume
Change-Id: Icac6e696efa1721933a1963b45d608d9ae735149
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/28589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nathaniel Roach <nroach44@gmail.com>
Reviewed-by: Evgeny Zinoviev <me@ch1p.com>
2018-09-14 20:17:09 +00:00
Nico Huber bb0ab9e531 device/ddr3: Prevent overflow when adding SMBUS Table 17 entries
Change-Id: If84c6849011106b2a50e504b79cda9cd6a3a9cc3
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/28588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-09-14 20:16:45 +00:00
Philipp Hug 26036d9db3 arch/riscv: Only execute on hart 0 for now
Only execute coreboot on hart 0 until synchronisation between hart's is ready.
Change-Id: I2181e79572fbb9cc7bee39a3c2298c0dae6c1658
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-09-14 14:34:09 +00:00
Philipp Hug 2326a284ac riscv: add trampoline in MBR block to support boot mode 1
Add "j pc + 0x0800" at the beginning of the MBR to jump to bootblock.

Tested on hardware:
boot mode 15: works as before
boot mode 1: jump to bootblock works, but bootblock needs to be modified to
move the stack to L2LIM. This will be in a separate commit.

Further changes are needed in the bootblock

Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/27397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-14 14:33:09 +00:00
Julien Viard de Galbert 2912e8e5dc soc/intel/denverton_ns: Enable common block PMC
Mainly update headers to build.

Added option PMC_GLOBAL_RESET_ENABLE_LOCK to remove
function configuring the global reset through PMC base.
On denverton the global reset lock is not in PMC base
but in the PCI registers so this code cannot be shared.

Change-Id: I9ace70862cab63f8355252d034292596c7eab1fd
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/25426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Evandro Luiz Hauenstein <kingsumos@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-14 14:11:03 +00:00
Alexander Couzens 86b8d176e8 ec/lenovo/pmh7: support 9bit address space
The pmh7 has at least a 9bit address space.
The h8s allows to access the 9th address space by using io port
0x15ed as second address register.

The pmh7 is connected via SPI to the h8s. The h8s is acting as
proxy to access the address space.

Change-Id: I0d7ce00950862adf928a88d70afbc33df8b87d9a
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/28196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Evgeny Zinoviev <me@ch1p.com>
2018-09-14 13:50:34 +00:00
Philipp Hug df5e6f64b6 soc/sifive/fu540: Implement uart_platform_refclk for UART divisor calculation
After changing clock from 33.33Mhz to 1Ghz the UART divisor needs to be
recalculated. Return correct tlck frequency in uart_platform_refclk.

Change-Id: I2291e4198cf466a8334211c6c46bc3268fc979a9
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-14 10:41:49 +00:00
Philipp Hug 91595724e7 soc/sifive/fu540: Initialize SDRAM
Based on SiFive bootloader code

Change-Id: I71043ce9e458e25e64da28d53cd36b02d2e22acc
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28604
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-14 10:32:20 +00:00
Ronald G. Minnich 95c331b94b rampayload: Add the linuxcheck payload
The i386.c file uses standard 3f8 UART for some simple diagnostic
prints, and the libpayload console otherwise.

This payload was used to debug Linux as a rampayload and was very helpful
for that work.

Change-Id: I1cce5528780cd825fd91a88137fa70abd9f218e7
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/28600
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-14 09:59:17 +00:00
Philipp Hug 374d992fc8 soc/sifive/fu540: Switch clock to 1GHz in romstage
Invoke clock_init in romstage for SiFive Unleashed.

Change-Id: Ib869762d557e8fdf4c83a53698102df116d80389
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-09-14 09:51:02 +00:00
Philipp Hug c014ef5919 soc/sifive/fu540: create ram_resource with actual memory size
Change-Id: If6af6f679e24e56c79b995de0970d4e6f455e40a
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-09-14 09:29:36 +00:00
Philipp Hug 199b75f58a arch/riscv: provide a monotonic timer
The RISC-V Privileged Architecture specification defines the Machine
Time Registers (mtime and mtimecmp) in section 3.1.15.

Makes it possible to use the generic udelay.
The timer is enabled using RISCV_USE_ARCH_TIMER for the lowrisc,
sifive and ucb soc.

Change-Id: I5139601226e6f89da69e302a10f2fb56b4b24f38
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/27434
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-14 09:28:06 +00:00
Philipp Hug 31dbfbc405 soc/sifive/fu540: add SiFive supplied header files for SDRAM initialization
Add original files from SiFive bootloader.

Change-Id: I8beb75c070a6fac1700dd7644fc4fe9df226e716
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-09-14 09:27:29 +00:00
Ronald G. Minnich 688eec1b97 lint-000-license-headers: add SPDX-License-Identifier: GPL-2.0-or-later
Change-Id: Icbf21b02d3092815bbe876eceea72ebba8dd54da
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/28599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-09-14 08:54:28 +00:00
Karthikeyan Ramasubramanian fa80dfd34f mb/google/octopus: Query the EC for board version
The board version is part of EC's EEPROM, but is not being populated
from EEPROM. Instead a default Kconfig parameter is returned as board
version. Select GOOGLE_SMBIOS_MAINBOARD_VERSION Kconfig item to enable
requesting the EC for board version.

BUG=b:114001972,b:114677884,b:114677887

Change-Id: Ib404a9da35156e197d232088fd7ca69432effbca
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Tested-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/28539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-14 08:36:18 +00:00
Philipp Hug 69acbbfd56 arch/riscv: add missing endian.h header to io.h
Make it uniform as other architectures also include it in io.h

Change-Id: I62c2d909c703f01cdaabdaaba344f82b6746f094
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28601
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-14 08:36:09 +00:00
peichao.wang 211ceb5976 mb/google/octopus: fetch DRAM part number from CBI for phaser after DVT phase
This modification for DVT build and use CBI method
enable all memory particles.

BUG=b:112870780
TEST=verify it under the EVT unit and pre-test EVT
unit(rework RAM ID follow the proposal) respectively.

Change-Id: I488a0652ba348eff9a6d8591b0cfa6ed4fe808aa
Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-14 08:26:04 +00:00
Aaron Durbin 75a62e7648 complier.h: add __always_inline and use it in code base
Add a __always_inline macro that wraps __attribute__((always_inline))
and replace current users with the macro, excluding files under
src/vendorcode.

Change-Id: Ic57e474c1d2ca7cc0405ac677869f78a28d3e529
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/28587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@google.com>
2018-09-14 08:16:37 +00:00
Lijian Zhao cf9ea55473 payloads/tianocore: Add option to use 8254 timer
Change TianoCore payload default to use HPET timer. Add an option to use
8254 timer for legacy platform support.

BUG=N/A.
TEST=Build and boot up into UEFI shell on Whiskey Lake rvp platform.

Change-Id: I857704b0ca128fc9da193ae26a33c7cf89ad7320
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2018-09-13 16:43:36 +00:00
Philipp Hug bdd866e38a soc/sifive/fu540: Get SDRAM controller out of reset
Change-Id: Ifa6faffbaf353379f57e0f80c1c4ca2fc380f874
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-13 15:33:57 +00:00
Philipp Hug 18764a328d soc/sifive/fu540: Update clock settings according SiFive bootloader
The documentation unfortunately doesn't match what SiFive uses in their FSBL.
Use the same values as in FSBL to make DDR RAM work.

Change-Id: I844cc41ed197333adeae495e71ea70b4a9603650
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28582
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-13 15:33:46 +00:00
Philipp Hug 7524400242 uart/sifive: make divisor configurable
The SiFive UART on the HiFive Unleashed uses the tlclk as input clock
which runs at coreclk / 2.

The input frequency is configured in the board code depending on the
current stage. (bootblock + romstage run at 33.33Mhz, ramstage at 1Ghz)

Change-Id: Iaf66723dba3d308f809fde5b05dfc3e43f43bd42
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/27440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-13 15:32:53 +00:00
Nico Huber 3e51d53064 Makefile.inc: Fix dependency tracking of fmap{_config.h,.desc}
GNU make is too smart (or too stupid?) for empty recipes. In the case of
empty recipes, GNU make doesn't consider the target as updated even if
its prerequisites are. So if we told make to rebuild `build/romstage/
lib/cbfs.o` for instance, and the FMAP changed, it rerun the fmaptool
recipe (as a prerequisite) but only considered `cbfs.o` to be updated
by chance.

Just not leaving the recipes empty seems to help here. I seeemed to
remember that it wasn't that easy, but it fixes the issue for me...

Change-Id: Ic7ecb88cf7df7f2488defd47ea02255fc10a67e9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-09-13 13:58:29 +00:00
Angel Pons 392e886552 util/superiotool: Add Winbond W83667HG register dump
This SuperIO is supported by coreboot and used in two Asus boards. However,
superiotool was lacking a register dump for this chip. Add the corresponding
data from datasheet W83667HG-B revision 1.3 into superiotool.

The SuperIO's datasheet was obtained by requesting it to Nuvoton.

Change-Id: Ie51dc492c761d9c3d4b6100017bb730b1ae6d1e0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-09-13 13:30:46 +00:00
Angel Pons cde835e39e src/mainboard/*/*: Set Mini-ITX boards' category to "mini"
Change-Id: I637792d3bf22d2e452144d44ba03cfe45b47501d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-09-13 08:29:16 +00:00
Angel Pons a52016cc46 src/*/intel: introduce warning when building with no IFD
Add a warning as suggested in patch CB:28233 with the
"CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED" option.

Change-Id: I42b6b336bb519f3d18b5a41eb20b380636ff5819
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-09-13 08:25:59 +00:00
Stefan Tauner ef8b95745f src/*/intel/: clarify Kconfig options regarding IFD
HAVE_INTEL_FIRMWARE is used to enable certain options that rely on a valid
Inter Flash Descriptor to exist. It does *not* identify platforms or boards
that are capable of running in descriptor mode if it's valid.
Refine the help text to make this clear.

Introduce a new option INTEL_DESCRIPTOR_MODE_CAPABLE that does simply
declare that IFD is supported by the platform. Select this value everywhere
instead of the HAVE_INTEL_FIRMWARE and default HAVE_INTEL_FIRMWARE to
y if INTEL_DESCRIPTOR_MODE_CAPABLE is selected.

Move the QEMU Q35 special case (deselection of HAVE_INTEL_FIRMWARE) to
the mainboard directory.

Change-Id: I4791fce03982bf0443bf0b8e26d9f4f06c6f2060
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/28371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-13 08:25:31 +00:00